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* [Qemu-devel] [Bug 696094] [NEW] TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working
@ 2010-12-31 20:30 Frikkie Thirion
  2010-12-31 20:30 ` [Qemu-devel] [Bug 696094] " Frikkie Thirion
                   ` (10 more replies)
  0 siblings, 11 replies; 13+ messages in thread
From: Frikkie Thirion @ 2010-12-31 20:30 UTC (permalink / raw)
  To: qemu-devel

Public bug reported:

I've tried to create a small project that uses the CMSIS as base library.
The problem is that the SysTick_interrupt_handler() doesn't get executed when the systick event is detected in QEMU. Furthermore, it seems asif QEMU gets stuck in an endless loop. QEMU doesn't respond to Ctrl-C on the command line and the GDB session also stalls. 'kill -9' is the only way to stop QEMU.

It seems asif the initialisation of the NVIC works fine. I've traced the function calls in QEMU as follows:
stellaris.c: stellaris_init() - Perform generic armv7 init: armv7m_init()
   armv7m.c: armv7m_init() - Create and init the nvic:
                               nvic = qdev_create(NULL, "armv7m_nvic");
                               env->nvic = nvic;
                               qdev_init_nofail(nvic);
                           - Configure the programmable interrupt controller:
                               Call: arm_pic_init_cpu() 
                                        qemu_allocate_irqs(arm_pic_cpu_handler)
                           - Initialise 64 interrupt structures.

The following call sequence is observed when the systick event occur:
armv7m_nvic.c: systick_timer_tick(): set pending interrupt
armv7m_nvic.c: armv7m_nvic_set_pending() for irq:15
  arm_gic.c: gic_set_pending_private(): GIC_SET_PENDING(15,)
    arm_gic.c: gic_update() - Raise IRQ with qemu_set_irq()
       irq.c: eqmu_set_irq() - Call the irq->handler 
                               -- I assume the irq handler is 'arm_pic_cpu_handler()',
                                  since that was passed as the parameter when
                                  qemu_allocate_irqs() was called in ...
          arm_pic.c: arm_pic_cpu_handler() - After evaluation, call cpu_interrupt()
             exec.c: cpu_interrupt() is called.     

The tools that were used during the testing of this project:
  GCC: Codesourcery ARM eabi 2010q3
  QEMU: Checked out on 31/12/2010 - Last commit: 0fcec41eec0432c77645b4a407d3a3e030c4abc4
The project files are attached, for reproducing of the errors.
   Note: The CMSIS wants to perform byte accesses to the NVIC. For the Cortex-M3, unaligned 8 bit and 16 bit accesses are allowed. The current QEMU implementation doesn't yet cater for it. As a work around, updated versions of
arm_gic.c armv7m_nvic.h armv7m_nvic.c is also included.

Launch project with: go_gdb.sh
Attach debugger with: arm-none-eabi-gdbtui --command=gdbCommands_tui
(s = step, n = next, c = continue, Ctrl-C = stop, print <variable> to look at variable contents)

** Affects: qemu
     Importance: Undecided
         Status: New

-- 
You received this bug notification because you are a member of qemu-
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https://bugs.launchpad.net/bugs/696094

Title:
  TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working

Status in QEMU:
  New

Bug description:
  I've tried to create a small project that uses the CMSIS as base library.
The problem is that the SysTick_interrupt_handler() doesn't get executed when the systick event is detected in QEMU. Furthermore, it seems asif QEMU gets stuck in an endless loop. QEMU doesn't respond to Ctrl-C on the command line and the GDB session also stalls. 'kill -9' is the only way to stop QEMU.

It seems asif the initialisation of the NVIC works fine. I've traced the function calls in QEMU as follows:
stellaris.c: stellaris_init() - Perform generic armv7 init: armv7m_init()
   armv7m.c: armv7m_init() - Create and init the nvic:
                               nvic = qdev_create(NULL, "armv7m_nvic");
                               env->nvic = nvic;
                               qdev_init_nofail(nvic);
                           - Configure the programmable interrupt controller:
                               Call: arm_pic_init_cpu() 
                                        qemu_allocate_irqs(arm_pic_cpu_handler)
                           - Initialise 64 interrupt structures.

The following call sequence is observed when the systick event occur:
armv7m_nvic.c: systick_timer_tick(): set pending interrupt
armv7m_nvic.c: armv7m_nvic_set_pending() for irq:15
  arm_gic.c: gic_set_pending_private(): GIC_SET_PENDING(15,)
    arm_gic.c: gic_update() - Raise IRQ with qemu_set_irq()
       irq.c: eqmu_set_irq() - Call the irq->handler 
                               -- I assume the irq handler is 'arm_pic_cpu_handler()',
                                  since that was passed as the parameter when
                                  qemu_allocate_irqs() was called in ...
          arm_pic.c: arm_pic_cpu_handler() - After evaluation, call cpu_interrupt()
             exec.c: cpu_interrupt() is called.     

The tools that were used during the testing of this project:
  GCC: Codesourcery ARM eabi 2010q3
  QEMU: Checked out on 31/12/2010 - Last commit: 0fcec41eec0432c77645b4a407d3a3e030c4abc4
The project files are attached, for reproducing of the errors.
   Note: The CMSIS wants to perform byte accesses to the NVIC. For the Cortex-M3, unaligned 8 bit and 16 bit accesses are allowed. The current QEMU implementation doesn't yet cater for it. As a work around, updated versions of
arm_gic.c armv7m_nvic.h armv7m_nvic.c is also included.

Launch project with: go_gdb.sh
Attach debugger with: arm-none-eabi-gdbtui --command=gdbCommands_tui
(s = step, n = next, c = continue, Ctrl-C = stop, print <variable> to look at variable contents)

^ permalink raw reply	[flat|nested] 13+ messages in thread

* [Qemu-devel] [Bug 696094] Re: TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working
  2010-12-31 20:30 [Qemu-devel] [Bug 696094] [NEW] TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working Frikkie Thirion
@ 2010-12-31 20:30 ` Frikkie Thirion
  2011-08-01 10:16 ` ARUNKUMAR VASUDEVAN
                   ` (9 subsequent siblings)
  10 siblings, 0 replies; 13+ messages in thread
From: Frikkie Thirion @ 2010-12-31 20:30 UTC (permalink / raw)
  To: qemu-devel


** Attachment added: "Project demonstrating that SysTick interrupt doesn't execute correctly."
   https://bugs.launchpad.net/bugs/696094/+attachment/1780598/+files/project.tar.bz2

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/696094

Title:
  TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working

Status in QEMU:
  New

Bug description:
  I've tried to create a small project that uses the CMSIS as base library.
The problem is that the SysTick_interrupt_handler() doesn't get executed when the systick event is detected in QEMU. Furthermore, it seems asif QEMU gets stuck in an endless loop. QEMU doesn't respond to Ctrl-C on the command line and the GDB session also stalls. 'kill -9' is the only way to stop QEMU.

It seems asif the initialisation of the NVIC works fine. I've traced the function calls in QEMU as follows:
stellaris.c: stellaris_init() - Perform generic armv7 init: armv7m_init()
   armv7m.c: armv7m_init() - Create and init the nvic:
                               nvic = qdev_create(NULL, "armv7m_nvic");
                               env->nvic = nvic;
                               qdev_init_nofail(nvic);
                           - Configure the programmable interrupt controller:
                               Call: arm_pic_init_cpu() 
                                        qemu_allocate_irqs(arm_pic_cpu_handler)
                           - Initialise 64 interrupt structures.

The following call sequence is observed when the systick event occur:
armv7m_nvic.c: systick_timer_tick(): set pending interrupt
armv7m_nvic.c: armv7m_nvic_set_pending() for irq:15
  arm_gic.c: gic_set_pending_private(): GIC_SET_PENDING(15,)
    arm_gic.c: gic_update() - Raise IRQ with qemu_set_irq()
       irq.c: eqmu_set_irq() - Call the irq->handler 
                               -- I assume the irq handler is 'arm_pic_cpu_handler()',
                                  since that was passed as the parameter when
                                  qemu_allocate_irqs() was called in ...
          arm_pic.c: arm_pic_cpu_handler() - After evaluation, call cpu_interrupt()
             exec.c: cpu_interrupt() is called.     

The tools that were used during the testing of this project:
  GCC: Codesourcery ARM eabi 2010q3
  QEMU: Checked out on 31/12/2010 - Last commit: 0fcec41eec0432c77645b4a407d3a3e030c4abc4
The project files are attached, for reproducing of the errors.
   Note: The CMSIS wants to perform byte accesses to the NVIC. For the Cortex-M3, unaligned 8 bit and 16 bit accesses are allowed. The current QEMU implementation doesn't yet cater for it. As a work around, updated versions of
arm_gic.c armv7m_nvic.h armv7m_nvic.c is also included.

Launch project with: go_gdb.sh
Attach debugger with: arm-none-eabi-gdbtui --command=gdbCommands_tui
(s = step, n = next, c = continue, Ctrl-C = stop, print <variable> to look at variable contents)

^ permalink raw reply	[flat|nested] 13+ messages in thread

* [Qemu-devel] [Bug 696094] Re: TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working
  2010-12-31 20:30 [Qemu-devel] [Bug 696094] [NEW] TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working Frikkie Thirion
  2010-12-31 20:30 ` [Qemu-devel] [Bug 696094] " Frikkie Thirion
@ 2011-08-01 10:16 ` ARUNKUMAR VASUDEVAN
  2011-12-16 19:28   ` Sebastian Huber
  2011-08-01 10:26 ` ARUNKUMAR VASUDEVAN
                   ` (8 subsequent siblings)
  10 siblings, 1 reply; 13+ messages in thread
From: ARUNKUMAR VASUDEVAN @ 2011-08-01 10:16 UTC (permalink / raw)
  To: qemu-devel

I also faced the same problem. I emulated cortex m3 in qemu ( $qemu-
system-arm -M lm3s811evb  -monitor stdio -kernel out.elf -s -S -gdb
tcp::53333 ) and arm-none-linux-gnueabi-gdb --command=./gdbinit

and my gdbinit is below
set verbose on
set solib-absolute-prefix nonexistantpath
set solib-search-path /root/CodeSourcery/Sourcery_G++_Lite/arm-none-linux-gnueabi/libc/lib
file out.elf
target remote localhost:53333
set remote exec-file out.elf

I didn't use any standard library. Instead I wrote a simple code
referring the cortex-m3 manual. The bug section is given below.

/**** code part *****/
#define         SysTick         ( (SysTickTemplate*) 0xE000E010 )  // as in the datasheet


typedef struct {

  volatile unsigned int CTRL;

  volatile unsigned int LOAD;

  volatile unsigned int VAL;

  volatile unsigned int CALIB;

} SysTickTemplate;


init() 
{
  SysTick->CTRL = 0x4;

  SysTick->LOAD = 8000000;  /* Frequency of 1 Hz */

  SysTick->CTRL |= 1; /* Enable counter */

  SysTick->CTRL |= 2; /* Enable interrupts */

  /* here it hangs, even ctrl+C wont work here */

   int c = 0;

   /* codes....*/
}

The same program I used to port into LPC1343 with a SysTickHandler() to
toggle an LED and there it worked.

Any help is appreciated,

Arun

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/696094

Title:
  TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not
  working

Status in QEMU:
  Incomplete

Bug description:
  I've tried to create a small project that uses the CMSIS as base library.
  The problem is that the SysTick_interrupt_handler() doesn't get executed when the systick event is detected in QEMU. Furthermore, it seems asif QEMU gets stuck in an endless loop. QEMU doesn't respond to Ctrl-C on the command line and the GDB session also stalls. 'kill -9' is the only way to stop QEMU.

  It seems asif the initialisation of the NVIC works fine. I've traced the function calls in QEMU as follows:
  stellaris.c: stellaris_init() - Perform generic armv7 init: armv7m_init()
     armv7m.c: armv7m_init() - Create and init the nvic:
                                 nvic = qdev_create(NULL, "armv7m_nvic");
                                 env->nvic = nvic;
                                 qdev_init_nofail(nvic);
                             - Configure the programmable interrupt controller:
                                 Call: arm_pic_init_cpu() 
                                          qemu_allocate_irqs(arm_pic_cpu_handler)
                             - Initialise 64 interrupt structures.

  The following call sequence is observed when the systick event occur:
  armv7m_nvic.c: systick_timer_tick(): set pending interrupt
  armv7m_nvic.c: armv7m_nvic_set_pending() for irq:15
    arm_gic.c: gic_set_pending_private(): GIC_SET_PENDING(15,)
      arm_gic.c: gic_update() - Raise IRQ with qemu_set_irq()
         irq.c: eqmu_set_irq() - Call the irq->handler 
                                 -- I assume the irq handler is 'arm_pic_cpu_handler()',
                                    since that was passed as the parameter when
                                    qemu_allocate_irqs() was called in ...
            arm_pic.c: arm_pic_cpu_handler() - After evaluation, call cpu_interrupt()
               exec.c: cpu_interrupt() is called.     

  The tools that were used during the testing of this project:
    GCC: Codesourcery ARM eabi 2010q3
    QEMU: Checked out on 31/12/2010 - Last commit: 0fcec41eec0432c77645b4a407d3a3e030c4abc4
  The project files are attached, for reproducing of the errors.
     Note: The CMSIS wants to perform byte accesses to the NVIC. For the Cortex-M3, unaligned 8 bit and 16 bit accesses are allowed. The current QEMU implementation doesn't yet cater for it. As a work around, updated versions of
  arm_gic.c armv7m_nvic.h armv7m_nvic.c is also included.

  Launch project with: go_gdb.sh
  Attach debugger with: arm-none-eabi-gdbtui --command=gdbCommands_tui
  (s = step, n = next, c = continue, Ctrl-C = stop, print <variable> to look at variable contents)

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/696094/+subscriptions

^ permalink raw reply	[flat|nested] 13+ messages in thread

* [Qemu-devel] [Bug 696094] Re: TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working
  2010-12-31 20:30 [Qemu-devel] [Bug 696094] [NEW] TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working Frikkie Thirion
  2010-12-31 20:30 ` [Qemu-devel] [Bug 696094] " Frikkie Thirion
  2011-08-01 10:16 ` ARUNKUMAR VASUDEVAN
@ 2011-08-01 10:26 ` ARUNKUMAR VASUDEVAN
  2011-08-01 11:28 ` Peter Maydell
                   ` (7 subsequent siblings)
  10 siblings, 0 replies; 13+ messages in thread
From: ARUNKUMAR VASUDEVAN @ 2011-08-01 10:26 UTC (permalink / raw)
  To: qemu-devel

** Changed in: qemu
       Status: New => Incomplete

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/696094

Title:
  TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not
  working

Status in QEMU:
  Incomplete

Bug description:
  I've tried to create a small project that uses the CMSIS as base library.
  The problem is that the SysTick_interrupt_handler() doesn't get executed when the systick event is detected in QEMU. Furthermore, it seems asif QEMU gets stuck in an endless loop. QEMU doesn't respond to Ctrl-C on the command line and the GDB session also stalls. 'kill -9' is the only way to stop QEMU.

  It seems asif the initialisation of the NVIC works fine. I've traced the function calls in QEMU as follows:
  stellaris.c: stellaris_init() - Perform generic armv7 init: armv7m_init()
     armv7m.c: armv7m_init() - Create and init the nvic:
                                 nvic = qdev_create(NULL, "armv7m_nvic");
                                 env->nvic = nvic;
                                 qdev_init_nofail(nvic);
                             - Configure the programmable interrupt controller:
                                 Call: arm_pic_init_cpu() 
                                          qemu_allocate_irqs(arm_pic_cpu_handler)
                             - Initialise 64 interrupt structures.

  The following call sequence is observed when the systick event occur:
  armv7m_nvic.c: systick_timer_tick(): set pending interrupt
  armv7m_nvic.c: armv7m_nvic_set_pending() for irq:15
    arm_gic.c: gic_set_pending_private(): GIC_SET_PENDING(15,)
      arm_gic.c: gic_update() - Raise IRQ with qemu_set_irq()
         irq.c: eqmu_set_irq() - Call the irq->handler 
                                 -- I assume the irq handler is 'arm_pic_cpu_handler()',
                                    since that was passed as the parameter when
                                    qemu_allocate_irqs() was called in ...
            arm_pic.c: arm_pic_cpu_handler() - After evaluation, call cpu_interrupt()
               exec.c: cpu_interrupt() is called.     

  The tools that were used during the testing of this project:
    GCC: Codesourcery ARM eabi 2010q3
    QEMU: Checked out on 31/12/2010 - Last commit: 0fcec41eec0432c77645b4a407d3a3e030c4abc4
  The project files are attached, for reproducing of the errors.
     Note: The CMSIS wants to perform byte accesses to the NVIC. For the Cortex-M3, unaligned 8 bit and 16 bit accesses are allowed. The current QEMU implementation doesn't yet cater for it. As a work around, updated versions of
  arm_gic.c armv7m_nvic.h armv7m_nvic.c is also included.

  Launch project with: go_gdb.sh
  Attach debugger with: arm-none-eabi-gdbtui --command=gdbCommands_tui
  (s = step, n = next, c = continue, Ctrl-C = stop, print <variable> to look at variable contents)

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/696094/+subscriptions

^ permalink raw reply	[flat|nested] 13+ messages in thread

* [Qemu-devel] [Bug 696094] Re: TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working
  2010-12-31 20:30 [Qemu-devel] [Bug 696094] [NEW] TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working Frikkie Thirion
                   ` (2 preceding siblings ...)
  2011-08-01 10:26 ` ARUNKUMAR VASUDEVAN
@ 2011-08-01 11:28 ` Peter Maydell
  2011-12-11 16:56 ` Petteri Aimonen
                   ` (6 subsequent siblings)
  10 siblings, 0 replies; 13+ messages in thread
From: Peter Maydell @ 2011-08-01 11:28 UTC (permalink / raw)
  To: qemu-devel

** Changed in: qemu
       Status: Incomplete => New

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/696094

Title:
  TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not
  working

Status in QEMU:
  New

Bug description:
  I've tried to create a small project that uses the CMSIS as base library.
  The problem is that the SysTick_interrupt_handler() doesn't get executed when the systick event is detected in QEMU. Furthermore, it seems asif QEMU gets stuck in an endless loop. QEMU doesn't respond to Ctrl-C on the command line and the GDB session also stalls. 'kill -9' is the only way to stop QEMU.

  It seems asif the initialisation of the NVIC works fine. I've traced the function calls in QEMU as follows:
  stellaris.c: stellaris_init() - Perform generic armv7 init: armv7m_init()
     armv7m.c: armv7m_init() - Create and init the nvic:
                                 nvic = qdev_create(NULL, "armv7m_nvic");
                                 env->nvic = nvic;
                                 qdev_init_nofail(nvic);
                             - Configure the programmable interrupt controller:
                                 Call: arm_pic_init_cpu() 
                                          qemu_allocate_irqs(arm_pic_cpu_handler)
                             - Initialise 64 interrupt structures.

  The following call sequence is observed when the systick event occur:
  armv7m_nvic.c: systick_timer_tick(): set pending interrupt
  armv7m_nvic.c: armv7m_nvic_set_pending() for irq:15
    arm_gic.c: gic_set_pending_private(): GIC_SET_PENDING(15,)
      arm_gic.c: gic_update() - Raise IRQ with qemu_set_irq()
         irq.c: eqmu_set_irq() - Call the irq->handler 
                                 -- I assume the irq handler is 'arm_pic_cpu_handler()',
                                    since that was passed as the parameter when
                                    qemu_allocate_irqs() was called in ...
            arm_pic.c: arm_pic_cpu_handler() - After evaluation, call cpu_interrupt()
               exec.c: cpu_interrupt() is called.     

  The tools that were used during the testing of this project:
    GCC: Codesourcery ARM eabi 2010q3
    QEMU: Checked out on 31/12/2010 - Last commit: 0fcec41eec0432c77645b4a407d3a3e030c4abc4
  The project files are attached, for reproducing of the errors.
     Note: The CMSIS wants to perform byte accesses to the NVIC. For the Cortex-M3, unaligned 8 bit and 16 bit accesses are allowed. The current QEMU implementation doesn't yet cater for it. As a work around, updated versions of
  arm_gic.c armv7m_nvic.h armv7m_nvic.c is also included.

  Launch project with: go_gdb.sh
  Attach debugger with: arm-none-eabi-gdbtui --command=gdbCommands_tui
  (s = step, n = next, c = continue, Ctrl-C = stop, print <variable> to look at variable contents)

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/696094/+subscriptions

^ permalink raw reply	[flat|nested] 13+ messages in thread

* [Qemu-devel] [Bug 696094] Re: TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working
  2010-12-31 20:30 [Qemu-devel] [Bug 696094] [NEW] TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working Frikkie Thirion
                   ` (3 preceding siblings ...)
  2011-08-01 11:28 ` Peter Maydell
@ 2011-12-11 16:56 ` Petteri Aimonen
  2011-12-11 18:57 ` Peter Maydell
                   ` (5 subsequent siblings)
  10 siblings, 0 replies; 13+ messages in thread
From: Petteri Aimonen @ 2011-12-11 16:56 UTC (permalink / raw)
  To: qemu-devel

I think the problem is line 53 in qemu-linaro/hw/armv7m_nvic.c:
int system_clock_scale;

This variable is initialized under some conditions from the Stellaris
peripheral emulation code, but apparently your code does not trigger
this initialization. It then uses the default value of 0, and gets into
an infinite loop.

I suggest that the line be changed to:
int system_clock_scale = 1;

This not only prevents the crash, but has a side benefit of being able to use the SysTick timer even without other peripherals, like this:
qemu-system-arm -cpu cortex-m3 -nographic -monitor null -serial null -semihosting -kernel test.elf
-device armv7m_nvic -icount 1

I still get hangs by messing around with the -icount parameter, but it
is a different bug - ctrl-C gets you out of those hangs.

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/696094

Title:
  TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not
  working

Status in QEMU:
  New

Bug description:
  I've tried to create a small project that uses the CMSIS as base library.
  The problem is that the SysTick_interrupt_handler() doesn't get executed when the systick event is detected in QEMU. Furthermore, it seems asif QEMU gets stuck in an endless loop. QEMU doesn't respond to Ctrl-C on the command line and the GDB session also stalls. 'kill -9' is the only way to stop QEMU.

  It seems asif the initialisation of the NVIC works fine. I've traced the function calls in QEMU as follows:
  stellaris.c: stellaris_init() - Perform generic armv7 init: armv7m_init()
     armv7m.c: armv7m_init() - Create and init the nvic:
                                 nvic = qdev_create(NULL, "armv7m_nvic");
                                 env->nvic = nvic;
                                 qdev_init_nofail(nvic);
                             - Configure the programmable interrupt controller:
                                 Call: arm_pic_init_cpu() 
                                          qemu_allocate_irqs(arm_pic_cpu_handler)
                             - Initialise 64 interrupt structures.

  The following call sequence is observed when the systick event occur:
  armv7m_nvic.c: systick_timer_tick(): set pending interrupt
  armv7m_nvic.c: armv7m_nvic_set_pending() for irq:15
    arm_gic.c: gic_set_pending_private(): GIC_SET_PENDING(15,)
      arm_gic.c: gic_update() - Raise IRQ with qemu_set_irq()
         irq.c: eqmu_set_irq() - Call the irq->handler 
                                 -- I assume the irq handler is 'arm_pic_cpu_handler()',
                                    since that was passed as the parameter when
                                    qemu_allocate_irqs() was called in ...
            arm_pic.c: arm_pic_cpu_handler() - After evaluation, call cpu_interrupt()
               exec.c: cpu_interrupt() is called.     

  The tools that were used during the testing of this project:
    GCC: Codesourcery ARM eabi 2010q3
    QEMU: Checked out on 31/12/2010 - Last commit: 0fcec41eec0432c77645b4a407d3a3e030c4abc4
  The project files are attached, for reproducing of the errors.
     Note: The CMSIS wants to perform byte accesses to the NVIC. For the Cortex-M3, unaligned 8 bit and 16 bit accesses are allowed. The current QEMU implementation doesn't yet cater for it. As a work around, updated versions of
  arm_gic.c armv7m_nvic.h armv7m_nvic.c is also included.

  Launch project with: go_gdb.sh
  Attach debugger with: arm-none-eabi-gdbtui --command=gdbCommands_tui
  (s = step, n = next, c = continue, Ctrl-C = stop, print <variable> to look at variable contents)

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/696094/+subscriptions

^ permalink raw reply	[flat|nested] 13+ messages in thread

* [Qemu-devel] [Bug 696094] Re: TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working
  2010-12-31 20:30 [Qemu-devel] [Bug 696094] [NEW] TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working Frikkie Thirion
                   ` (4 preceding siblings ...)
  2011-12-11 16:56 ` Petteri Aimonen
@ 2011-12-11 18:57 ` Peter Maydell
  2011-12-15 18:56 ` Peter Maydell
                   ` (4 subsequent siblings)
  10 siblings, 0 replies; 13+ messages in thread
From: Peter Maydell @ 2011-12-11 18:57 UTC (permalink / raw)
  To: qemu-devel

ssys_reset() should be calling  ssys_calculate_system_clock(). (We
should probably use a saner default value, though. Or treat
system_clock_scale == 0 as "this board doesn't provide an external clock
reference". And do we really have the sense right on the
SYSTICKX_CLKSOURCE flag?)

> qemu-system-arm -cpu cortex-m3 -nographic -monitor null -serial null
-semihosting -kernel test.elf -device armv7m_nvic -icount 1

This is a nonsensical command line since it will try to instantiate an
Integrator board model with a Cortex-M3 CPU.  It's not possible to
correctly wire up the armv7m_nvic device from the command line, in fact,
so any qemu command line that tries to do so is inherently broken; to
the extent that it works this will be purely by fluke.

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/696094

Title:
  TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not
  working

Status in QEMU:
  New

Bug description:
  I've tried to create a small project that uses the CMSIS as base library.
  The problem is that the SysTick_interrupt_handler() doesn't get executed when the systick event is detected in QEMU. Furthermore, it seems asif QEMU gets stuck in an endless loop. QEMU doesn't respond to Ctrl-C on the command line and the GDB session also stalls. 'kill -9' is the only way to stop QEMU.

  It seems asif the initialisation of the NVIC works fine. I've traced the function calls in QEMU as follows:
  stellaris.c: stellaris_init() - Perform generic armv7 init: armv7m_init()
     armv7m.c: armv7m_init() - Create and init the nvic:
                                 nvic = qdev_create(NULL, "armv7m_nvic");
                                 env->nvic = nvic;
                                 qdev_init_nofail(nvic);
                             - Configure the programmable interrupt controller:
                                 Call: arm_pic_init_cpu() 
                                          qemu_allocate_irqs(arm_pic_cpu_handler)
                             - Initialise 64 interrupt structures.

  The following call sequence is observed when the systick event occur:
  armv7m_nvic.c: systick_timer_tick(): set pending interrupt
  armv7m_nvic.c: armv7m_nvic_set_pending() for irq:15
    arm_gic.c: gic_set_pending_private(): GIC_SET_PENDING(15,)
      arm_gic.c: gic_update() - Raise IRQ with qemu_set_irq()
         irq.c: eqmu_set_irq() - Call the irq->handler 
                                 -- I assume the irq handler is 'arm_pic_cpu_handler()',
                                    since that was passed as the parameter when
                                    qemu_allocate_irqs() was called in ...
            arm_pic.c: arm_pic_cpu_handler() - After evaluation, call cpu_interrupt()
               exec.c: cpu_interrupt() is called.     

  The tools that were used during the testing of this project:
    GCC: Codesourcery ARM eabi 2010q3
    QEMU: Checked out on 31/12/2010 - Last commit: 0fcec41eec0432c77645b4a407d3a3e030c4abc4
  The project files are attached, for reproducing of the errors.
     Note: The CMSIS wants to perform byte accesses to the NVIC. For the Cortex-M3, unaligned 8 bit and 16 bit accesses are allowed. The current QEMU implementation doesn't yet cater for it. As a work around, updated versions of
  arm_gic.c armv7m_nvic.h armv7m_nvic.c is also included.

  Launch project with: go_gdb.sh
  Attach debugger with: arm-none-eabi-gdbtui --command=gdbCommands_tui
  (s = step, n = next, c = continue, Ctrl-C = stop, print <variable> to look at variable contents)

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/696094/+subscriptions

^ permalink raw reply	[flat|nested] 13+ messages in thread

* [Qemu-devel] [Bug 696094] Re: TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working
  2010-12-31 20:30 [Qemu-devel] [Bug 696094] [NEW] TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working Frikkie Thirion
                   ` (5 preceding siblings ...)
  2011-12-11 18:57 ` Peter Maydell
@ 2011-12-15 18:56 ` Peter Maydell
  2011-12-18 14:25 ` Peter Maydell
                   ` (3 subsequent siblings)
  10 siblings, 0 replies; 13+ messages in thread
From: Peter Maydell @ 2011-12-15 18:56 UTC (permalink / raw)
  To: qemu-devel

NB: the attached project fails for me like this:
qemu: hardware error: gic_dist_writeb: Bad offset d23

CPU #0:
R00=ffffffff R01=e000ed00 R02=000000e0 R03=e000ed0b
R04=00000000 R05=00000000 R06=00000000 R07=200004bb
R08=00000000 R09=00000000 R10=00000000 R11=00000000
R12=00000000 R13=200004bb R14=000003bd R15=00000338
PSR=80000173 N--- T svc32

This is because we don't support byte wide accesses to the SHPR*
registers. (The error message refers to the GIC because we currently map
the whole of that area of address space as part of the GIC and then have
it redirect some areas to code in arm7m_nvic.c. That should probably be
cleaned up.)

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/696094

Title:
  TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not
  working

Status in QEMU:
  New

Bug description:
  I've tried to create a small project that uses the CMSIS as base library.
  The problem is that the SysTick_interrupt_handler() doesn't get executed when the systick event is detected in QEMU. Furthermore, it seems asif QEMU gets stuck in an endless loop. QEMU doesn't respond to Ctrl-C on the command line and the GDB session also stalls. 'kill -9' is the only way to stop QEMU.

  It seems asif the initialisation of the NVIC works fine. I've traced the function calls in QEMU as follows:
  stellaris.c: stellaris_init() - Perform generic armv7 init: armv7m_init()
     armv7m.c: armv7m_init() - Create and init the nvic:
                                 nvic = qdev_create(NULL, "armv7m_nvic");
                                 env->nvic = nvic;
                                 qdev_init_nofail(nvic);
                             - Configure the programmable interrupt controller:
                                 Call: arm_pic_init_cpu() 
                                          qemu_allocate_irqs(arm_pic_cpu_handler)
                             - Initialise 64 interrupt structures.

  The following call sequence is observed when the systick event occur:
  armv7m_nvic.c: systick_timer_tick(): set pending interrupt
  armv7m_nvic.c: armv7m_nvic_set_pending() for irq:15
    arm_gic.c: gic_set_pending_private(): GIC_SET_PENDING(15,)
      arm_gic.c: gic_update() - Raise IRQ with qemu_set_irq()
         irq.c: eqmu_set_irq() - Call the irq->handler 
                                 -- I assume the irq handler is 'arm_pic_cpu_handler()',
                                    since that was passed as the parameter when
                                    qemu_allocate_irqs() was called in ...
            arm_pic.c: arm_pic_cpu_handler() - After evaluation, call cpu_interrupt()
               exec.c: cpu_interrupt() is called.     

  The tools that were used during the testing of this project:
    GCC: Codesourcery ARM eabi 2010q3
    QEMU: Checked out on 31/12/2010 - Last commit: 0fcec41eec0432c77645b4a407d3a3e030c4abc4
  The project files are attached, for reproducing of the errors.
     Note: The CMSIS wants to perform byte accesses to the NVIC. For the Cortex-M3, unaligned 8 bit and 16 bit accesses are allowed. The current QEMU implementation doesn't yet cater for it. As a work around, updated versions of
  arm_gic.c armv7m_nvic.h armv7m_nvic.c is also included.

  Launch project with: go_gdb.sh
  Attach debugger with: arm-none-eabi-gdbtui --command=gdbCommands_tui
  (s = step, n = next, c = continue, Ctrl-C = stop, print <variable> to look at variable contents)

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/696094/+subscriptions

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [Qemu-devel] [Bug 696094] Re: TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working
  2011-08-01 10:16 ` ARUNKUMAR VASUDEVAN
@ 2011-12-16 19:28   ` Sebastian Huber
  0 siblings, 0 replies; 13+ messages in thread
From: Sebastian Huber @ 2011-12-16 19:28 UTC (permalink / raw)
  To: qemu-devel

[-- Attachment #1: Type: text/plain, Size: 560 bytes --]

Hello,

I am able to run the RTEMS real time system on the TI Stellaris LM3S6965 
with a working system tick. I used the attached local hacks and patches 
with the Qemu development branch from today.

Have a nice day!

-- 
Sebastian Huber, embedded brains GmbH

Address : Obere Lagerstr. 30, D-82178 Puchheim, Germany
Phone   : +49 89 18 90 80 79-6
Fax     : +49 89 18 90 80 79-9
E-Mail  : sebastian.huber@embedded-brains.de
PGP     : Public key available on request.

Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.


[-- Attachment #2: 0001-target-arm-Fixed-ARMv7-M-SHPR-access.patch --]
[-- Type: text/x-patch, Size: 4071 bytes --]

>From 0c8e700376cec0c7b5a70f999b5e286efc321423 Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Fri, 16 Dec 2011 19:46:40 +0100
Subject: [PATCH 1/4] target-arm: Fixed ARMv7-M SHPR access

According to "ARMv7-M Architecture Reference Manual" issue D section
"B3.2.10 System Handler Prioriy Register 1, SHPR1", "B3.2.11 System
Handler Prioriy Register 2, SHPR2", and "B3.2.12 System Handler Prioriy
Register 3, SHPR3".

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
---
 hw/arm_gic.c     |   16 ++++++++++++++--
 hw/armv7m_nvic.c |   19 -------------------
 2 files changed, 14 insertions(+), 21 deletions(-)

diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 9b52119..5139d95 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -356,6 +356,11 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
             if (GIC_TEST_TRIGGER(irq + i))
                 res |= (2 << (i * 2));
         }
+#else
+    } else if (0xd18 <= offset && offset < 0xd24) {
+        /* System Handler Priority.  */
+        irq = offset - 0xd14;
+        res = GIC_GET_PRIORITY(irq, cpu);
 #endif
     } else if (offset < 0xfe0) {
         goto bad_reg;
@@ -387,7 +392,8 @@ static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
     gic_state *s = (gic_state *)opaque;
     uint32_t addr;
     addr = offset;
-    if (addr < 0x100 || addr > 0xd00)
+    if (addr < 0x100 || (addr > 0xd00 && addr != 0xd18 && addr != 0xd1c
+        && addr != 0xd20))
         return nvic_readl(s, addr);
 #endif
     val = gic_dist_readw(opaque, offset);
@@ -528,6 +534,11 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
                 GIC_CLEAR_TRIGGER(irq + i);
             }
         }
+#else
+    } else if (0xd18 <= offset && offset < 0xd24) {
+        /* System Handler Priority.  */
+        irq = offset - 0xd14;
+        s->priority1[irq][0] = value & 0xff;
 #endif
     } else {
         /* 0xf00 is only handled for 32-bit writes.  */
@@ -553,7 +564,8 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
 #ifdef NVIC
     uint32_t addr;
     addr = offset;
-    if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) {
+    if (addr < 0x100 || (addr > 0xd00 && addr != 0xd18 && addr != 0xd1c
+        && addr != 0xd20 && addr != 0xf00)) {
         nvic_writel(s, addr, value);
         return;
     }
diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c
index bf8c3c5..65b575e 100644
--- a/hw/armv7m_nvic.c
+++ b/hw/armv7m_nvic.c
@@ -195,14 +195,6 @@ static uint32_t nvic_readl(void *opaque, uint32_t offset)
     case 0xd14: /* Configuration Control.  */
         /* TODO: Implement Configuration Control bits.  */
         return 0;
-    case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority.  */
-        irq = offset - 0xd14;
-        val = 0;
-        val |= s->gic.priority1[irq++][0];
-        val |= s->gic.priority1[irq++][0] << 8;
-        val |= s->gic.priority1[irq++][0] << 16;
-        val |= s->gic.priority1[irq][0] << 24;
-        return val;
     case 0xd24: /* System Handler Status.  */
         val = 0;
         if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0);
@@ -335,17 +327,6 @@ static void nvic_writel(void *opaque, uint32_t offset, uint32_t value)
     case 0xd14: /* Configuration Control.  */
         /* TODO: Implement control registers.  */
         goto bad_reg;
-    case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority.  */
-        {
-            int irq;
-            irq = offset - 0xd14;
-            s->gic.priority1[irq++][0] = value & 0xff;
-            s->gic.priority1[irq++][0] = (value >> 8) & 0xff;
-            s->gic.priority1[irq++][0] = (value >> 16) & 0xff;
-            s->gic.priority1[irq][0] = (value >> 24) & 0xff;
-            gic_update(&s->gic);
-        }
-        break;
     case 0xd24: /* System Handler Control.  */
         /* TODO: Real hardware allows you to set/clear the active bits
            under some circumstances.  We don't implement this.  */
-- 
1.7.1


[-- Attachment #3: 0002-target-arm-Disable-priority_mask-feature.patch --]
[-- Type: text/x-patch, Size: 932 bytes --]

>From 5f562d098d84e12d4688272dcf68a2d0318721a7 Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Fri, 16 Dec 2011 20:00:59 +0100
Subject: [PATCH 2/4] target-arm: Disable priority_mask feature

This is unused for the ARMv7-M NVIC.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
---
 hw/arm_gic.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 5139d95..cafcc81 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -707,7 +707,11 @@ static void gic_reset(gic_state *s)
     int i;
     memset(s->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state));
     for (i = 0 ; i < NUM_CPU(s); i++) {
+#ifdef NVIC
+        s->priority_mask[i] = 0x100;
+#else
         s->priority_mask[i] = 0xf0;
+#endif
         s->current_pending[i] = 1023;
         s->running_irq[i] = 1023;
         s->running_priority[i] = 0x100;
-- 
1.7.1


[-- Attachment #4: 0003-target-arm-Evil-hack-for-BASEPRI-and-BASEPRI_MAX.patch --]
[-- Type: text/x-patch, Size: 2443 bytes --]

>From 78e85bb79c02b14170c3f39d9bb9cccd4d625890 Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Fri, 16 Dec 2011 20:12:29 +0100
Subject: [PATCH 3/4] target-arm: Evil hack for BASEPRI and BASEPRI_MAX

This is only a quick and dirty fix to get the ARMv7-M BASEPRI and
BASEPRI_MAX feature working.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
---
 cpu-exec.c          |    4 ++--
 target-arm/helper.c |   12 +++++-------
 2 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/cpu-exec.c b/cpu-exec.c
index a9fa608..6ca9aab 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -408,8 +408,8 @@ int cpu_exec(CPUState *env)
                        We avoid this by disabling interrupts when
                        pc contains a magic address.  */
                     if (interrupt_request & CPU_INTERRUPT_HARD
-                        && ((IS_M(env) && env->regs[15] < 0xfffffff0)
-                            || !(env->uncached_cpsr & CPSR_I))) {
+                        && !(env->uncached_cpsr & CPSR_I)
+                        && (!IS_M(env) || env->regs[15] < 0xfffffff0)) {
                         env->exception_index = EXCP_IRQ;
                         do_interrupt(env);
                         next_tb = 0;
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 65f4fbf..be2e6db 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2163,7 +2163,7 @@ uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
         return (env->uncached_cpsr & CPSR_I) != 0;
     case 17: /* BASEPRI */
     case 18: /* BASEPRI_MAX */
-        return env->v7m.basepri;
+        return (env->uncached_cpsr & CPSR_I) != 0;
     case 19: /* FAULTMASK */
         return (env->uncached_cpsr & CPSR_F) != 0;
     case 20: /* CONTROL */
@@ -2218,13 +2218,11 @@ void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
             env->uncached_cpsr &= ~CPSR_I;
         break;
     case 17: /* BASEPRI */
-        env->v7m.basepri = val & 0xff;
-        break;
     case 18: /* BASEPRI_MAX */
-        val &= 0xff;
-        if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
-            env->v7m.basepri = val;
-        break;
+        if (val)
+            env->uncached_cpsr |= CPSR_I;
+        else
+            env->uncached_cpsr &= ~CPSR_I;
     case 19: /* FAULTMASK */
         if (val & 1)
             env->uncached_cpsr |= CPSR_F;
-- 
1.7.1


[-- Attachment #5: 0004-target-arm-Evil-hack-to-increase-the-RAM-size.patch --]
[-- Type: text/x-patch, Size: 987 bytes --]

>From e06edd436a336e5db5188eb7ffac594138fc825a Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Fri, 16 Dec 2011 20:19:45 +0100
Subject: [PATCH 4/4] target-arm: Evil hack to increase the RAM size

This increases the RAM of the Stellaris LM3S6965 in a brute force way.
It would be nice to be able to override the default RAM size with
command line options.  The default RAM size is to small to run complex
test suites.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
---
 hw/stellaris.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/hw/stellaris.c b/hw/stellaris.c
index ce62a98..dd7b7d7 100644
--- a/hw/stellaris.c
+++ b/hw/stellaris.c
@@ -1219,7 +1219,8 @@ static stellaris_board_info stellaris_boards[] = {
   { "LM3S6965EVB",
     0x10010002,
     0x1073402e,
-    0x00ff007f, /* dc0 */
+    /* FIXME */
+    0xffffffff, /* dc0 */
     0x001133ff,
     0x030f5317,
     0x0f0f87ff,
-- 
1.7.1


^ permalink raw reply related	[flat|nested] 13+ messages in thread

* [Qemu-devel] [Bug 696094] Re: TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working
  2010-12-31 20:30 [Qemu-devel] [Bug 696094] [NEW] TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working Frikkie Thirion
                   ` (6 preceding siblings ...)
  2011-12-15 18:56 ` Peter Maydell
@ 2011-12-18 14:25 ` Peter Maydell
  2017-11-06 11:40 ` Peter Maydell
                   ` (2 subsequent siblings)
  10 siblings, 0 replies; 13+ messages in thread
From: Peter Maydell @ 2011-12-18 14:25 UTC (permalink / raw)
  To: qemu-devel

http://www.mail-archive.com/qemu-devel@nongnu.org/msg90256.html has some
patches from Sebastian Huber which let him run the RTEMS real time
system on the TI Stellaris LM3S6965 with a working system tick. As he
notes, some of them are hacks and not suitable for applying to qemu, but
they give a reasonable list of problems needing fixing:

(1) SHPR* (and some other) system registers need to be byte and halfword accessible
(2) GIC priority mask feature not correct for v7M? [actually this looks to be wrong for A profile too, at least as far as the reset value goes: 11MPCore had a reset value of 0xf0 but A9 has reset value of 0.]
(3) BASEPRI and BASEPRI_MAX are totally ignored at the moment
(4) not very much RAM and it's not configurable from command line

(2) and (3) add up to "we don't implement the M profile execution
priority and exception model properly"; I strongly suspect there are
further bugs in this area. (I'm not convinced that sharing code between
the A profile GIC and the M profile NVIC is worthwhile, incidentally.)

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/696094

Title:
  TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not
  working

Status in QEMU:
  New

Bug description:
  I've tried to create a small project that uses the CMSIS as base library.
  The problem is that the SysTick_interrupt_handler() doesn't get executed when the systick event is detected in QEMU. Furthermore, it seems asif QEMU gets stuck in an endless loop. QEMU doesn't respond to Ctrl-C on the command line and the GDB session also stalls. 'kill -9' is the only way to stop QEMU.

  It seems asif the initialisation of the NVIC works fine. I've traced the function calls in QEMU as follows:
  stellaris.c: stellaris_init() - Perform generic armv7 init: armv7m_init()
     armv7m.c: armv7m_init() - Create and init the nvic:
                                 nvic = qdev_create(NULL, "armv7m_nvic");
                                 env->nvic = nvic;
                                 qdev_init_nofail(nvic);
                             - Configure the programmable interrupt controller:
                                 Call: arm_pic_init_cpu() 
                                          qemu_allocate_irqs(arm_pic_cpu_handler)
                             - Initialise 64 interrupt structures.

  The following call sequence is observed when the systick event occur:
  armv7m_nvic.c: systick_timer_tick(): set pending interrupt
  armv7m_nvic.c: armv7m_nvic_set_pending() for irq:15
    arm_gic.c: gic_set_pending_private(): GIC_SET_PENDING(15,)
      arm_gic.c: gic_update() - Raise IRQ with qemu_set_irq()
         irq.c: eqmu_set_irq() - Call the irq->handler 
                                 -- I assume the irq handler is 'arm_pic_cpu_handler()',
                                    since that was passed as the parameter when
                                    qemu_allocate_irqs() was called in ...
            arm_pic.c: arm_pic_cpu_handler() - After evaluation, call cpu_interrupt()
               exec.c: cpu_interrupt() is called.     

  The tools that were used during the testing of this project:
    GCC: Codesourcery ARM eabi 2010q3
    QEMU: Checked out on 31/12/2010 - Last commit: 0fcec41eec0432c77645b4a407d3a3e030c4abc4
  The project files are attached, for reproducing of the errors.
     Note: The CMSIS wants to perform byte accesses to the NVIC. For the Cortex-M3, unaligned 8 bit and 16 bit accesses are allowed. The current QEMU implementation doesn't yet cater for it. As a work around, updated versions of
  arm_gic.c armv7m_nvic.h armv7m_nvic.c is also included.

  Launch project with: go_gdb.sh
  Attach debugger with: arm-none-eabi-gdbtui --command=gdbCommands_tui
  (s = step, n = next, c = continue, Ctrl-C = stop, print <variable> to look at variable contents)

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/696094/+subscriptions

^ permalink raw reply	[flat|nested] 13+ messages in thread

* [Qemu-devel] [Bug 696094] Re: TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working
  2010-12-31 20:30 [Qemu-devel] [Bug 696094] [NEW] TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working Frikkie Thirion
                   ` (7 preceding siblings ...)
  2011-12-18 14:25 ` Peter Maydell
@ 2017-11-06 11:40 ` Peter Maydell
  2017-11-07 17:02 ` Peter Maydell
  2017-12-15 16:15 ` Thomas Huth
  10 siblings, 0 replies; 13+ messages in thread
From: Peter Maydell @ 2017-11-06 11:40 UTC (permalink / raw)
  To: qemu-devel

** Tags added: arm

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/696094

Title:
  TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not
  working

Status in QEMU:
  New

Bug description:
  I've tried to create a small project that uses the CMSIS as base library.
  The problem is that the SysTick_interrupt_handler() doesn't get executed when the systick event is detected in QEMU. Furthermore, it seems asif QEMU gets stuck in an endless loop. QEMU doesn't respond to Ctrl-C on the command line and the GDB session also stalls. 'kill -9' is the only way to stop QEMU.

  It seems asif the initialisation of the NVIC works fine. I've traced the function calls in QEMU as follows:
  stellaris.c: stellaris_init() - Perform generic armv7 init: armv7m_init()
     armv7m.c: armv7m_init() - Create and init the nvic:
                                 nvic = qdev_create(NULL, "armv7m_nvic");
                                 env->nvic = nvic;
                                 qdev_init_nofail(nvic);
                             - Configure the programmable interrupt controller:
                                 Call: arm_pic_init_cpu() 
                                          qemu_allocate_irqs(arm_pic_cpu_handler)
                             - Initialise 64 interrupt structures.

  The following call sequence is observed when the systick event occur:
  armv7m_nvic.c: systick_timer_tick(): set pending interrupt
  armv7m_nvic.c: armv7m_nvic_set_pending() for irq:15
    arm_gic.c: gic_set_pending_private(): GIC_SET_PENDING(15,)
      arm_gic.c: gic_update() - Raise IRQ with qemu_set_irq()
         irq.c: eqmu_set_irq() - Call the irq->handler 
                                 -- I assume the irq handler is 'arm_pic_cpu_handler()',
                                    since that was passed as the parameter when
                                    qemu_allocate_irqs() was called in ...
            arm_pic.c: arm_pic_cpu_handler() - After evaluation, call cpu_interrupt()
               exec.c: cpu_interrupt() is called.     

  The tools that were used during the testing of this project:
    GCC: Codesourcery ARM eabi 2010q3
    QEMU: Checked out on 31/12/2010 - Last commit: 0fcec41eec0432c77645b4a407d3a3e030c4abc4
  The project files are attached, for reproducing of the errors.
     Note: The CMSIS wants to perform byte accesses to the NVIC. For the Cortex-M3, unaligned 8 bit and 16 bit accesses are allowed. The current QEMU implementation doesn't yet cater for it. As a work around, updated versions of
  arm_gic.c armv7m_nvic.h armv7m_nvic.c is also included.

  Launch project with: go_gdb.sh
  Attach debugger with: arm-none-eabi-gdbtui --command=gdbCommands_tui
  (s = step, n = next, c = continue, Ctrl-C = stop, print <variable> to look at variable contents)

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/696094/+subscriptions

^ permalink raw reply	[flat|nested] 13+ messages in thread

* [Qemu-devel] [Bug 696094] Re: TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working
  2010-12-31 20:30 [Qemu-devel] [Bug 696094] [NEW] TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working Frikkie Thirion
                   ` (8 preceding siblings ...)
  2017-11-06 11:40 ` Peter Maydell
@ 2017-11-07 17:02 ` Peter Maydell
  2017-12-15 16:15 ` Thomas Huth
  10 siblings, 0 replies; 13+ messages in thread
From: Peter Maydell @ 2017-11-07 17:02 UTC (permalink / raw)
  To: qemu-devel

I've just retested with the project attached to the bug (had to hack it
a little bit to build with a recent gcc, but nothing affecting the timer
code), and with current head-of-git QEMU we execute it OK and putting a
breakpoint on the SysTick_Handler function shows that it is being
invoked once a second, as expected.

>From my comment #6, we've fixed SHPR byte/halfword accessibility, and
rewritten the NVIC handling so it gets priority masking, BASEPRI, etc
right. The stellaris boards having not much RAM is unavoidable, but we
do now have the mps2 boards if you need a basic M profile system with
more memory.

So I'm going to close this bug as fix-committed, as it should be fixed
in 2.11. (It might have been fixed already in 2.10, but 2.11 will
definitely be OK.)


** Changed in: qemu
       Status: New => Fix Committed

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/696094

Title:
  TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not
  working

Status in QEMU:
  Fix Committed

Bug description:
  I've tried to create a small project that uses the CMSIS as base library.
  The problem is that the SysTick_interrupt_handler() doesn't get executed when the systick event is detected in QEMU. Furthermore, it seems asif QEMU gets stuck in an endless loop. QEMU doesn't respond to Ctrl-C on the command line and the GDB session also stalls. 'kill -9' is the only way to stop QEMU.

  It seems asif the initialisation of the NVIC works fine. I've traced the function calls in QEMU as follows:
  stellaris.c: stellaris_init() - Perform generic armv7 init: armv7m_init()
     armv7m.c: armv7m_init() - Create and init the nvic:
                                 nvic = qdev_create(NULL, "armv7m_nvic");
                                 env->nvic = nvic;
                                 qdev_init_nofail(nvic);
                             - Configure the programmable interrupt controller:
                                 Call: arm_pic_init_cpu() 
                                          qemu_allocate_irqs(arm_pic_cpu_handler)
                             - Initialise 64 interrupt structures.

  The following call sequence is observed when the systick event occur:
  armv7m_nvic.c: systick_timer_tick(): set pending interrupt
  armv7m_nvic.c: armv7m_nvic_set_pending() for irq:15
    arm_gic.c: gic_set_pending_private(): GIC_SET_PENDING(15,)
      arm_gic.c: gic_update() - Raise IRQ with qemu_set_irq()
         irq.c: eqmu_set_irq() - Call the irq->handler 
                                 -- I assume the irq handler is 'arm_pic_cpu_handler()',
                                    since that was passed as the parameter when
                                    qemu_allocate_irqs() was called in ...
            arm_pic.c: arm_pic_cpu_handler() - After evaluation, call cpu_interrupt()
               exec.c: cpu_interrupt() is called.     

  The tools that were used during the testing of this project:
    GCC: Codesourcery ARM eabi 2010q3
    QEMU: Checked out on 31/12/2010 - Last commit: 0fcec41eec0432c77645b4a407d3a3e030c4abc4
  The project files are attached, for reproducing of the errors.
     Note: The CMSIS wants to perform byte accesses to the NVIC. For the Cortex-M3, unaligned 8 bit and 16 bit accesses are allowed. The current QEMU implementation doesn't yet cater for it. As a work around, updated versions of
  arm_gic.c armv7m_nvic.h armv7m_nvic.c is also included.

  Launch project with: go_gdb.sh
  Attach debugger with: arm-none-eabi-gdbtui --command=gdbCommands_tui
  (s = step, n = next, c = continue, Ctrl-C = stop, print <variable> to look at variable contents)

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/696094/+subscriptions

^ permalink raw reply	[flat|nested] 13+ messages in thread

* [Qemu-devel] [Bug 696094] Re: TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working
  2010-12-31 20:30 [Qemu-devel] [Bug 696094] [NEW] TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working Frikkie Thirion
                   ` (9 preceding siblings ...)
  2017-11-07 17:02 ` Peter Maydell
@ 2017-12-15 16:15 ` Thomas Huth
  10 siblings, 0 replies; 13+ messages in thread
From: Thomas Huth @ 2017-12-15 16:15 UTC (permalink / raw)
  To: qemu-devel

** Changed in: qemu
       Status: Fix Committed => Fix Released

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/696094

Title:
  TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not
  working

Status in QEMU:
  Fix Released

Bug description:
  I've tried to create a small project that uses the CMSIS as base library.
  The problem is that the SysTick_interrupt_handler() doesn't get executed when the systick event is detected in QEMU. Furthermore, it seems asif QEMU gets stuck in an endless loop. QEMU doesn't respond to Ctrl-C on the command line and the GDB session also stalls. 'kill -9' is the only way to stop QEMU.

  It seems asif the initialisation of the NVIC works fine. I've traced the function calls in QEMU as follows:
  stellaris.c: stellaris_init() - Perform generic armv7 init: armv7m_init()
     armv7m.c: armv7m_init() - Create and init the nvic:
                                 nvic = qdev_create(NULL, "armv7m_nvic");
                                 env->nvic = nvic;
                                 qdev_init_nofail(nvic);
                             - Configure the programmable interrupt controller:
                                 Call: arm_pic_init_cpu() 
                                          qemu_allocate_irqs(arm_pic_cpu_handler)
                             - Initialise 64 interrupt structures.

  The following call sequence is observed when the systick event occur:
  armv7m_nvic.c: systick_timer_tick(): set pending interrupt
  armv7m_nvic.c: armv7m_nvic_set_pending() for irq:15
    arm_gic.c: gic_set_pending_private(): GIC_SET_PENDING(15,)
      arm_gic.c: gic_update() - Raise IRQ with qemu_set_irq()
         irq.c: eqmu_set_irq() - Call the irq->handler 
                                 -- I assume the irq handler is 'arm_pic_cpu_handler()',
                                    since that was passed as the parameter when
                                    qemu_allocate_irqs() was called in ...
            arm_pic.c: arm_pic_cpu_handler() - After evaluation, call cpu_interrupt()
               exec.c: cpu_interrupt() is called.     

  The tools that were used during the testing of this project:
    GCC: Codesourcery ARM eabi 2010q3
    QEMU: Checked out on 31/12/2010 - Last commit: 0fcec41eec0432c77645b4a407d3a3e030c4abc4
  The project files are attached, for reproducing of the errors.
     Note: The CMSIS wants to perform byte accesses to the NVIC. For the Cortex-M3, unaligned 8 bit and 16 bit accesses are allowed. The current QEMU implementation doesn't yet cater for it. As a work around, updated versions of
  arm_gic.c armv7m_nvic.h armv7m_nvic.c is also included.

  Launch project with: go_gdb.sh
  Attach debugger with: arm-none-eabi-gdbtui --command=gdbCommands_tui
  (s = step, n = next, c = continue, Ctrl-C = stop, print <variable> to look at variable contents)

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/696094/+subscriptions

^ permalink raw reply	[flat|nested] 13+ messages in thread

end of thread, other threads:[~2017-12-15 16:29 UTC | newest]

Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2010-12-31 20:30 [Qemu-devel] [Bug 696094] [NEW] TI Stellaris lm3s811evb (ARM Cortex-M3) : Systick interrupt not working Frikkie Thirion
2010-12-31 20:30 ` [Qemu-devel] [Bug 696094] " Frikkie Thirion
2011-08-01 10:16 ` ARUNKUMAR VASUDEVAN
2011-12-16 19:28   ` Sebastian Huber
2011-08-01 10:26 ` ARUNKUMAR VASUDEVAN
2011-08-01 11:28 ` Peter Maydell
2011-12-11 16:56 ` Petteri Aimonen
2011-12-11 18:57 ` Peter Maydell
2011-12-15 18:56 ` Peter Maydell
2011-12-18 14:25 ` Peter Maydell
2017-11-06 11:40 ` Peter Maydell
2017-11-07 17:02 ` Peter Maydell
2017-12-15 16:15 ` Thomas Huth

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