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From: Luwei Kang <luwei.kang@intel.com>
To: kvm@vger.kernel.org
Cc: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com,
	x86@kernel.org, pbonzini@redhat.com, rkrcmar@redhat.com,
	linux-kernel@vger.kernel.org, joro@8bytes.org,
	Chao Peng <chao.p.peng@linux.intel.com>,
	Luwei Kang <luwei.kang@intel.com>
Subject: [PATCH v3 7/9] KVM: x86: Implement Intel Processor Trace MSRs read/write
Date: Tue, 28 Nov 2017 04:24:00 +0800	[thread overview]
Message-ID: <1511814242-12949-8-git-send-email-luwei.kang@intel.com> (raw)
In-Reply-To: <1511814242-12949-1-git-send-email-luwei.kang@intel.com>

From: Chao Peng <chao.p.peng@linux.intel.com>

Intel PT MSRs read/write will not be intercepted when guest enabled
Intel PT. IA32_RTIT_CTL read/write will always cause a VM-Exit.

Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
 arch/x86/kvm/vmx.c | 67 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/x86/kvm/x86.c | 23 +++++++++++++++++++
 2 files changed, 90 insertions(+)

diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index c10350b..e002a44 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -948,6 +948,8 @@ static void vmx_get_segment(struct kvm_vcpu *vcpu,
 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
 					    u16 error_code);
+static bool vmx_pt_supported(void);
+static inline void pt_disable_intercept_for_msr(bool flag);
 
 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
@@ -3337,6 +3339,38 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 			return 1;
 		msr_info->data = vcpu->arch.ia32_xss;
 		break;
+	case MSR_IA32_RTIT_CTL:
+		if (!vmx_pt_supported())
+			return 1;
+		msr_info->data = to_vmx(vcpu)->pt_desc.guest.ctl;
+		break;
+	case MSR_IA32_RTIT_STATUS:
+		if (!vmx_pt_supported())
+			return 1;
+		msr_info->data = to_vmx(vcpu)->pt_desc.guest.status;
+		break;
+	case MSR_IA32_RTIT_CR3_MATCH:
+		if (!vmx_pt_supported())
+			return 1;
+		msr_info->data = to_vmx(vcpu)->pt_desc.guest.cr3_match;
+		break;
+	case MSR_IA32_RTIT_OUTPUT_BASE:
+		if (!vmx_pt_supported())
+			return 1;
+		msr_info->data = to_vmx(vcpu)->pt_desc.guest.output_base;
+		break;
+	case MSR_IA32_RTIT_OUTPUT_MASK:
+		if (!vmx_pt_supported())
+			return 1;
+		msr_info->data = to_vmx(vcpu)->pt_desc.guest.output_mask;
+		break;
+	case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
+		if (!vmx_pt_supported())
+			return 1;
+		msr_info->data =
+			to_vmx(vcpu)->pt_desc.guest.addrs[msr_info->index -
+						MSR_IA32_RTIT_ADDR0_A];
+		break;
 	case MSR_TSC_AUX:
 		if (!msr_info->host_initiated &&
 		    !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
@@ -3461,6 +3495,39 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 		else
 			clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
 		break;
+	case MSR_IA32_RTIT_CTL:
+		if (!vmx_pt_supported() || to_vmx(vcpu)->nested.vmxon)
+			return 1;
+		pt_disable_intercept_for_msr(data & RTIT_CTL_TRACEEN);
+		vmcs_write64(GUEST_IA32_RTIT_CTL, data);
+		vmx->pt_desc.guest.ctl = data;
+		break;
+	case MSR_IA32_RTIT_STATUS:
+		if (!vmx_pt_supported())
+			return 1;
+		vmx->pt_desc.guest.status = data;
+		break;
+	case MSR_IA32_RTIT_CR3_MATCH:
+		if (!vmx_pt_supported())
+			return 1;
+		vmx->pt_desc.guest.cr3_match = data;
+		break;
+	case MSR_IA32_RTIT_OUTPUT_BASE:
+		if (!vmx_pt_supported())
+			return 1;
+		vmx->pt_desc.guest.output_base = data;
+		break;
+	case MSR_IA32_RTIT_OUTPUT_MASK:
+		if (!vmx_pt_supported())
+			return 1;
+		vmx->pt_desc.guest.output_mask = data;
+		break;
+	case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
+		if (!vmx_pt_supported())
+			return 1;
+		vmx->pt_desc.guest.addrs[msr_info->index -
+				MSR_IA32_RTIT_ADDR0_A] = data;
+		break;
 	case MSR_TSC_AUX:
 		if (!msr_info->host_initiated &&
 		    !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 34c85aa..775dabf3 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1006,6 +1006,12 @@ bool kvm_rdpmc(struct kvm_vcpu *vcpu)
 #endif
 	MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
 	MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
+	MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
+	MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
+	MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
+	MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
+	MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
+	MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
 };
 
 static unsigned num_msrs_to_save;
@@ -4310,6 +4316,23 @@ static void kvm_init_msr_list(void)
 			if (!kvm_x86_ops->rdtscp_supported())
 				continue;
 			break;
+		case MSR_IA32_RTIT_CTL:
+		case MSR_IA32_RTIT_STATUS:
+		case MSR_IA32_RTIT_CR3_MATCH:
+		case MSR_IA32_RTIT_OUTPUT_BASE:
+		case MSR_IA32_RTIT_OUTPUT_MASK:
+			if (!kvm_x86_ops->pt_supported())
+				continue;
+			break;
+		case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
+			u32 eax, ebx, ecx, edx;
+
+			cpuid_count(0x14, 1, &eax, &ebx, &ecx, &edx);
+			if (!kvm_x86_ops->pt_supported() || msrs_to_save[i] -
+					MSR_IA32_RTIT_ADDR0_A >= (eax & 0x7))
+				continue;
+			break;
+		}
 		default:
 			break;
 		}
-- 
1.8.3.1

  parent reply	other threads:[~2017-11-28 10:09 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-11-27 20:23 [PATCH v3 0/9] Intel Processor Trace virtulization enabling Luwei Kang
2017-11-27 20:23 ` [PATCH v3 1/9] perf/x86/intel/pt: Move Intel-PT MSR bit definitions to a public header Luwei Kang
2017-11-27 20:23 ` [PATCH v3 2/9] perf/x86/intel/pt: Change pt_cap_get() to a public function Luwei Kang
2017-11-27 20:23 ` [PATCH v3 3/9] KVM: x86: Add Intel Processor Trace virtualization mode Luwei Kang
2017-11-30 12:25   ` Paolo Bonzini
2017-11-27 20:23 ` [PATCH v3 4/9] KVM: x86: Add Intel Processor Trace cpuid emulation Luwei Kang
2017-11-30 12:14   ` Paolo Bonzini
2017-11-30 12:17   ` Paolo Bonzini
2017-11-27 20:23 ` [PATCH v3 5/9] KVM: x86: Add a function to disable/enable Intel PT MSRs intercept Luwei Kang
2017-11-27 20:23 ` [PATCH v3 6/9] KVM: x86: Add Intel processor trace context for each vcpu Luwei Kang
2017-11-27 20:24 ` Luwei Kang [this message]
2017-11-30 12:20   ` [PATCH v3 7/9] KVM: x86: Implement Intel Processor Trace MSRs read/write Paolo Bonzini
2017-12-01  6:40     ` Kang, Luwei
2017-12-01  8:33       ` Paolo Bonzini
2017-12-04  1:21         ` Kang, Luwei
2017-11-27 20:24 ` [PATCH v3 8/9] KVM: x86: Disable Intel Processor Trace when VMXON in L1 guest Luwei Kang
2017-11-30 12:22   ` Paolo Bonzini
2017-11-27 20:24 ` [PATCH v3 9/9] KVM: x86: Implement Intel Processor Trace context switch Luwei Kang
2017-11-30 12:27   ` Paolo Bonzini
2017-11-30 12:27 ` [PATCH v3 0/9] Intel Processor Trace virtulization enabling Paolo Bonzini

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