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From: "Kang, Luwei" <luwei.kang@intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>
Cc: "tglx@linutronix.de" <tglx@linutronix.de>,
	"mingo@redhat.com" <mingo@redhat.com>,
	"hpa@zytor.com" <hpa@zytor.com>,
	"x86@kernel.org" <x86@kernel.org>,
	"rkrcmar@redhat.com" <rkrcmar@redhat.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"joro@8bytes.org" <joro@8bytes.org>,
	Chao Peng <chao.p.peng@linux.intel.com>
Subject: RE: [PATCH v3 7/9] KVM: x86: Implement Intel Processor Trace MSRs read/write
Date: Mon, 4 Dec 2017 01:21:20 +0000	[thread overview]
Message-ID: <82D7661F83C1A047AF7DC287873BF1E167E504FC@SHSMSX101.ccr.corp.intel.com> (raw)
In-Reply-To: <b1930a75-f166-bf35-6280-f18850a1da59@redhat.com>

> >>> +		case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
> >>> +			u32 eax, ebx, ecx, edx;
> >>> +
> >>> +			cpuid_count(0x14, 1, &eax, &ebx, &ecx, &edx);
> >>
> >> Please cache the cpuid_count result, or do the cpuid_count after testing
> >> vmx_pt_supported() (which you can use instead of going through kvm_x86_ops).
> >
> > Hi Paolo,
> >     Thanks for your reply. I have cache EAX in "struct pt_desc" and will initialize in vmx_vcpu_setup().
> > +struct pt_desc {
> > +       unsigned int addr_num;
> > +       struct pt_ctx host;
> > +       struct pt_ctx guest;
> > +};
> >     But kvm_init_msr_list() is invoked too early, I have to read from hardware.  So, what about change like this.
> >
> > -                       cpuid_count(0x14, 1, &eax, &ebx, &ecx, &edx);
> > -                       if (!kvm_x86_ops->pt_supported() || msrs_to_save[i] -
> > -                                       MSR_IA32_RTIT_ADDR0_A >= (eax & 0x7))
> > +                       if (!kvm_x86_ops->pt_supported())
> >                                 continue;
> > +                       cpuid_count(0x14, 1, &eax, &ebx, &ecx, &edx);
> > +                       if (msrs_to_save[i] -
> > +                               MSR_IA32_RTIT_ADDR0_A >= (eax & 0x7))
> > +                                       continue;
> 
> For kvm_init_msr_list it's okay.  But can you please add a
> pt_msr_count() function?
>

Of course, I will fix in next version. Thanks!

Luwei Kang

> >>
> >>> +			if (!kvm_x86_ops->pt_supported() || msrs_to_save[i] -
> >>> +					MSR_IA32_RTIT_ADDR0_A >= (eax & 0x7))
> >>> +				continue;
> >>> +			break;
> >

  reply	other threads:[~2017-12-04  1:21 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-11-27 20:23 [PATCH v3 0/9] Intel Processor Trace virtulization enabling Luwei Kang
2017-11-27 20:23 ` [PATCH v3 1/9] perf/x86/intel/pt: Move Intel-PT MSR bit definitions to a public header Luwei Kang
2017-11-27 20:23 ` [PATCH v3 2/9] perf/x86/intel/pt: Change pt_cap_get() to a public function Luwei Kang
2017-11-27 20:23 ` [PATCH v3 3/9] KVM: x86: Add Intel Processor Trace virtualization mode Luwei Kang
2017-11-30 12:25   ` Paolo Bonzini
2017-11-27 20:23 ` [PATCH v3 4/9] KVM: x86: Add Intel Processor Trace cpuid emulation Luwei Kang
2017-11-30 12:14   ` Paolo Bonzini
2017-11-30 12:17   ` Paolo Bonzini
2017-11-27 20:23 ` [PATCH v3 5/9] KVM: x86: Add a function to disable/enable Intel PT MSRs intercept Luwei Kang
2017-11-27 20:23 ` [PATCH v3 6/9] KVM: x86: Add Intel processor trace context for each vcpu Luwei Kang
2017-11-27 20:24 ` [PATCH v3 7/9] KVM: x86: Implement Intel Processor Trace MSRs read/write Luwei Kang
2017-11-30 12:20   ` Paolo Bonzini
2017-12-01  6:40     ` Kang, Luwei
2017-12-01  8:33       ` Paolo Bonzini
2017-12-04  1:21         ` Kang, Luwei [this message]
2017-11-27 20:24 ` [PATCH v3 8/9] KVM: x86: Disable Intel Processor Trace when VMXON in L1 guest Luwei Kang
2017-11-30 12:22   ` Paolo Bonzini
2017-11-27 20:24 ` [PATCH v3 9/9] KVM: x86: Implement Intel Processor Trace context switch Luwei Kang
2017-11-30 12:27   ` Paolo Bonzini
2017-11-30 12:27 ` [PATCH v3 0/9] Intel Processor Trace virtulization enabling Paolo Bonzini

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