From: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> To: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org, sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, lgirdwood-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Cc: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Subject: [PATCH v3 04/11] clk: tegra: add CVB tables for Tegra210 CPU DFLL Date: Tue, 6 Feb 2018 18:34:05 +0200 [thread overview] Message-ID: <1517934852-23255-5-git-send-email-pdeschrijver@nvidia.com> (raw) In-Reply-To: <1517934852-23255-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Signed-off-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> --- drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 426 +++++++++++++++++++++++++++++ drivers/clk/tegra/cvb.h | 1 + 2 files changed, 427 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c index 6486ad9..78dddab 100644 --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c @@ -88,6 +88,421 @@ struct dfll_fcpu_data { }, }; +static const unsigned long tegra210_cpu_max_freq_table[] = { + [0] = 1912500000UL, + [1] = 1912500000UL, + [2] = 2218500000UL, + [3] = 1785000000UL, + [4] = 1632000000UL, + [5] = 1912500000UL, + [6] = 2014500000UL, + [7] = 1734000000UL, + [8] = 1683000000UL, + [9] = 1555500000UL, + [10] = 1504500000UL, +}; + +#define CPU_CVB_TABLE \ + .speedo_scale = 100, \ + .voltage_scale = 1000, \ + .entries = { \ + {204000000UL, {1007452, -23865, 370} }, \ + {306000000UL, {1052709, -24875, 370} }, \ + {408000000UL, {1099069, -25895, 370} }, \ + {510000000UL, {1146534, -26905, 370} }, \ + {612000000UL, {1195102, -27915, 370} }, \ + {714000000UL, {1244773, -28925, 370} }, \ + {816000000UL, {1295549, -29935, 370} }, \ + {918000000UL, {1347428, -30955, 370} }, \ + {1020000000UL, {1400411, -31965, 370} }, \ + {1122000000UL, {1454497, -32975, 370} }, \ + {1224000000UL, {1509687, -33985, 370} }, \ + {1326000000UL, {1565981, -35005, 370} }, \ + {1428000000UL, {1623379, -36015, 370} }, \ + {1530000000UL, {1681880, -37025, 370} }, \ + {1632000000UL, {1741485, -38035, 370} }, \ + {1734000000UL, {1802194, -39055, 370} }, \ + {1836000000UL, {1864006, -40065, 370} }, \ + {1912500000UL, {1910780, -40815, 370} }, \ + {2014500000UL, {1227000, 0, 0} }, \ + {2218500000UL, {1227000, 0, 0} }, \ + {0, { 0, 0, 0} }, \ + } + +#define CPU_CVB_TABLE_XA \ + .speedo_scale = 100, \ + .voltage_scale = 1000, \ + .entries = { \ + {204000000UL, {1250024, -39785, 565} }, \ + {306000000UL, {1297556, -41145, 565} }, \ + {408000000UL, {1346718, -42505, 565} }, \ + {510000000UL, {1397511, -43855, 565} }, \ + {612000000UL, {1449933, -45215, 565} }, \ + {714000000UL, {1503986, -46575, 565} }, \ + {816000000UL, {1559669, -47935, 565} }, \ + {918000000UL, {1616982, -49295, 565} }, \ + {1020000000UL, {1675926, -50645, 565} }, \ + {1122000000UL, {1736500, -52005, 565} }, \ + {1224000000UL, {1798704, -53365, 565} }, \ + {1326000000UL, {1862538, -54725, 565} }, \ + {1428000000UL, {1928003, -56085, 565} }, \ + {1530000000UL, {1995097, -57435, 565} }, \ + {1606500000UL, {2046149, -58445, 565} }, \ + {1632000000UL, {2063822, -58795, 565} }, \ + {0, { 0, 0, 0} }, \ + } + +#define CPU_CVB_TABLE_EUCM1 \ + .speedo_scale = 100, \ + .voltage_scale = 1000, \ + .entries = { \ + {204000000UL, {734429, 0, 0} }, \ + {306000000UL, {768191, 0, 0} }, \ + {408000000UL, {801953, 0, 0} }, \ + {510000000UL, {835715, 0, 0} }, \ + {612000000UL, {869477, 0, 0} }, \ + {714000000UL, {903239, 0, 0} }, \ + {816000000UL, {937001, 0, 0} }, \ + {918000000UL, {970763, 0, 0} }, \ + {1020000000UL, {1004525, 0, 0} }, \ + {1122000000UL, {1038287, 0, 0} }, \ + {1224000000UL, {1072049, 0, 0} }, \ + {1326000000UL, {1105811, 0, 0} }, \ + {1428000000UL, {1130000, 0, 0} }, \ + {1555500000UL, {1130000, 0, 0} }, \ + {1632000000UL, {1170000, 0, 0} }, \ + {1734000000UL, {1227500, 0, 0} }, \ + {0, { 0, 0, 0} }, \ + } + +#define CPU_CVB_TABLE_EUCM2 \ + .speedo_scale = 100, \ + .voltage_scale = 1000, \ + .entries = { \ + {204000000UL, {742283, 0, 0} }, \ + {306000000UL, {776249, 0, 0} }, \ + {408000000UL, {810215, 0, 0} }, \ + {510000000UL, {844181, 0, 0} }, \ + {612000000UL, {878147, 0, 0} }, \ + {714000000UL, {912113, 0, 0} }, \ + {816000000UL, {946079, 0, 0} }, \ + {918000000UL, {980045, 0, 0} }, \ + {1020000000UL, {1014011, 0, 0} }, \ + {1122000000UL, {1047977, 0, 0} }, \ + {1224000000UL, {1081943, 0, 0} }, \ + {1326000000UL, {1090000, 0, 0} }, \ + {1479000000UL, {1090000, 0, 0} }, \ + {1555500000UL, {1162000, 0, 0} }, \ + {1683000000UL, {1195000, 0, 0} }, \ + {0, { 0, 0, 0} }, \ + } + +#define CPU_CVB_TABLE_EUCM2_JOINT_RAIL \ + .speedo_scale = 100, \ + .voltage_scale = 1000, \ + .entries = { \ + {204000000UL, {742283, 0, 0} }, \ + {306000000UL, {776249, 0, 0} }, \ + {408000000UL, {810215, 0, 0} }, \ + {510000000UL, {844181, 0, 0} }, \ + {612000000UL, {878147, 0, 0} }, \ + {714000000UL, {912113, 0, 0} }, \ + {816000000UL, {946079, 0, 0} }, \ + {918000000UL, {980045, 0, 0} }, \ + {1020000000UL, {1014011, 0, 0} }, \ + {1122000000UL, {1047977, 0, 0} }, \ + {1224000000UL, {1081943, 0, 0} }, \ + {1326000000UL, {1090000, 0, 0} }, \ + {1479000000UL, {1090000, 0, 0} }, \ + {1504500000UL, {1120000, 0, 0} }, \ + {0, { 0, 0, 0} }, \ + } + +#define CPU_CVB_TABLE_ODN \ + .speedo_scale = 100, \ + .voltage_scale = 1000, \ + .entries = { \ + {204000000UL, {721094, 0, 0} }, \ + {306000000UL, {754040, 0, 0} }, \ + {408000000UL, {786986, 0, 0} }, \ + {510000000UL, {819932, 0, 0} }, \ + {612000000UL, {852878, 0, 0} }, \ + {714000000UL, {885824, 0, 0} }, \ + {816000000UL, {918770, 0, 0} }, \ + {918000000UL, {915716, 0, 0} }, \ + {1020000000UL, {984662, 0, 0} }, \ + {1122000000UL, {1017608, 0, 0} }, \ + {1224000000UL, {1050554, 0, 0} }, \ + {1326000000UL, {1083500, 0, 0} }, \ + {1428000000UL, {1116446, 0, 0} }, \ + {1581000000UL, {1130000, 0, 0} }, \ + {1683000000UL, {1168000, 0, 0} }, \ + {1785000000UL, {1227500, 0, 0} }, \ + {0, { 0, 0, 0} }, \ + } + +struct cvb_table tegra210_cpu_cvb_tables[] = { + { + .speedo_id = 10, + .process_id = 0, + .min_millivolts = 840, + .max_millivolts = 1120, + CPU_CVB_TABLE_EUCM2_JOINT_RAIL, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 10, + .process_id = 1, + .min_millivolts = 840, + .max_millivolts = 1120, + CPU_CVB_TABLE_EUCM2_JOINT_RAIL, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 9, + .process_id = 0, + .min_millivolts = 900, + .max_millivolts = 1162, + CPU_CVB_TABLE_EUCM2, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + } + }, + { + .speedo_id = 9, + .process_id = 1, + .min_millivolts = 900, + .max_millivolts = 1162, + CPU_CVB_TABLE_EUCM2, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + } + }, + { + .speedo_id = 8, + .process_id = 0, + .min_millivolts = 900, + .max_millivolts = 1195, + CPU_CVB_TABLE_EUCM2, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + } + }, + { + .speedo_id = 8, + .process_id = 1, + .min_millivolts = 900, + .max_millivolts = 1195, + CPU_CVB_TABLE_EUCM2, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + } + }, + { + .speedo_id = 7, + .process_id = 0, + .min_millivolts = 841, + .max_millivolts = 1227, + CPU_CVB_TABLE_EUCM1, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 7, + .process_id = 1, + .min_millivolts = 841, + .max_millivolts = 1227, + CPU_CVB_TABLE_EUCM1, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 6, + .process_id = 0, + .min_millivolts = 870, + .max_millivolts = 1150, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune1 = 0x20091d9, + } + }, + { + .speedo_id = 6, + .process_id = 1, + .min_millivolts = 870, + .max_millivolts = 1150, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune1 = 0x25501d0, + } + }, + { + .speedo_id = 5, + .process_id = 0, + .min_millivolts = 818, + .max_millivolts = 1227, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 5, + .process_id = 1, + .min_millivolts = 818, + .max_millivolts = 1227, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x25501d0, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 4, + .process_id = -1, + .min_millivolts = 918, + .max_millivolts = 1113, + CPU_CVB_TABLE_XA, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune1 = 0x17711BD, + } + }, + { + .speedo_id = 3, + .process_id = 0, + .min_millivolts = 825, + .max_millivolts = 1227, + CPU_CVB_TABLE_ODN, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 3, + .process_id = 1, + .min_millivolts = 825, + .max_millivolts = 1227, + CPU_CVB_TABLE_ODN, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x25501d0, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 2, + .process_id = 0, + .min_millivolts = 870, + .max_millivolts = 1227, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune1 = 0x20091d9, + } + }, + { + .speedo_id = 2, + .process_id = 1, + .min_millivolts = 870, + .max_millivolts = 1227, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune1 = 0x25501d0, + } + }, + { + .speedo_id = 1, + .process_id = 0, + .min_millivolts = 837, + .max_millivolts = 1227, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 1, + .process_id = 1, + .min_millivolts = 837, + .max_millivolts = 1227, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x25501d0, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 0, + .process_id = 0, + .min_millivolts = 850, + .max_millivolts = 1170, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 0, + .process_id = 1, + .min_millivolts = 850, + .max_millivolts = 1170, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x25501d0, + .tune_high_min_millivolts = 864, + } + }, +}; + static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = { .cpu_max_freq_table = tegra124_cpu_max_freq_table, .cpu_max_freq_table_size = ARRAY_SIZE(tegra124_cpu_max_freq_table), @@ -95,11 +510,22 @@ struct dfll_fcpu_data { .cpu_cvb_tables_size = ARRAY_SIZE(tegra124_cpu_cvb_tables) }; +static const struct dfll_fcpu_data tegra210_dfll_fcpu_data = { + .cpu_max_freq_table = tegra210_cpu_max_freq_table, + .cpu_max_freq_table_size = ARRAY_SIZE(tegra210_cpu_max_freq_table), + .cpu_cvb_tables = tegra210_cpu_cvb_tables, + .cpu_cvb_tables_size = ARRAY_SIZE(tegra210_cpu_cvb_tables), +}; + static const struct of_device_id tegra124_dfll_fcpu_of_match[] = { { .compatible = "nvidia,tegra124-dfll", .data = &tegra124_dfll_fcpu_data, }, + { + .compatible = "nvidia,tegra210-dfll", + .data = &tegra210_dfll_fcpu_data + }, { }, }; diff --git a/drivers/clk/tegra/cvb.h b/drivers/clk/tegra/cvb.h index bcf15a0..91a1941 100644 --- a/drivers/clk/tegra/cvb.h +++ b/drivers/clk/tegra/cvb.h @@ -41,6 +41,7 @@ struct cvb_cpu_dfll_data { u32 tune0_low; u32 tune0_high; u32 tune1; + unsigned int tune_high_min_millivolts; }; struct cvb_table { -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: Peter De Schrijver <pdeschrijver@nvidia.com> To: <linux-tegra@vger.kernel.org>, <linux-clk@vger.kernel.org>, <mturquette@baylibre.com>, <sboyd@codeaurora.org>, <robh+dt@kernel.org>, <mark.rutland@arm.com>, <devicetree@vger.kernel.org>, <lgirdwood@gmail.com>, <broonie@kernel.org>, <linux-kernel@vger.kernel.org> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Subject: [PATCH v3 04/11] clk: tegra: add CVB tables for Tegra210 CPU DFLL Date: Tue, 6 Feb 2018 18:34:05 +0200 [thread overview] Message-ID: <1517934852-23255-5-git-send-email-pdeschrijver@nvidia.com> (raw) In-Reply-To: <1517934852-23255-1-git-send-email-pdeschrijver@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> --- drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 426 +++++++++++++++++++++++++++++ drivers/clk/tegra/cvb.h | 1 + 2 files changed, 427 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c index 6486ad9..78dddab 100644 --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c @@ -88,6 +88,421 @@ struct dfll_fcpu_data { }, }; +static const unsigned long tegra210_cpu_max_freq_table[] = { + [0] = 1912500000UL, + [1] = 1912500000UL, + [2] = 2218500000UL, + [3] = 1785000000UL, + [4] = 1632000000UL, + [5] = 1912500000UL, + [6] = 2014500000UL, + [7] = 1734000000UL, + [8] = 1683000000UL, + [9] = 1555500000UL, + [10] = 1504500000UL, +}; + +#define CPU_CVB_TABLE \ + .speedo_scale = 100, \ + .voltage_scale = 1000, \ + .entries = { \ + {204000000UL, {1007452, -23865, 370} }, \ + {306000000UL, {1052709, -24875, 370} }, \ + {408000000UL, {1099069, -25895, 370} }, \ + {510000000UL, {1146534, -26905, 370} }, \ + {612000000UL, {1195102, -27915, 370} }, \ + {714000000UL, {1244773, -28925, 370} }, \ + {816000000UL, {1295549, -29935, 370} }, \ + {918000000UL, {1347428, -30955, 370} }, \ + {1020000000UL, {1400411, -31965, 370} }, \ + {1122000000UL, {1454497, -32975, 370} }, \ + {1224000000UL, {1509687, -33985, 370} }, \ + {1326000000UL, {1565981, -35005, 370} }, \ + {1428000000UL, {1623379, -36015, 370} }, \ + {1530000000UL, {1681880, -37025, 370} }, \ + {1632000000UL, {1741485, -38035, 370} }, \ + {1734000000UL, {1802194, -39055, 370} }, \ + {1836000000UL, {1864006, -40065, 370} }, \ + {1912500000UL, {1910780, -40815, 370} }, \ + {2014500000UL, {1227000, 0, 0} }, \ + {2218500000UL, {1227000, 0, 0} }, \ + {0, { 0, 0, 0} }, \ + } + +#define CPU_CVB_TABLE_XA \ + .speedo_scale = 100, \ + .voltage_scale = 1000, \ + .entries = { \ + {204000000UL, {1250024, -39785, 565} }, \ + {306000000UL, {1297556, -41145, 565} }, \ + {408000000UL, {1346718, -42505, 565} }, \ + {510000000UL, {1397511, -43855, 565} }, \ + {612000000UL, {1449933, -45215, 565} }, \ + {714000000UL, {1503986, -46575, 565} }, \ + {816000000UL, {1559669, -47935, 565} }, \ + {918000000UL, {1616982, -49295, 565} }, \ + {1020000000UL, {1675926, -50645, 565} }, \ + {1122000000UL, {1736500, -52005, 565} }, \ + {1224000000UL, {1798704, -53365, 565} }, \ + {1326000000UL, {1862538, -54725, 565} }, \ + {1428000000UL, {1928003, -56085, 565} }, \ + {1530000000UL, {1995097, -57435, 565} }, \ + {1606500000UL, {2046149, -58445, 565} }, \ + {1632000000UL, {2063822, -58795, 565} }, \ + {0, { 0, 0, 0} }, \ + } + +#define CPU_CVB_TABLE_EUCM1 \ + .speedo_scale = 100, \ + .voltage_scale = 1000, \ + .entries = { \ + {204000000UL, {734429, 0, 0} }, \ + {306000000UL, {768191, 0, 0} }, \ + {408000000UL, {801953, 0, 0} }, \ + {510000000UL, {835715, 0, 0} }, \ + {612000000UL, {869477, 0, 0} }, \ + {714000000UL, {903239, 0, 0} }, \ + {816000000UL, {937001, 0, 0} }, \ + {918000000UL, {970763, 0, 0} }, \ + {1020000000UL, {1004525, 0, 0} }, \ + {1122000000UL, {1038287, 0, 0} }, \ + {1224000000UL, {1072049, 0, 0} }, \ + {1326000000UL, {1105811, 0, 0} }, \ + {1428000000UL, {1130000, 0, 0} }, \ + {1555500000UL, {1130000, 0, 0} }, \ + {1632000000UL, {1170000, 0, 0} }, \ + {1734000000UL, {1227500, 0, 0} }, \ + {0, { 0, 0, 0} }, \ + } + +#define CPU_CVB_TABLE_EUCM2 \ + .speedo_scale = 100, \ + .voltage_scale = 1000, \ + .entries = { \ + {204000000UL, {742283, 0, 0} }, \ + {306000000UL, {776249, 0, 0} }, \ + {408000000UL, {810215, 0, 0} }, \ + {510000000UL, {844181, 0, 0} }, \ + {612000000UL, {878147, 0, 0} }, \ + {714000000UL, {912113, 0, 0} }, \ + {816000000UL, {946079, 0, 0} }, \ + {918000000UL, {980045, 0, 0} }, \ + {1020000000UL, {1014011, 0, 0} }, \ + {1122000000UL, {1047977, 0, 0} }, \ + {1224000000UL, {1081943, 0, 0} }, \ + {1326000000UL, {1090000, 0, 0} }, \ + {1479000000UL, {1090000, 0, 0} }, \ + {1555500000UL, {1162000, 0, 0} }, \ + {1683000000UL, {1195000, 0, 0} }, \ + {0, { 0, 0, 0} }, \ + } + +#define CPU_CVB_TABLE_EUCM2_JOINT_RAIL \ + .speedo_scale = 100, \ + .voltage_scale = 1000, \ + .entries = { \ + {204000000UL, {742283, 0, 0} }, \ + {306000000UL, {776249, 0, 0} }, \ + {408000000UL, {810215, 0, 0} }, \ + {510000000UL, {844181, 0, 0} }, \ + {612000000UL, {878147, 0, 0} }, \ + {714000000UL, {912113, 0, 0} }, \ + {816000000UL, {946079, 0, 0} }, \ + {918000000UL, {980045, 0, 0} }, \ + {1020000000UL, {1014011, 0, 0} }, \ + {1122000000UL, {1047977, 0, 0} }, \ + {1224000000UL, {1081943, 0, 0} }, \ + {1326000000UL, {1090000, 0, 0} }, \ + {1479000000UL, {1090000, 0, 0} }, \ + {1504500000UL, {1120000, 0, 0} }, \ + {0, { 0, 0, 0} }, \ + } + +#define CPU_CVB_TABLE_ODN \ + .speedo_scale = 100, \ + .voltage_scale = 1000, \ + .entries = { \ + {204000000UL, {721094, 0, 0} }, \ + {306000000UL, {754040, 0, 0} }, \ + {408000000UL, {786986, 0, 0} }, \ + {510000000UL, {819932, 0, 0} }, \ + {612000000UL, {852878, 0, 0} }, \ + {714000000UL, {885824, 0, 0} }, \ + {816000000UL, {918770, 0, 0} }, \ + {918000000UL, {915716, 0, 0} }, \ + {1020000000UL, {984662, 0, 0} }, \ + {1122000000UL, {1017608, 0, 0} }, \ + {1224000000UL, {1050554, 0, 0} }, \ + {1326000000UL, {1083500, 0, 0} }, \ + {1428000000UL, {1116446, 0, 0} }, \ + {1581000000UL, {1130000, 0, 0} }, \ + {1683000000UL, {1168000, 0, 0} }, \ + {1785000000UL, {1227500, 0, 0} }, \ + {0, { 0, 0, 0} }, \ + } + +struct cvb_table tegra210_cpu_cvb_tables[] = { + { + .speedo_id = 10, + .process_id = 0, + .min_millivolts = 840, + .max_millivolts = 1120, + CPU_CVB_TABLE_EUCM2_JOINT_RAIL, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 10, + .process_id = 1, + .min_millivolts = 840, + .max_millivolts = 1120, + CPU_CVB_TABLE_EUCM2_JOINT_RAIL, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 9, + .process_id = 0, + .min_millivolts = 900, + .max_millivolts = 1162, + CPU_CVB_TABLE_EUCM2, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + } + }, + { + .speedo_id = 9, + .process_id = 1, + .min_millivolts = 900, + .max_millivolts = 1162, + CPU_CVB_TABLE_EUCM2, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + } + }, + { + .speedo_id = 8, + .process_id = 0, + .min_millivolts = 900, + .max_millivolts = 1195, + CPU_CVB_TABLE_EUCM2, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + } + }, + { + .speedo_id = 8, + .process_id = 1, + .min_millivolts = 900, + .max_millivolts = 1195, + CPU_CVB_TABLE_EUCM2, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + } + }, + { + .speedo_id = 7, + .process_id = 0, + .min_millivolts = 841, + .max_millivolts = 1227, + CPU_CVB_TABLE_EUCM1, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 7, + .process_id = 1, + .min_millivolts = 841, + .max_millivolts = 1227, + CPU_CVB_TABLE_EUCM1, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 6, + .process_id = 0, + .min_millivolts = 870, + .max_millivolts = 1150, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune1 = 0x20091d9, + } + }, + { + .speedo_id = 6, + .process_id = 1, + .min_millivolts = 870, + .max_millivolts = 1150, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune1 = 0x25501d0, + } + }, + { + .speedo_id = 5, + .process_id = 0, + .min_millivolts = 818, + .max_millivolts = 1227, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 5, + .process_id = 1, + .min_millivolts = 818, + .max_millivolts = 1227, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x25501d0, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 4, + .process_id = -1, + .min_millivolts = 918, + .max_millivolts = 1113, + CPU_CVB_TABLE_XA, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune1 = 0x17711BD, + } + }, + { + .speedo_id = 3, + .process_id = 0, + .min_millivolts = 825, + .max_millivolts = 1227, + CPU_CVB_TABLE_ODN, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 3, + .process_id = 1, + .min_millivolts = 825, + .max_millivolts = 1227, + CPU_CVB_TABLE_ODN, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x25501d0, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 2, + .process_id = 0, + .min_millivolts = 870, + .max_millivolts = 1227, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune1 = 0x20091d9, + } + }, + { + .speedo_id = 2, + .process_id = 1, + .min_millivolts = 870, + .max_millivolts = 1227, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune1 = 0x25501d0, + } + }, + { + .speedo_id = 1, + .process_id = 0, + .min_millivolts = 837, + .max_millivolts = 1227, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 1, + .process_id = 1, + .min_millivolts = 837, + .max_millivolts = 1227, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x25501d0, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 0, + .process_id = 0, + .min_millivolts = 850, + .max_millivolts = 1170, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 0, + .process_id = 1, + .min_millivolts = 850, + .max_millivolts = 1170, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x25501d0, + .tune_high_min_millivolts = 864, + } + }, +}; + static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = { .cpu_max_freq_table = tegra124_cpu_max_freq_table, .cpu_max_freq_table_size = ARRAY_SIZE(tegra124_cpu_max_freq_table), @@ -95,11 +510,22 @@ struct dfll_fcpu_data { .cpu_cvb_tables_size = ARRAY_SIZE(tegra124_cpu_cvb_tables) }; +static const struct dfll_fcpu_data tegra210_dfll_fcpu_data = { + .cpu_max_freq_table = tegra210_cpu_max_freq_table, + .cpu_max_freq_table_size = ARRAY_SIZE(tegra210_cpu_max_freq_table), + .cpu_cvb_tables = tegra210_cpu_cvb_tables, + .cpu_cvb_tables_size = ARRAY_SIZE(tegra210_cpu_cvb_tables), +}; + static const struct of_device_id tegra124_dfll_fcpu_of_match[] = { { .compatible = "nvidia,tegra124-dfll", .data = &tegra124_dfll_fcpu_data, }, + { + .compatible = "nvidia,tegra210-dfll", + .data = &tegra210_dfll_fcpu_data + }, { }, }; diff --git a/drivers/clk/tegra/cvb.h b/drivers/clk/tegra/cvb.h index bcf15a0..91a1941 100644 --- a/drivers/clk/tegra/cvb.h +++ b/drivers/clk/tegra/cvb.h @@ -41,6 +41,7 @@ struct cvb_cpu_dfll_data { u32 tune0_low; u32 tune0_high; u32 tune1; + unsigned int tune_high_min_millivolts; }; struct cvb_table { -- 1.9.1
next prev parent reply other threads:[~2018-02-06 16:34 UTC|newest] Thread overview: 87+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-02-06 16:34 [PATCH v3 00/11] Tegra210 DFLL implementation Peter De Schrijver 2018-02-06 16:34 ` Peter De Schrijver [not found] ` <1517934852-23255-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2018-02-06 16:34 ` [PATCH v3 01/11] regulator: core: add API to get voltage constraints Peter De Schrijver 2018-02-06 16:34 ` Peter De Schrijver 2018-02-06 16:35 ` Mark Brown [not found] ` <20180206163544.GI5681-GFdadSzt00ze9xe1eoZjHA@public.gmane.org> 2018-02-07 8:47 ` Peter De Schrijver 2018-02-07 8:47 ` Peter De Schrijver 2018-02-07 10:43 ` Mark Brown [not found] ` <20180207104351.GA6003-GFdadSzt00ze9xe1eoZjHA@public.gmane.org> 2018-02-07 12:37 ` Peter De Schrijver 2018-02-07 12:37 ` Peter De Schrijver [not found] ` <20180207123750.GA5850-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org> 2018-02-07 14:18 ` Mark Brown 2018-02-07 14:18 ` Mark Brown 2018-02-07 14:32 ` Peter De Schrijver 2018-02-07 14:32 ` Peter De Schrijver [not found] ` <20180207143213.GB5850-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org> 2018-02-07 15:01 ` Mark Brown 2018-02-07 15:01 ` Mark Brown 2018-02-07 15:20 ` Peter De Schrijver 2018-02-07 15:20 ` Peter De Schrijver [not found] ` <20180207152045.GC5850-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org> 2018-02-07 15:37 ` Mark Brown 2018-02-07 15:37 ` Mark Brown [not found] ` <20180207153711.GE6003-GFdadSzt00ze9xe1eoZjHA@public.gmane.org> 2018-02-08 10:04 ` Laxman Dewangan 2018-02-08 10:04 ` Laxman Dewangan [not found] ` <86cd40ac-d255-f4b9-87cb-0cd34efba7d8-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2018-02-08 14:58 ` Mark Brown 2018-02-08 14:58 ` Mark Brown 2018-02-06 16:34 ` [PATCH v3 02/11] clk: tegra: retrieve regulator info from framework Peter De Schrijver 2018-02-06 16:34 ` Peter De Schrijver 2018-03-08 22:26 ` Jon Hunter 2018-03-08 22:26 ` Jon Hunter 2018-02-06 16:34 ` [PATCH v3 03/11] clk: tegra: dfll registration for multiple SoCs Peter De Schrijver 2018-02-06 16:34 ` Peter De Schrijver 2018-03-08 22:15 ` Jon Hunter 2018-03-08 22:15 ` Jon Hunter 2018-02-06 16:34 ` Peter De Schrijver [this message] 2018-02-06 16:34 ` [PATCH v3 04/11] clk: tegra: add CVB tables for Tegra210 CPU DFLL Peter De Schrijver 2018-03-08 22:28 ` Jon Hunter 2018-03-08 22:28 ` Jon Hunter 2018-02-06 16:34 ` [PATCH v3 05/11] clk: tegra: prepare dfll driver for PWM regulator Peter De Schrijver 2018-02-06 16:34 ` Peter De Schrijver 2018-03-08 22:50 ` Jon Hunter 2018-03-08 22:50 ` Jon Hunter 2018-03-12 9:14 ` Peter De Schrijver 2018-03-12 9:14 ` Peter De Schrijver 2018-03-12 11:08 ` Jon Hunter 2018-03-12 11:08 ` Jon Hunter 2018-03-13 9:03 ` Peter De Schrijver 2018-03-13 9:03 ` Peter De Schrijver 2018-03-13 10:07 ` Jon Hunter 2018-03-13 10:07 ` Jon Hunter 2018-02-06 16:34 ` [PATCH v3 07/11] dt-bindings: tegra: Update DFLL binding " Peter De Schrijver 2018-02-06 16:34 ` Peter De Schrijver [not found] ` <1517934852-23255-8-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2018-02-09 23:19 ` Rob Herring 2018-02-09 23:19 ` Rob Herring 2018-03-08 23:21 ` Jon Hunter 2018-03-08 23:21 ` Jon Hunter 2018-03-12 9:10 ` Peter De Schrijver 2018-03-12 9:10 ` Peter De Schrijver 2018-02-06 16:34 ` [PATCH v3 09/11] cpufreq: tegra124-cpufreq: extend to support Tegra210 Peter De Schrijver 2018-02-06 16:34 ` Peter De Schrijver 2018-03-08 23:25 ` Jon Hunter 2018-03-08 23:25 ` Jon Hunter 2018-03-09 8:14 ` Peter De Schrijver 2018-03-09 8:14 ` Peter De Schrijver 2018-03-12 10:14 ` Jon Hunter 2018-03-12 10:14 ` Jon Hunter 2018-03-13 9:28 ` Peter De Schrijver 2018-03-13 9:28 ` Peter De Schrijver 2018-03-09 9:11 ` Viresh Kumar 2018-03-12 12:15 ` Jon Hunter 2018-03-12 12:15 ` Jon Hunter 2018-03-13 9:51 ` Peter De Schrijver 2018-03-13 9:51 ` Peter De Schrijver 2018-03-13 10:20 ` Jon Hunter 2018-03-13 10:20 ` Jon Hunter 2018-02-06 16:34 ` [PATCH v3 10/11] arm64: dts: tegra: Add Tegra210 DFLL definition Peter De Schrijver 2018-02-06 16:34 ` Peter De Schrijver 2018-02-06 16:34 ` [PATCH v3 11/11] arm64: dts: nvidia: Tegra210 CPU clock definition Peter De Schrijver 2018-02-06 16:34 ` Peter De Schrijver 2018-02-06 16:34 ` [PATCH v3 06/11] clk: tegra: dfll: support PWM regulator control Peter De Schrijver 2018-02-06 16:34 ` Peter De Schrijver 2018-03-08 23:15 ` Jon Hunter 2018-03-08 23:15 ` Jon Hunter 2018-03-09 8:12 ` Peter De Schrijver 2018-03-09 8:12 ` Peter De Schrijver 2018-02-06 16:34 ` [PATCH v3 08/11] clk: tegra: build clk-dfll.c for Tegra124 and Tegra210 Peter De Schrijver 2018-02-06 16:34 ` Peter De Schrijver 2018-03-08 23:22 ` Jon Hunter 2018-03-08 23:22 ` Jon Hunter
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