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From: Jon Hunter <jonathanh@nvidia.com>
To: Peter De Schrijver <pdeschrijver@nvidia.com>,
	linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org,
	mturquette@baylibre.com, sboyd@codeaurora.org,
	robh+dt@kernel.org, mark.rutland@arm.com,
	devicetree@vger.kernel.org, lgirdwood@gmail.com,
	broonie@kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 08/11] clk: tegra: build clk-dfll.c for Tegra124 and Tegra210
Date: Thu, 8 Mar 2018 23:22:09 +0000	[thread overview]
Message-ID: <6ea88ecd-20bb-31f6-74ad-7f7e3aaecfe1@nvidia.com> (raw)
In-Reply-To: <1517934852-23255-9-git-send-email-pdeschrijver@nvidia.com>


On 06/02/18 16:34, Peter De Schrijver wrote:
> Tegra210 has a DFLL as well and can share the majority of the code with
> the Tegra124 implementation. So build the same code for both platforms.
> 
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
>  drivers/clk/tegra/Kconfig  | 5 +++++
>  drivers/clk/tegra/Makefile | 2 +-
>  2 files changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/tegra/Kconfig b/drivers/clk/tegra/Kconfig
> index 7ddacae..57902ab 100644
> --- a/drivers/clk/tegra/Kconfig
> +++ b/drivers/clk/tegra/Kconfig
> @@ -5,3 +5,8 @@ config TEGRA_CLK_EMC
>  config CLK_TEGRA_BPMP
>  	def_bool y
>  	depends on TEGRA_BPMP
> +
> +config TEGRA_CLK_DFLL
> +	depends on (ARCH_TEGRA_124_SOC || ARCH_TEGRA_210_SOC)
> +	select PM_OPP
> +	def_bool y
> diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
> index b716923..fc7f4b4 100644
> --- a/drivers/clk/tegra/Makefile
> +++ b/drivers/clk/tegra/Makefile
> @@ -19,7 +19,7 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clk-tegra20.o
>  obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += clk-tegra30.o
>  obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= clk-tegra114.o
>  obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= clk-tegra124.o
> -obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= clk-tegra124-dfll-fcpu.o
> +obj-$(CONFIG_TEGRA_CLK_DFLL)		+= clk-tegra124-dfll-fcpu.o
>  obj-$(CONFIG_ARCH_TEGRA_132_SOC)	+= clk-tegra124.o
>  obj-y					+= cvb.o
>  obj-$(CONFIG_ARCH_TEGRA_210_SOC)	+= clk-tegra210.o
> 

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>

Cheers
Jon

-- 
nvpublic

WARNING: multiple messages have this Message-ID (diff)
From: Jon Hunter <jonathanh@nvidia.com>
To: Peter De Schrijver <pdeschrijver@nvidia.com>,
	<linux-tegra@vger.kernel.org>, <linux-clk@vger.kernel.org>,
	<mturquette@baylibre.com>, <sboyd@codeaurora.org>,
	<robh+dt@kernel.org>, <mark.rutland@arm.com>,
	<devicetree@vger.kernel.org>, <lgirdwood@gmail.com>,
	<broonie@kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 08/11] clk: tegra: build clk-dfll.c for Tegra124 and Tegra210
Date: Thu, 8 Mar 2018 23:22:09 +0000	[thread overview]
Message-ID: <6ea88ecd-20bb-31f6-74ad-7f7e3aaecfe1@nvidia.com> (raw)
In-Reply-To: <1517934852-23255-9-git-send-email-pdeschrijver@nvidia.com>


On 06/02/18 16:34, Peter De Schrijver wrote:
> Tegra210 has a DFLL as well and can share the majority of the code with
> the Tegra124 implementation. So build the same code for both platforms.
> 
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
>  drivers/clk/tegra/Kconfig  | 5 +++++
>  drivers/clk/tegra/Makefile | 2 +-
>  2 files changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/tegra/Kconfig b/drivers/clk/tegra/Kconfig
> index 7ddacae..57902ab 100644
> --- a/drivers/clk/tegra/Kconfig
> +++ b/drivers/clk/tegra/Kconfig
> @@ -5,3 +5,8 @@ config TEGRA_CLK_EMC
>  config CLK_TEGRA_BPMP
>  	def_bool y
>  	depends on TEGRA_BPMP
> +
> +config TEGRA_CLK_DFLL
> +	depends on (ARCH_TEGRA_124_SOC || ARCH_TEGRA_210_SOC)
> +	select PM_OPP
> +	def_bool y
> diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
> index b716923..fc7f4b4 100644
> --- a/drivers/clk/tegra/Makefile
> +++ b/drivers/clk/tegra/Makefile
> @@ -19,7 +19,7 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clk-tegra20.o
>  obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += clk-tegra30.o
>  obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= clk-tegra114.o
>  obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= clk-tegra124.o
> -obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= clk-tegra124-dfll-fcpu.o
> +obj-$(CONFIG_TEGRA_CLK_DFLL)		+= clk-tegra124-dfll-fcpu.o
>  obj-$(CONFIG_ARCH_TEGRA_132_SOC)	+= clk-tegra124.o
>  obj-y					+= cvb.o
>  obj-$(CONFIG_ARCH_TEGRA_210_SOC)	+= clk-tegra210.o
> 

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>

Cheers
Jon

-- 
nvpublic

  reply	other threads:[~2018-03-08 23:22 UTC|newest]

Thread overview: 87+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-06 16:34 [PATCH v3 00/11] Tegra210 DFLL implementation Peter De Schrijver
2018-02-06 16:34 ` Peter De Schrijver
     [not found] ` <1517934852-23255-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2018-02-06 16:34   ` [PATCH v3 01/11] regulator: core: add API to get voltage constraints Peter De Schrijver
2018-02-06 16:34     ` Peter De Schrijver
2018-02-06 16:35     ` Mark Brown
     [not found]       ` <20180206163544.GI5681-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
2018-02-07  8:47         ` Peter De Schrijver
2018-02-07  8:47           ` Peter De Schrijver
2018-02-07 10:43           ` Mark Brown
     [not found]             ` <20180207104351.GA6003-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
2018-02-07 12:37               ` Peter De Schrijver
2018-02-07 12:37                 ` Peter De Schrijver
     [not found]                 ` <20180207123750.GA5850-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2018-02-07 14:18                   ` Mark Brown
2018-02-07 14:18                     ` Mark Brown
2018-02-07 14:32                     ` Peter De Schrijver
2018-02-07 14:32                       ` Peter De Schrijver
     [not found]                       ` <20180207143213.GB5850-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2018-02-07 15:01                         ` Mark Brown
2018-02-07 15:01                           ` Mark Brown
2018-02-07 15:20                           ` Peter De Schrijver
2018-02-07 15:20                             ` Peter De Schrijver
     [not found]                             ` <20180207152045.GC5850-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2018-02-07 15:37                               ` Mark Brown
2018-02-07 15:37                                 ` Mark Brown
     [not found]                                 ` <20180207153711.GE6003-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
2018-02-08 10:04                                   ` Laxman Dewangan
2018-02-08 10:04                                     ` Laxman Dewangan
     [not found]                                     ` <86cd40ac-d255-f4b9-87cb-0cd34efba7d8-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2018-02-08 14:58                                       ` Mark Brown
2018-02-08 14:58                                         ` Mark Brown
2018-02-06 16:34   ` [PATCH v3 02/11] clk: tegra: retrieve regulator info from framework Peter De Schrijver
2018-02-06 16:34     ` Peter De Schrijver
2018-03-08 22:26     ` Jon Hunter
2018-03-08 22:26       ` Jon Hunter
2018-02-06 16:34   ` [PATCH v3 03/11] clk: tegra: dfll registration for multiple SoCs Peter De Schrijver
2018-02-06 16:34     ` Peter De Schrijver
2018-03-08 22:15     ` Jon Hunter
2018-03-08 22:15       ` Jon Hunter
2018-02-06 16:34   ` [PATCH v3 04/11] clk: tegra: add CVB tables for Tegra210 CPU DFLL Peter De Schrijver
2018-02-06 16:34     ` Peter De Schrijver
2018-03-08 22:28     ` Jon Hunter
2018-03-08 22:28       ` Jon Hunter
2018-02-06 16:34   ` [PATCH v3 05/11] clk: tegra: prepare dfll driver for PWM regulator Peter De Schrijver
2018-02-06 16:34     ` Peter De Schrijver
2018-03-08 22:50     ` Jon Hunter
2018-03-08 22:50       ` Jon Hunter
2018-03-12  9:14       ` Peter De Schrijver
2018-03-12  9:14         ` Peter De Schrijver
2018-03-12 11:08         ` Jon Hunter
2018-03-12 11:08           ` Jon Hunter
2018-03-13  9:03           ` Peter De Schrijver
2018-03-13  9:03             ` Peter De Schrijver
2018-03-13 10:07             ` Jon Hunter
2018-03-13 10:07               ` Jon Hunter
2018-02-06 16:34   ` [PATCH v3 07/11] dt-bindings: tegra: Update DFLL binding " Peter De Schrijver
2018-02-06 16:34     ` Peter De Schrijver
     [not found]     ` <1517934852-23255-8-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2018-02-09 23:19       ` Rob Herring
2018-02-09 23:19         ` Rob Herring
2018-03-08 23:21     ` Jon Hunter
2018-03-08 23:21       ` Jon Hunter
2018-03-12  9:10       ` Peter De Schrijver
2018-03-12  9:10         ` Peter De Schrijver
2018-02-06 16:34   ` [PATCH v3 09/11] cpufreq: tegra124-cpufreq: extend to support Tegra210 Peter De Schrijver
2018-02-06 16:34     ` Peter De Schrijver
2018-03-08 23:25     ` Jon Hunter
2018-03-08 23:25       ` Jon Hunter
2018-03-09  8:14       ` Peter De Schrijver
2018-03-09  8:14         ` Peter De Schrijver
2018-03-12 10:14         ` Jon Hunter
2018-03-12 10:14           ` Jon Hunter
2018-03-13  9:28           ` Peter De Schrijver
2018-03-13  9:28             ` Peter De Schrijver
2018-03-09  9:11     ` Viresh Kumar
2018-03-12 12:15     ` Jon Hunter
2018-03-12 12:15       ` Jon Hunter
2018-03-13  9:51       ` Peter De Schrijver
2018-03-13  9:51         ` Peter De Schrijver
2018-03-13 10:20         ` Jon Hunter
2018-03-13 10:20           ` Jon Hunter
2018-02-06 16:34   ` [PATCH v3 10/11] arm64: dts: tegra: Add Tegra210 DFLL definition Peter De Schrijver
2018-02-06 16:34     ` Peter De Schrijver
2018-02-06 16:34   ` [PATCH v3 11/11] arm64: dts: nvidia: Tegra210 CPU clock definition Peter De Schrijver
2018-02-06 16:34     ` Peter De Schrijver
2018-02-06 16:34 ` [PATCH v3 06/11] clk: tegra: dfll: support PWM regulator control Peter De Schrijver
2018-02-06 16:34   ` Peter De Schrijver
2018-03-08 23:15   ` Jon Hunter
2018-03-08 23:15     ` Jon Hunter
2018-03-09  8:12     ` Peter De Schrijver
2018-03-09  8:12       ` Peter De Schrijver
2018-02-06 16:34 ` [PATCH v3 08/11] clk: tegra: build clk-dfll.c for Tegra124 and Tegra210 Peter De Schrijver
2018-02-06 16:34   ` Peter De Schrijver
2018-03-08 23:22   ` Jon Hunter [this message]
2018-03-08 23:22     ` Jon Hunter

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