From: Sricharan R <sricharan@codeaurora.org> To: robh@kernel.org, viresh.kumar@linaro.org, mark.rutland@arm.com, mturquette@baylibre.com, sboyd@codeaurora.org, linux@armlinux.org.uk, andy.gross@linaro.org, david.brown@linaro.org, rjw@rjwysocki.net, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-pm@vger.kernel.org, linux@arm.linux.org.uk Cc: sricharan@codeaurora.org Subject: [PATCH v9 07/15] clk: qcom: Add IPQ806X's HFPLLs Date: Tue, 6 Mar 2018 20:09:00 +0530 [thread overview] Message-ID: <1520347148-27852-8-git-send-email-sricharan@codeaurora.org> (raw) In-Reply-To: <1520347148-27852-1-git-send-email-sricharan@codeaurora.org> From: Stephen Boyd <sboyd@codeaurora.org> Describe the HFPLLs present on IPQ806X devices. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> --- drivers/clk/qcom/gcc-ipq806x.c | 82 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 28eb200..d571cf8 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -30,6 +30,7 @@ #include "clk-pll.h" #include "clk-rcg.h" #include "clk-branch.h" +#include "clk-hfpll.h" #include "reset.h" static struct clk_pll pll0 = { @@ -113,6 +114,84 @@ }, }; +static struct hfpll_data hfpll0_data = { + .mode_reg = 0x3200, + .l_reg = 0x3208, + .m_reg = 0x320c, + .n_reg = 0x3210, + .config_reg = 0x3204, + .status_reg = 0x321c, + .config_val = 0x7845c665, + .droop_reg = 0x3214, + .droop_val = 0x0108c000, + .min_rate = 600000000UL, + .max_rate = 1800000000UL, +}; + +static struct clk_hfpll hfpll0 = { + .d = &hfpll0_data, + .clkr.hw.init = &(struct clk_init_data){ + .parent_names = (const char *[]){ "pxo" }, + .num_parents = 1, + .name = "hfpll0", + .ops = &clk_ops_hfpll, + .flags = CLK_IGNORE_UNUSED, + }, + .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock), +}; + +static struct hfpll_data hfpll1_data = { + .mode_reg = 0x3240, + .l_reg = 0x3248, + .m_reg = 0x324c, + .n_reg = 0x3250, + .config_reg = 0x3244, + .status_reg = 0x325c, + .config_val = 0x7845c665, + .droop_reg = 0x3314, + .droop_val = 0x0108c000, + .min_rate = 600000000UL, + .max_rate = 1800000000UL, +}; + +static struct clk_hfpll hfpll1 = { + .d = &hfpll1_data, + .clkr.hw.init = &(struct clk_init_data){ + .parent_names = (const char *[]){ "pxo" }, + .num_parents = 1, + .name = "hfpll1", + .ops = &clk_ops_hfpll, + .flags = CLK_IGNORE_UNUSED, + }, + .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock), +}; + +static struct hfpll_data hfpll_l2_data = { + .mode_reg = 0x3300, + .l_reg = 0x3308, + .m_reg = 0x330c, + .n_reg = 0x3310, + .config_reg = 0x3304, + .status_reg = 0x331c, + .config_val = 0x7845c665, + .droop_reg = 0x3314, + .droop_val = 0x0108c000, + .min_rate = 600000000UL, + .max_rate = 1800000000UL, +}; + +static struct clk_hfpll hfpll_l2 = { + .d = &hfpll_l2_data, + .clkr.hw.init = &(struct clk_init_data){ + .parent_names = (const char *[]){ "pxo" }, + .num_parents = 1, + .name = "hfpll_l2", + .ops = &clk_ops_hfpll, + .flags = CLK_IGNORE_UNUSED, + }, + .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock), +}; + static struct clk_pll pll14 = { .l_reg = 0x31c4, .m_reg = 0x31c8, @@ -2800,6 +2879,9 @@ enum { [UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr, [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr, [NSSTCM_CLK] = &nss_tcm_clk.clkr, + [PLL9] = &hfpll0.clkr, + [PLL10] = &hfpll1.clkr, + [PLL12] = &hfpll_l2.clkr, }; static const struct qcom_reset_map gcc_ipq806x_resets[] = { -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
WARNING: multiple messages have this Message-ID (diff)
From: sricharan@codeaurora.org (Sricharan R) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v9 07/15] clk: qcom: Add IPQ806X's HFPLLs Date: Tue, 6 Mar 2018 20:09:00 +0530 [thread overview] Message-ID: <1520347148-27852-8-git-send-email-sricharan@codeaurora.org> (raw) In-Reply-To: <1520347148-27852-1-git-send-email-sricharan@codeaurora.org> From: Stephen Boyd <sboyd@codeaurora.org> Describe the HFPLLs present on IPQ806X devices. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> --- drivers/clk/qcom/gcc-ipq806x.c | 82 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 28eb200..d571cf8 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -30,6 +30,7 @@ #include "clk-pll.h" #include "clk-rcg.h" #include "clk-branch.h" +#include "clk-hfpll.h" #include "reset.h" static struct clk_pll pll0 = { @@ -113,6 +114,84 @@ }, }; +static struct hfpll_data hfpll0_data = { + .mode_reg = 0x3200, + .l_reg = 0x3208, + .m_reg = 0x320c, + .n_reg = 0x3210, + .config_reg = 0x3204, + .status_reg = 0x321c, + .config_val = 0x7845c665, + .droop_reg = 0x3214, + .droop_val = 0x0108c000, + .min_rate = 600000000UL, + .max_rate = 1800000000UL, +}; + +static struct clk_hfpll hfpll0 = { + .d = &hfpll0_data, + .clkr.hw.init = &(struct clk_init_data){ + .parent_names = (const char *[]){ "pxo" }, + .num_parents = 1, + .name = "hfpll0", + .ops = &clk_ops_hfpll, + .flags = CLK_IGNORE_UNUSED, + }, + .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock), +}; + +static struct hfpll_data hfpll1_data = { + .mode_reg = 0x3240, + .l_reg = 0x3248, + .m_reg = 0x324c, + .n_reg = 0x3250, + .config_reg = 0x3244, + .status_reg = 0x325c, + .config_val = 0x7845c665, + .droop_reg = 0x3314, + .droop_val = 0x0108c000, + .min_rate = 600000000UL, + .max_rate = 1800000000UL, +}; + +static struct clk_hfpll hfpll1 = { + .d = &hfpll1_data, + .clkr.hw.init = &(struct clk_init_data){ + .parent_names = (const char *[]){ "pxo" }, + .num_parents = 1, + .name = "hfpll1", + .ops = &clk_ops_hfpll, + .flags = CLK_IGNORE_UNUSED, + }, + .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock), +}; + +static struct hfpll_data hfpll_l2_data = { + .mode_reg = 0x3300, + .l_reg = 0x3308, + .m_reg = 0x330c, + .n_reg = 0x3310, + .config_reg = 0x3304, + .status_reg = 0x331c, + .config_val = 0x7845c665, + .droop_reg = 0x3314, + .droop_val = 0x0108c000, + .min_rate = 600000000UL, + .max_rate = 1800000000UL, +}; + +static struct clk_hfpll hfpll_l2 = { + .d = &hfpll_l2_data, + .clkr.hw.init = &(struct clk_init_data){ + .parent_names = (const char *[]){ "pxo" }, + .num_parents = 1, + .name = "hfpll_l2", + .ops = &clk_ops_hfpll, + .flags = CLK_IGNORE_UNUSED, + }, + .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock), +}; + static struct clk_pll pll14 = { .l_reg = 0x31c4, .m_reg = 0x31c8, @@ -2800,6 +2879,9 @@ enum { [UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr, [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr, [NSSTCM_CLK] = &nss_tcm_clk.clkr, + [PLL9] = &hfpll0.clkr, + [PLL10] = &hfpll1.clkr, + [PLL12] = &hfpll_l2.clkr, }; static const struct qcom_reset_map gcc_ipq806x_resets[] = { -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2018-03-06 14:39 UTC|newest] Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-03-06 14:38 [PATCH v9 00/15] Krait clocks + Krait CPUfreq Sricharan R 2018-03-06 14:38 ` Sricharan R 2018-03-06 14:38 ` [PATCH v9 01/15] ARM: Add Krait L2 register accessor functions Sricharan R 2018-03-06 14:38 ` Sricharan R 2018-05-24 17:39 ` Bjorn Andersson 2018-05-24 17:39 ` Bjorn Andersson 2018-05-25 5:40 ` Sricharan R 2018-05-25 5:40 ` Sricharan R 2018-05-30 15:55 ` Stephen Boyd 2018-05-30 15:55 ` Stephen Boyd 2018-05-30 15:55 ` Stephen Boyd 2018-05-31 4:57 ` Sricharan R 2018-05-31 4:57 ` Sricharan R 2018-05-31 7:41 ` Stephen Boyd 2018-05-31 7:41 ` Stephen Boyd 2018-05-31 7:41 ` Stephen Boyd 2018-06-01 13:20 ` Sricharan R 2018-06-01 13:20 ` Sricharan R 2018-06-01 17:12 ` Stephen Boyd 2018-06-01 17:12 ` Stephen Boyd 2018-06-01 17:12 ` Stephen Boyd 2018-03-06 14:38 ` [PATCH v9 02/15] clk: mux: Split out register accessors for reuse Sricharan R 2018-03-06 14:38 ` Sricharan R 2018-05-24 16:50 ` Bjorn Andersson 2018-05-24 16:50 ` Bjorn Andersson 2018-05-25 5:38 ` Sricharan R 2018-05-25 5:38 ` Sricharan R 2018-03-06 14:38 ` [PATCH v9 03/15] clk: qcom: Add support for High-Frequency PLLs (HFPLLs) Sricharan R 2018-03-06 14:38 ` Sricharan R 2018-03-06 14:38 ` [PATCH v9 04/15] clk: qcom: Add HFPLL driver Sricharan R 2018-03-06 14:38 ` Sricharan R 2018-03-06 14:38 ` [PATCH v9 05/15] dt-bindings: clock: Document qcom,hfpll Sricharan R 2018-03-06 14:38 ` Sricharan R 2018-03-06 14:38 ` [PATCH v9 06/15] clk: qcom: Add MSM8960/APQ8064's HFPLLs Sricharan R 2018-03-06 14:38 ` Sricharan R 2018-03-06 14:39 ` Sricharan R [this message] 2018-03-06 14:39 ` [PATCH v9 07/15] clk: qcom: Add IPQ806X's HFPLLs Sricharan R 2018-03-06 14:39 ` [PATCH v9 08/15] clk: qcom: Add support for Krait clocks Sricharan R 2018-03-06 14:39 ` Sricharan R 2018-03-06 14:39 ` [PATCH v9 09/15] clk: qcom: Add KPSS ACC/GCC driver Sricharan R 2018-03-06 14:39 ` Sricharan R 2018-03-06 14:39 ` [PATCH v9 10/15] dt-bindings: arm: Document qcom,kpss-gcc Sricharan R 2018-03-06 14:39 ` Sricharan R 2018-03-06 14:39 ` [PATCH v9 11/15] clk: qcom: Add Krait clock controller driver Sricharan R 2018-03-06 14:39 ` Sricharan R 2018-03-06 14:39 ` [PATCH v9 12/15] dt-bindings: clock: Document qcom,krait-cc Sricharan R 2018-03-06 14:39 ` Sricharan R 2018-03-06 14:39 ` [PATCH v9 13/15] clk: qcom: Add safe switch hook for krait mux clocks Sricharan R 2018-03-06 14:39 ` Sricharan R 2018-03-06 14:39 ` [PATCH v9 14/15] cpufreq: Add module to register cpufreq on Krait CPUs Sricharan R 2018-03-06 14:39 ` Sricharan R 2018-03-07 5:09 ` Viresh Kumar 2018-03-07 5:09 ` Viresh Kumar 2018-03-06 14:39 ` [PATCH v9 15/15] dt-bindings: cpufreq: Document operating-points-v2-krait-cpu Sricharan R 2018-03-06 14:39 ` Sricharan R
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