* [PATCH 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads
@ 2018-03-22 16:59 Yunwei Zhang
2018-03-22 16:59 ` [PATCH 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads Yunwei Zhang
2018-03-22 17:15 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads Patchwork
0 siblings, 2 replies; 8+ messages in thread
From: Yunwei Zhang @ 2018-03-22 16:59 UTC (permalink / raw)
To: intel-gfx
WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value will be returned.
However, that means each subsequent MMIO read will be forwarded to a
specific slice/subslice combination as read is unicast. This is OK since
slice/subslice specific register values are consistent in almost all cases
across slice/subslice. There are rare occasions such as INSTDONE that this
value will be dependent on slice/subslice combo, in such cases, we need to
program 0xFDC and recover this after. This is already covered by
read_subslice_reg for INSTDONE.
Also, 0xFDC will lose its information after TDR/engine reset/power state
change.
v2:
- use fls() instead of find_last_bit()
- added INTEL_SSEU to extract sseu from device info.
Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_engine_cs.c | 41 ++++++++++++++++++++++++++++++++--
2 files changed, 40 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d35f805..8484da1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2287,6 +2287,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
#define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
+#define INTEL_SSEU(dev_priv) ((dev_priv)->info.sseu)
#define REVID_FOREVER 0xff
#define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index a2b1e9e..452840d 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -781,6 +781,27 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
}
}
+static u32 calculate_mcr(u32 mcr, struct drm_i915_private *dev_priv)
+{
+ const struct sseu_dev_info *sseu = &(INTEL_SSEU(dev_priv));
+ u32 slice = fls(sseu->slice_mask);
+ u32 subslice = fls(sseu->subslice_mask[slice]);
+
+ mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
+ mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
+
+ return mcr;
+}
+
+static void wa_init_mcr(struct drm_i915_private *dev_priv)
+{
+ u32 mcr;
+
+ mcr = I915_READ(GEN8_MCR_SELECTOR);
+ mcr = calculate_mcr(mcr, dev_priv);
+ I915_WRITE(GEN8_MCR_SELECTOR, mcr);
+}
+
static inline uint32_t
read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
int subslice, i915_reg_t reg)
@@ -799,18 +820,31 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
+
/*
* The HW expects the slice and sublice selectors to be reset to 0
* after reading out the registers.
*/
- WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK));
+ if (INTEL_GEN(dev_priv) < 10)
+ WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK |
+ GEN8_MCR_SUBSLICE_MASK));
+
mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
ret = I915_READ_FW(reg);
- mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
+ /*
+ * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
+ * expects mcr to be programed to a enabled slice/subslice pair
+ * before any MMIO read into slice/subslice register
+ */
+ if (INTEL_GEN(dev_priv) < 10)
+ mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
+ else
+ mcr = calculate_mcr(mcr, dev_priv);
+
I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
@@ -1278,6 +1312,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
struct drm_i915_private *dev_priv = engine->i915;
int ret;
+ /* WaProgramMgsrForCorrectSliceSpecificMmioReads: cnl */
+ wa_init_mcr(dev_priv);
+
/* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
I915_WRITE(GAMT_CHKN_BIT_REG,
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads
2018-03-22 16:59 [PATCH 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads Yunwei Zhang
@ 2018-03-22 16:59 ` Yunwei Zhang
2018-03-22 17:15 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads Patchwork
1 sibling, 0 replies; 8+ messages in thread
From: Yunwei Zhang @ 2018-03-22 16:59 UTC (permalink / raw)
To: intel-gfx
L3Bank could be fused off in hardware for debug purpose, and it
is possible that subslice is enabled while its corresponding L3Bank pairs
are disabled. In such case, if MCR packet control register(0xFDC) is
programed to point to a disabled bank pair, a MMIO read into L3Bank range
will return 0 instead of correct values.
However, this is not going to be the case in any production silicon.
Therefore, we only check at initialization and issue a warning should
this really happen.
v2:
- use fls instead of find_last_bit
- use is_power_of_2() instead of counting bit set
Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
drivers/gpu/drm/i915/intel_engine_cs.c | 18 ++++++++++++++++++
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index abdc513..b283427 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2849,6 +2849,10 @@ enum i915_power_well_id {
#define GEN10_F2_SS_DIS_SHIFT 18
#define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)
+#define GEN10_MIRROR_FUSE3 _MMIO(0x9118)
+#define GEN10_L3BANK_PAIR_COUNT 4
+#define GEN10_L3BANK_MASK 0x0F
+
#define GEN8_EU_DISABLE0 _MMIO(0x9134)
#define GEN8_EU_DIS0_S0_MASK 0xffffff
#define GEN8_EU_DIS0_S1_SHIFT 24
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 452840d..6d38a6d 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -796,7 +796,25 @@ static u32 calculate_mcr(u32 mcr, struct drm_i915_private *dev_priv)
static void wa_init_mcr(struct drm_i915_private *dev_priv)
{
u32 mcr;
+ u32 fuse3;
+ const struct sseu_dev_info *sseu = &(INTEL_SSEU(dev_priv));
+ u32 slice;
+ /* If more than one slice are enabled, L3Banks should be all enabled */
+ if (is_power_of_2(sseu->slice_mask)) {
+ /*
+ * WaProgramMgsrForL3BankSpecificMmioReads:
+ * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
+ * enabled subslice, no need to redirect MCR packet
+ */
+ slice = fls(sseu->slice_mask);
+ fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
+ if (WARN_ON(!((fuse3 & GEN10_L3BANK_MASK)
+ & ((sseu->subslice_mask[slice]
+ | sseu->subslice_mask[slice]>>GEN10_L3BANK_PAIR_COUNT)
+ & GEN10_L3BANK_MASK))))
+ DRM_WARN("Production silicon should have matched L3Bank and subslice enabled\n");
+ }
mcr = I915_READ(GEN8_MCR_SELECTOR);
mcr = calculate_mcr(mcr, dev_priv);
I915_WRITE(GEN8_MCR_SELECTOR, mcr);
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads
2018-03-22 16:59 [PATCH 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads Yunwei Zhang
2018-03-22 16:59 ` [PATCH 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads Yunwei Zhang
@ 2018-03-22 17:15 ` Patchwork
1 sibling, 0 replies; 8+ messages in thread
From: Patchwork @ 2018-03-22 17:15 UTC (permalink / raw)
To: Yunwei Zhang; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads
URL : https://patchwork.freedesktop.org/series/40495/
State : failure
== Summary ==
Applying: drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads
error: Failed to merge in the changes.
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/i915_drv.h
M drivers/gpu/drm/i915/intel_engine_cs.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_engine_cs.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_engine_cs.c
Auto-merging drivers/gpu/drm/i915/i915_drv.h
Patch failed at 0001 drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads
@ 2018-03-22 18:05 Yunwei Zhang
2018-03-23 8:50 ` Mika Kuoppala
0 siblings, 1 reply; 8+ messages in thread
From: Yunwei Zhang @ 2018-03-22 18:05 UTC (permalink / raw)
To: intel-gfx
WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value will be returned.
However, that means each subsequent MMIO read will be forwarded to a
specific slice/subslice combination as read is unicast. This is OK since
slice/subslice specific register values are consistent in almost all cases
across slice/subslice. There are rare occasions such as INSTDONE that this
value will be dependent on slice/subslice combo, in such cases, we need to
program 0xFDC and recover this after. This is already covered by
read_subslice_reg for INSTDONE.
Also, 0xFDC will lose its information after TDR/engine reset/power state
change.
v2:
- use fls() instead of find_last_bit() (Chris)
- added INTEL_SSEU to extract sseu from device info. (Chris)
v3:
- rebase on latest tip
Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_engine_cs.c | 39 ++++++++++++++++++++++++++++++++--
2 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c9c3b2b..d902c50 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2296,6 +2296,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
#define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
+#define INTEL_SSEU(dev_priv) ((dev_priv)->info.sseu)
#define REVID_FOREVER 0xff
#define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index de09fa4..cc19e0a 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -796,6 +796,27 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
}
}
+static u32 calculate_mcr(u32 mcr, struct drm_i915_private *dev_priv)
+{
+ const struct sseu_dev_info *sseu = &(INTEL_SSEU(dev_priv));
+ u32 slice = fls(sseu->slice_mask);
+ u32 subslice = fls(sseu->subslice_mask[slice]);
+
+ mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
+ mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
+
+ return mcr;
+}
+
+static void wa_init_mcr(struct drm_i915_private *dev_priv)
+{
+ u32 mcr;
+
+ mcr = I915_READ(GEN8_MCR_SELECTOR);
+ mcr = calculate_mcr(mcr, dev_priv);
+ I915_WRITE(GEN8_MCR_SELECTOR, mcr);
+}
+
static inline uint32_t
read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
int subslice, i915_reg_t reg)
@@ -828,18 +849,29 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
+
/*
* The HW expects the slice and sublice selectors to be reset to 0
* after reading out the registers.
*/
- WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
+ if (INTEL_GEN(dev_priv) < 10)
+ WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
mcr &= ~mcr_slice_subslice_mask;
mcr |= mcr_slice_subslice_select;
I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
ret = I915_READ_FW(reg);
- mcr &= ~mcr_slice_subslice_mask;
+ /*
+ * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
+ * expects mcr to be programed to a enabled slice/subslice pair
+ * before any MMIO read into slice/subslice register
+ */
+ if (INTEL_GEN(dev_priv) < 10)
+ mcr &= ~mcr_slice_subslice_mask;
+ else
+ mcr = calculate_mcr(mcr, dev_priv);
+
I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
@@ -1307,6 +1339,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
struct drm_i915_private *dev_priv = engine->i915;
int ret;
+ /* WaProgramMgsrForCorrectSliceSpecificMmioReads: cnl */
+ wa_init_mcr(dev_priv);
+
/* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
I915_WRITE(GAMT_CHKN_BIT_REG,
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads
2018-03-22 18:05 [PATCH 1/2] " Yunwei Zhang
@ 2018-03-23 8:50 ` Mika Kuoppala
0 siblings, 0 replies; 8+ messages in thread
From: Mika Kuoppala @ 2018-03-23 8:50 UTC (permalink / raw)
To: Yunwei Zhang, intel-gfx
Hi,
Yunwei Zhang <yunwei.zhang@intel.com> writes:
> WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
> read into Slice/Subslice specific registers, MCR packet control
> register(0xFDC) needs to be programmed to point to any enabled
> slice/subslice pair. Otherwise, incorrect value will be returned.
>
> However, that means each subsequent MMIO read will be forwarded to a
> specific slice/subslice combination as read is unicast. This is OK since
> slice/subslice specific register values are consistent in almost all cases
> across slice/subslice. There are rare occasions such as INSTDONE that this
> value will be dependent on slice/subslice combo, in such cases, we need to
> program 0xFDC and recover this after. This is already covered by
> read_subslice_reg for INSTDONE.
>
> Also, 0xFDC will lose its information after TDR/engine reset/power state
> change.
>
> v2:
> - use fls() instead of find_last_bit() (Chris)
> - added INTEL_SSEU to extract sseu from device info. (Chris)
> v3:
> - rebase on latest tip
>
Please add the relevant bspec id's and/or hsds
as a references into both patches.
For example see commit 86ebb015fa744dd1e265c9b45ade870ac859a4d5
-Mika
> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_engine_cs.c | 39 ++++++++++++++++++++++++++++++++--
> 2 files changed, 38 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c9c3b2b..d902c50 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2296,6 +2296,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>
> #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
> #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
> +#define INTEL_SSEU(dev_priv) ((dev_priv)->info.sseu)
>
> #define REVID_FOREVER 0xff
> #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index de09fa4..cc19e0a 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -796,6 +796,27 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
> }
> }
>
> +static u32 calculate_mcr(u32 mcr, struct drm_i915_private *dev_priv)
> +{
> + const struct sseu_dev_info *sseu = &(INTEL_SSEU(dev_priv));
> + u32 slice = fls(sseu->slice_mask);
> + u32 subslice = fls(sseu->subslice_mask[slice]);
> +
> + mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
> + mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
> +
> + return mcr;
> +}
> +
> +static void wa_init_mcr(struct drm_i915_private *dev_priv)
> +{
> + u32 mcr;
> +
> + mcr = I915_READ(GEN8_MCR_SELECTOR);
> + mcr = calculate_mcr(mcr, dev_priv);
> + I915_WRITE(GEN8_MCR_SELECTOR, mcr);
> +}
> +
> static inline uint32_t
> read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
> int subslice, i915_reg_t reg)
> @@ -828,18 +849,29 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
> intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
>
> mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
> +
> /*
> * The HW expects the slice and sublice selectors to be reset to 0
> * after reading out the registers.
> */
> - WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
> + if (INTEL_GEN(dev_priv) < 10)
> + WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
> mcr &= ~mcr_slice_subslice_mask;
> mcr |= mcr_slice_subslice_select;
> I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>
> ret = I915_READ_FW(reg);
>
> - mcr &= ~mcr_slice_subslice_mask;
> + /*
> + * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
> + * expects mcr to be programed to a enabled slice/subslice pair
> + * before any MMIO read into slice/subslice register
> + */
> + if (INTEL_GEN(dev_priv) < 10)
> + mcr &= ~mcr_slice_subslice_mask;
> + else
> + mcr = calculate_mcr(mcr, dev_priv);
> +
> I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>
> intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
> @@ -1307,6 +1339,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
> struct drm_i915_private *dev_priv = engine->i915;
> int ret;
>
> + /* WaProgramMgsrForCorrectSliceSpecificMmioReads: cnl */
> + wa_init_mcr(dev_priv);
> +
> /* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
> if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
> I915_WRITE(GAMT_CHKN_BIT_REG,
> --
> 2.7.4
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads
@ 2018-03-19 21:50 Yunwei Zhang
2018-03-19 22:08 ` Chris Wilson
0 siblings, 1 reply; 8+ messages in thread
From: Yunwei Zhang @ 2018-03-19 21:50 UTC (permalink / raw)
To: intel-gfx
WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value will be returned.
However, that means each subsequent MMIO read will be forwarded to a
specific slice/subslice combination as read is unicast. This is OK since
slice/subslice specific register values are consistent in almost all cases
across slice/subslice. There are rare occasions such as INSTDONE that this
value will be dependent on slice/subslice combo, in such cases, we need to
program 0xFDC and recover this after. This is already covered by
read_subslice_reg for INSTDONE.
Also, 0xFDC will lose its information after TDR/engine reset/power state
change.
Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 43 ++++++++++++++++++++++++++++++++--
1 file changed, 41 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index a2b1e9e..bc8fed7 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -781,6 +781,29 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
}
}
+static u32 calculate_mcr(u32 mcr, struct drm_i915_private *dev_priv)
+{
+ const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
+ u32 slice = find_last_bit((unsigned long *)&(sseu->slice_mask),
+ sizeof(sseu->slice_mask));
+ u32 subslice = find_last_bit((unsigned long *)&(sseu->subslice_mask[slice]),
+ sizeof(sseu->subslice_mask[0]));
+
+ mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
+ mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
+
+ return mcr;
+}
+
+static void wa_init_mcr(struct drm_i915_private *dev_priv)
+{
+ u32 mcr;
+
+ mcr = I915_READ(GEN8_MCR_SELECTOR);
+ mcr = calculate_mcr(mcr, dev_priv);
+ I915_WRITE(GEN8_MCR_SELECTOR, mcr);
+}
+
static inline uint32_t
read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
int subslice, i915_reg_t reg)
@@ -799,18 +822,31 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
+
/*
* The HW expects the slice and sublice selectors to be reset to 0
* after reading out the registers.
*/
- WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK));
+ if (INTEL_GEN(dev_priv) < 10)
+ WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK |
+ GEN8_MCR_SUBSLICE_MASK));
+
mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
ret = I915_READ_FW(reg);
- mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
+ /*
+ * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
+ * expects mcr to be programed to a enabled slice/subslice pair
+ * before any MMIO read into slice/subslice register
+ */
+ if (INTEL_GEN(dev_priv) < 10)
+ mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
+ else
+ mcr = calculate_mcr(mcr, dev_priv);
+
I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
@@ -1278,6 +1314,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
struct drm_i915_private *dev_priv = engine->i915;
int ret;
+ /* WaProgramMgsrForCorrectSliceSpecificMmioReads: cnl */
+ wa_init_mcr(dev_priv);
+
/* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
I915_WRITE(GAMT_CHKN_BIT_REG,
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads
2018-03-19 21:50 Yunwei Zhang
@ 2018-03-19 22:08 ` Chris Wilson
0 siblings, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2018-03-19 22:08 UTC (permalink / raw)
To: Yunwei Zhang, intel-gfx
Quoting Yunwei Zhang (2018-03-19 21:50:07)
> WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
> read into Slice/Subslice specific registers, MCR packet control
> register(0xFDC) needs to be programmed to point to any enabled
> slice/subslice pair. Otherwise, incorrect value will be returned.
>
> However, that means each subsequent MMIO read will be forwarded to a
> specific slice/subslice combination as read is unicast. This is OK since
> slice/subslice specific register values are consistent in almost all cases
> across slice/subslice. There are rare occasions such as INSTDONE that this
> value will be dependent on slice/subslice combo, in such cases, we need to
> program 0xFDC and recover this after. This is already covered by
> read_subslice_reg for INSTDONE.
>
> Also, 0xFDC will lose its information after TDR/engine reset/power state
> change.
>
> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_engine_cs.c | 43 ++++++++++++++++++++++++++++++++--
> 1 file changed, 41 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index a2b1e9e..bc8fed7 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -781,6 +781,29 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
> }
> }
>
> +static u32 calculate_mcr(u32 mcr, struct drm_i915_private *dev_priv)
> +{
> + const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
INTEL_SSEU(dev_priv);
> + u32 slice = find_last_bit((unsigned long *)&(sseu->slice_mask),
> + sizeof(sseu->slice_mask));
> + u32 subslice = find_last_bit((unsigned long *)&(sseu->subslice_mask[slice]),
> + sizeof(sseu->subslice_mask[0]));
You seem to have mispelt fls().
Or send a patch to convert find_last_bit() into fls() for known small
sizes.
-Chris
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads
@ 2018-03-14 23:22 Yunwei Zhang
0 siblings, 0 replies; 8+ messages in thread
From: Yunwei Zhang @ 2018-03-14 23:22 UTC (permalink / raw)
To: intel-gfx
WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value will be returned.
However, that means each subsequent MMIO read will be forwarded to a
specific slice/subslice combination as read is unicast. This is OK since
slice/subslice specific register values are consistent in almost all cases
across slice/subslice. There are rare occasions such as INSTDONE that this
value will be dependent on slice/subslice combo, in such cases, we need to
program 0xFDC and recover this after. This is already covered by
read_subslice_reg for INSTDONE.
Also, 0xFDC will lose its information after TDR/engine reset/power state
change.
Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 43 ++++++++++++++++++++++++++++++++--
1 file changed, 41 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index a2b1e9e..bc8fed7 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -781,6 +781,29 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
}
}
+static u32 calculate_mcr(u32 mcr, struct drm_i915_private *dev_priv)
+{
+ const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
+ u32 slice = find_last_bit((unsigned long *)&(sseu->slice_mask),
+ sizeof(sseu->slice_mask));
+ u32 subslice = find_last_bit((unsigned long *)&(sseu->subslice_mask[slice]),
+ sizeof(sseu->subslice_mask[0]));
+
+ mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
+ mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
+
+ return mcr;
+}
+
+static void wa_init_mcr(struct drm_i915_private *dev_priv)
+{
+ u32 mcr;
+
+ mcr = I915_READ(GEN8_MCR_SELECTOR);
+ mcr = calculate_mcr(mcr, dev_priv);
+ I915_WRITE(GEN8_MCR_SELECTOR, mcr);
+}
+
static inline uint32_t
read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
int subslice, i915_reg_t reg)
@@ -799,18 +822,31 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
+
/*
* The HW expects the slice and sublice selectors to be reset to 0
* after reading out the registers.
*/
- WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK));
+ if (INTEL_GEN(dev_priv) < 10)
+ WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK |
+ GEN8_MCR_SUBSLICE_MASK));
+
mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
ret = I915_READ_FW(reg);
- mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
+ /*
+ * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
+ * expects mcr to be programed to a enabled slice/subslice pair
+ * before any MMIO read into slice/subslice register
+ */
+ if (INTEL_GEN(dev_priv) < 10)
+ mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
+ else
+ mcr = calculate_mcr(mcr, dev_priv);
+
I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
@@ -1278,6 +1314,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
struct drm_i915_private *dev_priv = engine->i915;
int ret;
+ /* WaProgramMgsrForCorrectSliceSpecificMmioReads: cnl */
+ wa_init_mcr(dev_priv);
+
/* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
I915_WRITE(GAMT_CHKN_BIT_REG,
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2018-03-23 8:50 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-03-22 16:59 [PATCH 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads Yunwei Zhang
2018-03-22 16:59 ` [PATCH 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads Yunwei Zhang
2018-03-22 17:15 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads Patchwork
-- strict thread matches above, loose matches on Subject: below --
2018-03-22 18:05 [PATCH 1/2] " Yunwei Zhang
2018-03-23 8:50 ` Mika Kuoppala
2018-03-19 21:50 Yunwei Zhang
2018-03-19 22:08 ` Chris Wilson
2018-03-14 23:22 Yunwei Zhang
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