From: Michel Pollet <michel.pollet@bp.renesas.com> To: linux-renesas-soc@vger.kernel.org, Simon Horman <horms@verge.net.au> Cc: phil.edworthy@renesas.com, buserror+upstream@gmail.com, Michel Pollet <michel.pollet@bp.renesas.com>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Magnus Damm <magnus.damm@gmail.com>, Russell King <linux@armlinux.org.uk>, Carlo Caione <carlo@endlessm.com>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Rajendra Nayak <rnayak@codeaurora.org>, Stefan Wahren <stefan.wahren@i2se.com>, Frank Rowand <frank.rowand@sony.com>, Juri Lelli <juri.lelli@arm.com>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [RFC 1/3] dt-bindings: cpu: Add Renesas RZ/N1D SMP enable method. Date: Mon, 16 Apr 2018 10:34:57 +0100 [thread overview] Message-ID: <1523871304-48517-3-git-send-email-michel.pollet@bp.renesas.com> (raw) In-Reply-To: <1523871304-48517-1-git-send-email-michel.pollet@bp.renesas.com> Add a special enable method for second CA8 of the Renesas RZ/N1D (R9A06G032). Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> --- Documentation/devicetree/bindings/arm/cpus.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 29e1dc5..b395d107 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -219,6 +219,7 @@ described below. "qcom,kpss-acc-v1" "qcom,kpss-acc-v2" "renesas,apmu" + "renesas,r9a06g032-smp" "rockchip,rk3036-smp" "rockchip,rk3066-smp" "ste,dbx500-smp" -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: michel.pollet@bp.renesas.com (Michel Pollet) To: linux-arm-kernel@lists.infradead.org Subject: [RFC 1/3] dt-bindings: cpu: Add Renesas RZ/N1D SMP enable method. Date: Mon, 16 Apr 2018 10:34:57 +0100 [thread overview] Message-ID: <1523871304-48517-3-git-send-email-michel.pollet@bp.renesas.com> (raw) In-Reply-To: <1523871304-48517-1-git-send-email-michel.pollet@bp.renesas.com> Add a special enable method for second CA8 of the Renesas RZ/N1D (R9A06G032). Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> --- Documentation/devicetree/bindings/arm/cpus.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 29e1dc5..b395d107 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -219,6 +219,7 @@ described below. "qcom,kpss-acc-v1" "qcom,kpss-acc-v2" "renesas,apmu" + "renesas,r9a06g032-smp" "rockchip,rk3036-smp" "rockchip,rk3066-smp" "ste,dbx500-smp" -- 2.7.4
next prev parent reply other threads:[~2018-04-16 9:34 UTC|newest] Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-04-16 9:34 [RFC 0/3] Renesas RZ/N1D SMP enabler Michel Pollet 2018-04-16 9:34 ` Michel Pollet 2018-04-16 9:34 ` Michel Pollet 2018-04-16 9:34 ` [PATCH 1/1] arm: rzn1: Add support for the second CPU Michel Pollet 2018-04-16 9:34 ` Michel Pollet 2018-04-16 9:34 ` Michel Pollet [this message] 2018-04-16 9:34 ` [RFC 1/3] dt-bindings: cpu: Add Renesas RZ/N1D SMP enable method Michel Pollet 2018-04-16 21:37 ` Rob Herring 2018-04-16 21:37 ` Rob Herring 2018-04-16 9:34 ` [RFC 2/3] ARM: dts: " Michel Pollet 2018-04-16 9:34 ` Michel Pollet 2018-04-16 9:34 ` [RFC 3/3] arm: shmobile: Add the RZ/N1D SMP enabler driver Michel Pollet 2018-04-16 9:34 ` Michel Pollet 2018-04-16 21:46 ` Florian Fainelli 2018-04-16 21:46 ` Florian Fainelli 2018-04-17 9:32 ` Michel Pollet 2018-04-17 9:32 ` Michel Pollet 2018-04-17 9:32 ` Michel Pollet
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