All of lore.kernel.org
 help / color / mirror / Atom feed
From: Luwei Kang <luwei.kang@intel.com>
To: kvm@vger.kernel.org
Cc: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com,
	x86@kernel.org, pbonzini@redhat.com, rkrcmar@redhat.com,
	linux-kernel@vger.kernel.org, joro@8bytes.org,
	peterz@infradead.org, chao.p.peng@linux.intel.com,
	Luwei Kang <luwei.kang@intel.com>
Subject: [PATCH v7 07/13] KVM: x86: Add Intel Processor Trace cpuid emulation
Date: Thu,  3 May 2018 20:08:37 +0800	[thread overview]
Message-ID: <1525349323-9938-8-git-send-email-luwei.kang@intel.com> (raw)
In-Reply-To: <1525349323-9938-1-git-send-email-luwei.kang@intel.com>

From: Chao Peng <chao.p.peng@linux.intel.com>

Expose Intel Processor Trace to guest only when PT work in
HOST_GUEST mode.

Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
 arch/x86/include/asm/kvm_host.h |  1 +
 arch/x86/kvm/cpuid.c            | 22 ++++++++++++++++++++--
 arch/x86/kvm/svm.c              |  6 ++++++
 arch/x86/kvm/vmx.c              |  6 ++++++
 4 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index c25775f..03875aa 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -1025,6 +1025,7 @@ struct kvm_x86_ops {
 	bool (*mpx_supported)(void);
 	bool (*xsaves_supported)(void);
 	bool (*umip_emulated)(void);
+	bool (*pt_supported)(void);
 
 	int (*check_nested_events)(struct kvm_vcpu *vcpu, bool external_intr);
 
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 82055b9..e04bf67 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -336,6 +336,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
 	unsigned f_mpx = kvm_mpx_supported() ? F(MPX) : 0;
 	unsigned f_xsaves = kvm_x86_ops->xsaves_supported() ? F(XSAVES) : 0;
 	unsigned f_umip = kvm_x86_ops->umip_emulated() ? F(UMIP) : 0;
+	unsigned f_intel_pt = kvm_x86_ops->pt_supported() ? F(INTEL_PT) : 0;
 
 	/* cpuid 1.edx */
 	const u32 kvm_cpuid_1_edx_x86_features =
@@ -393,7 +394,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
 		F(BMI2) | F(ERMS) | f_invpcid | F(RTM) | f_mpx | F(RDSEED) |
 		F(ADX) | F(SMAP) | F(AVX512IFMA) | F(AVX512F) | F(AVX512PF) |
 		F(AVX512ER) | F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(AVX512DQ) |
-		F(SHA_NI) | F(AVX512BW) | F(AVX512VL);
+		F(SHA_NI) | F(AVX512BW) | F(AVX512VL) | f_intel_pt;
 
 	/* cpuid 0xD.1.eax */
 	const u32 kvm_cpuid_D_1_eax_x86_features =
@@ -423,7 +424,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
 
 	switch (function) {
 	case 0:
-		entry->eax = min(entry->eax, (u32)0xd);
+		entry->eax = min(entry->eax, (u32)(f_intel_pt ? 0x14 : 0xd));
 		break;
 	case 1:
 		entry->edx &= kvm_cpuid_1_edx_x86_features;
@@ -595,6 +596,23 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
 		}
 		break;
 	}
+	/* Intel PT */
+	case 0x14: {
+		int t, times = entry->eax;
+
+		if (!f_intel_pt)
+			break;
+
+		entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
+		for (t = 1; t <= times; ++t) {
+			if (*nent >= maxnent)
+				goto out;
+			do_cpuid_1_ent(&entry[t], function, t);
+			entry[t].flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
+			++*nent;
+		}
+		break;
+	}
 	case KVM_CPUID_SIGNATURE: {
 		static const char signature[12] = "KVMKVMKVM\0\0";
 		const u32 *sigptr = (const u32 *)signature;
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 80ea262..23a1ef9 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -5877,6 +5877,11 @@ static bool svm_umip_emulated(void)
 	return false;
 }
 
+static bool svm_pt_supported(void)
+{
+	return false;
+}
+
 static bool svm_has_wbinvd_exit(void)
 {
 	return true;
@@ -7102,6 +7107,7 @@ static int svm_unregister_enc_region(struct kvm *kvm,
 	.mpx_supported = svm_mpx_supported,
 	.xsaves_supported = svm_xsaves_supported,
 	.umip_emulated = svm_umip_emulated,
+	.pt_supported = svm_pt_supported,
 
 	.set_supported_cpuid = svm_set_supported_cpuid,
 
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 8680cd5..27cf417 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -9563,6 +9563,11 @@ static bool vmx_umip_emulated(void)
 		SECONDARY_EXEC_DESC;
 }
 
+static bool vmx_pt_supported(void)
+{
+	return (pt_mode == PT_MODE_HOST_GUEST);
+}
+
 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
 {
 	u32 exit_intr_info;
@@ -12790,6 +12795,7 @@ static int enable_smi_window(struct kvm_vcpu *vcpu)
 	.mpx_supported = vmx_mpx_supported,
 	.xsaves_supported = vmx_xsaves_supported,
 	.umip_emulated = vmx_umip_emulated,
+	.pt_supported = vmx_pt_supported,
 
 	.check_nested_events = vmx_check_nested_events,
 
-- 
1.8.3.1

  parent reply	other threads:[~2018-05-03 10:15 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-03 12:08 [PATCH v7 00/13] Intel Processor Trace virtualization enabling Luwei Kang
2018-05-03 10:33 ` Alexander Shishkin
2018-05-03 12:08 ` [PATCH v7 01/13] perf/x86/intel/pt: Move Intel-PT MSRs bit definitions to a public header Luwei Kang
2018-05-03 12:08 ` [PATCH v7 02/13] perf/x86/intel/pt: Change pt_cap_get() to a public function Luwei Kang
2018-05-03 12:08 ` [PATCH v7 03/13] perf/x86/intel/pt: Add new bit definitions for Intel PT MSRs Luwei Kang
2018-05-03 12:08 ` [PATCH v7 04/13] perf/x86/intel/pt: add new capability for Intel PT Luwei Kang
2018-05-03 12:08 ` [PATCH v7 05/13] perf/x86/intel/pt: Introduce a new function to get capability of " Luwei Kang
2018-05-03 10:50   ` Alexander Shishkin
2018-05-03 11:04     ` Kang, Luwei
2018-05-03 12:13       ` Alexander Shishkin
2018-05-03 12:30         ` Paolo Bonzini
2018-05-03 12:30         ` Kang, Luwei
2018-05-03 12:32           ` Paolo Bonzini
2018-05-03 12:50             ` Kang, Luwei
2018-05-03 12:59               ` Alexander Shishkin
2018-05-03 12:08 ` [PATCH v7 06/13] KVM: x86: Add Intel Processor Trace virtualization mode Luwei Kang
2018-05-03 11:32   ` Alexander Shishkin
2018-05-03 11:50     ` Paolo Bonzini
2018-05-03 12:02       ` Alexander Shishkin
2018-05-03 12:30         ` Paolo Bonzini
2018-05-03 12:48           ` Alexander Shishkin
2018-05-03 12:50             ` Paolo Bonzini
2018-05-03 13:38               ` Alexander Shishkin
2018-05-03 13:48                 ` Paolo Bonzini
2018-05-04 10:38                   ` Alexander Shishkin
2018-05-04 21:52                     ` Paolo Bonzini
2018-05-04 10:45                 ` Peter Zijlstra
2018-05-04 21:44                   ` Paolo Bonzini
2018-05-04 22:15                     ` Peter Zijlstra
2018-05-07 10:47                       ` Paolo Bonzini
2018-05-03 11:52     ` Paolo Bonzini
2018-05-03 12:09       ` Alexander Shishkin
2018-05-03 12:31         ` Paolo Bonzini
2018-05-03 12:08 ` Luwei Kang [this message]
2018-05-03 12:08 ` [PATCH v7 08/13] KVM: x86: Add Intel processor trace context for each vcpu Luwei Kang
2018-05-03 11:39   ` Alexander Shishkin
2018-05-03 11:53     ` Paolo Bonzini
2018-05-03 12:08 ` [PATCH v7 09/13] KVM: x86: Implement Intel Processor Trace context switch Luwei Kang
2018-05-04 10:29   ` Alexander Shishkin
2018-05-04 21:49     ` Paolo Bonzini
2018-05-03 12:08 ` [PATCH v7 10/13] KVM: x86: Introduce a function to initialize the PT configuration Luwei Kang
2018-05-03 12:08 ` [PATCH v7 11/13] KVM: x86: Implement Intel Processor Trace MSRs read/write Luwei Kang
2018-05-04 10:11   ` Alexander Shishkin
2018-05-04 21:47     ` Paolo Bonzini
2018-05-03 12:08 ` [PATCH v7 12/13] KVM: x86: Set intercept for Intel PT " Luwei Kang
2018-05-03 12:08 ` [PATCH v7 13/13] KVM: x86: Disable Intel Processor Trace when VMXON in L1 guest Luwei Kang
2018-05-04 10:23   ` Alexander Shishkin
2018-05-04 21:49     ` Paolo Bonzini
2018-05-03 12:13 [PATCH v7 00/13] Intel Processor Trace virtualization enabling Luwei Kang
2018-05-03 12:13 ` [PATCH v7 07/13] KVM: x86: Add Intel Processor Trace cpuid emulation Luwei Kang

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1525349323-9938-8-git-send-email-luwei.kang@intel.com \
    --to=luwei.kang@intel.com \
    --cc=chao.p.peng@linux.intel.com \
    --cc=hpa@zytor.com \
    --cc=joro@8bytes.org \
    --cc=kvm@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mingo@redhat.com \
    --cc=pbonzini@redhat.com \
    --cc=peterz@infradead.org \
    --cc=rkrcmar@redhat.com \
    --cc=tglx@linutronix.de \
    --cc=x86@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.