* [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
@ 2018-05-08 21:29 ` Oscar Mateo
2018-05-11 12:37 ` Mika Kuoppala
2018-05-08 21:29 ` [PATCH 02/22] drm/i915/icl: Enable Sampler DFR Oscar Mateo
` (25 subsequent siblings)
26 siblings, 1 reply; 42+ messages in thread
From: Oscar Mateo @ 2018-05-08 21:29 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Inherit workarounds from previous platforms that are still valid for
Icelake.
v2: GEN7_ROW_CHICKEN2 is masked
v3:
- Since it has been fixed already in upstream, removed the TODO
comment about WA_SET_BIT for WaInPlaceDecompressionHang.
- Squashed with this patch:
drm/i915/icl: add icelake_init_clock_gating()
from Paulo Zanoni <paulo.r.zanoni@intel.com>
- Squashed with this patch:
drm/i915/icl: WaForceEnableNonCoherent
from Oscar Mateo <oscar.mateo@intel.com>
- WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
applies to B0 as well.
- WaPipeControlBefore3DStateSamplePattern WABB was being applied
to ICL incorrectly.
v4:
- Wrap the commit message
- s/dev_priv/p to please checkpatch
v5: Rebased on top of the WA refactoring
v6: Rebased on top of further whitelist registers refactoring (Michel)
v7: Added WaRsForcewakeAddDelayForAck
v8: s/ICL_HDC_CHICKEN0/ICL_HDC_MODE (Mika)
v9:
- C, not lisp (Chris)
- WaIncreaseDefaultTLBEntries is the same for GEN > 9_LP (Tvrtko)
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Tomasz Lis <tomasz.lis@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 9 +++++++
drivers/gpu/drm/i915/i915_gem_gtt.c | 6 ++---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_lrc.c | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 4 ++-
drivers/gpu/drm/i915/intel_uncore.c | 7 +++--
drivers/gpu/drm/i915/intel_workarounds.c | 46 ++++++++++++++++++++++++++++++++
7 files changed, 69 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 04e2780..ad79d5a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2469,6 +2469,15 @@ static inline unsigned int i915_sg_segment_size(void)
#define IS_CNL_REVID(p, since, until) \
(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
+#define ICL_REVID_A0 0x0
+#define ICL_REVID_A2 0x1
+#define ICL_REVID_B0 0x3
+#define ICL_REVID_B2 0x4
+#define ICL_REVID_C0 0x5
+
+#define IS_ICL_REVID(p, since, until) \
+ (IS_ICELAKE(p) && IS_REVID(p, since, until))
+
/*
* The genX designation typically refers to the render engine, so render
* capability related checks should use IS_GEN, while display and other checks
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c879bfd..ea30e84 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2137,15 +2137,15 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
* called on driver load and after a GPU reset, so you can place
* workarounds here even if they get overwritten by GPU reset.
*/
- /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
+ /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
if (IS_BROADWELL(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
else if (IS_CHERRYVIEW(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
- else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
- I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
else if (IS_GEN9_LP(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
+ else if (INTEL_GEN(dev_priv) >= 9)
+ I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
/*
* To support 64K PTEs we need to first enable the use of the
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 085928c..2b22d4d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7238,6 +7238,7 @@ enum {
/* GEN8 chicken */
#define HDC_CHICKEN0 _MMIO(0x7300)
#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
+#define ICL_HDC_MODE _MMIO(0xE5F4)
#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
#define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 911f288..920752a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1665,6 +1665,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
return -EINVAL;
switch (INTEL_GEN(engine->i915)) {
+ case 11:
+ return 0;
case 10:
wa_bb_fn[0] = gen10_init_indirectctx_bb;
wa_bb_fn[1] = NULL;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4126132..9c6e48c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9190,7 +9190,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
*/
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_CANNONLAKE(dev_priv))
+ if (IS_ICELAKE(dev_priv))
+ dev_priv->display.init_clock_gating = nop_init_clock_gating;
+ else if (IS_CANNONLAKE(dev_priv))
dev_priv->display.init_clock_gating = cnl_init_clock_gating;
else if (IS_COFFEELAKE(dev_priv))
dev_priv->display.init_clock_gating = cfl_init_clock_gating;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index d6e20f0..448293e 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -139,7 +139,9 @@ enum ack_type {
* in the hope that the original ack will be delivered along with
* the fallback ack.
*
- * This workaround is described in HSDES #1604254524
+ * This workaround is described in HSDES #1604254524 and it's known as:
+ * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
+ * although the name is a bit misleading.
*/
pass = 1;
@@ -1394,7 +1396,8 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
if (INTEL_GEN(dev_priv) >= 11) {
int i;
- dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
+ dev_priv->uncore.funcs.force_wake_get =
+ fw_domains_get_with_fallback;
dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
FORCEWAKE_RENDER_GEN9,
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index ec9d340..73d02d3 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -441,6 +441,27 @@ static int cnl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
return 0;
}
+static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
+{
+ /* Wa_1604370585:icl (pre-prod)
+ * Formerly known as WaPushConstantDereferenceHoldDisable
+ */
+ if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+ WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+ PUSH_CONSTANT_DEREF_DISABLE);
+
+ /* WaForceEnableNonCoherent:icl
+ * This is not the same workaround as in early Gen9 platforms, where
+ * lacking this could cause system hangs, but coherency performance
+ * overhead is high and only a few compute workloads really need it
+ * (the register is whitelisted in hardware now, so UMDs can opt in
+ * for coherency if they have a good reason).
+ */
+ WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
+
+ return 0;
+}
+
int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
{
int err = 0;
@@ -465,6 +486,8 @@ int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
err = cfl_ctx_workarounds_init(dev_priv);
else if (IS_CANNONLAKE(dev_priv))
err = cnl_ctx_workarounds_init(dev_priv);
+ else if (IS_ICELAKE(dev_priv))
+ err = icl_ctx_workarounds_init(dev_priv);
else
MISSING_CASE(INTEL_GEN(dev_priv));
if (err)
@@ -663,6 +686,21 @@ static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
_MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
}
+static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
+{
+ /* This is not an Wa. Enable for better image quality */
+ I915_WRITE(_3D_CHICKEN3,
+ _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
+
+ /* WaInPlaceDecompressionHang:icl */
+ I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+
+ /* WaPipelineFlushCoherentLines:icl */
+ I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
+ GEN8_LQSC_FLUSH_COHERENT_LINES);
+}
+
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
{
if (INTEL_GEN(dev_priv) < 8)
@@ -683,6 +721,8 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
cfl_gt_workarounds_apply(dev_priv);
else if (IS_CANNONLAKE(dev_priv))
cnl_gt_workarounds_apply(dev_priv);
+ else if (IS_ICELAKE(dev_priv))
+ icl_gt_workarounds_apply(dev_priv);
else
MISSING_CASE(INTEL_GEN(dev_priv));
}
@@ -761,6 +801,10 @@ static void cnl_whitelist_build(struct whitelist *w)
whitelist_reg(w, GEN8_CS_CHICKEN1);
}
+static void icl_whitelist_build(struct whitelist *w)
+{
+}
+
static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
struct whitelist *w)
{
@@ -789,6 +833,8 @@ static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
cfl_whitelist_build(w);
else if (IS_CANNONLAKE(i915))
cnl_whitelist_build(w);
+ else if (IS_ICELAKE(i915))
+ icl_whitelist_build(w);
else
MISSING_CASE(INTEL_GEN(i915));
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread
* Re: [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds
2018-05-08 21:29 ` [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
@ 2018-05-11 12:37 ` Mika Kuoppala
0 siblings, 0 replies; 42+ messages in thread
From: Mika Kuoppala @ 2018-05-11 12:37 UTC (permalink / raw)
To: Oscar Mateo, intel-gfx; +Cc: Rodrigo Vivi
Oscar Mateo <oscar.mateo@intel.com> writes:
> Inherit workarounds from previous platforms that are still valid for
> Icelake.
>
> v2: GEN7_ROW_CHICKEN2 is masked
> v3:
> - Since it has been fixed already in upstream, removed the TODO
> comment about WA_SET_BIT for WaInPlaceDecompressionHang.
> - Squashed with this patch:
> drm/i915/icl: add icelake_init_clock_gating()
> from Paulo Zanoni <paulo.r.zanoni@intel.com>
> - Squashed with this patch:
> drm/i915/icl: WaForceEnableNonCoherent
> from Oscar Mateo <oscar.mateo@intel.com>
> - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
> applies to B0 as well.
> - WaPipeControlBefore3DStateSamplePattern WABB was being applied
> to ICL incorrectly.
> v4:
> - Wrap the commit message
> - s/dev_priv/p to please checkpatch
> v5: Rebased on top of the WA refactoring
> v6: Rebased on top of further whitelist registers refactoring (Michel)
> v7: Added WaRsForcewakeAddDelayForAck
> v8: s/ICL_HDC_CHICKEN0/ICL_HDC_MODE (Mika)
> v9:
> - C, not lisp (Chris)
> - WaIncreaseDefaultTLBEntries is the same for GEN > 9_LP (Tvrtko)
>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Tomasz Lis <tomasz.lis@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 9 +++++++
> drivers/gpu/drm/i915/i915_gem_gtt.c | 6 ++---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_lrc.c | 2 ++
> drivers/gpu/drm/i915/intel_pm.c | 4 ++-
> drivers/gpu/drm/i915/intel_uncore.c | 7 +++--
> drivers/gpu/drm/i915/intel_workarounds.c | 46 ++++++++++++++++++++++++++++++++
> 7 files changed, 69 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 04e2780..ad79d5a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2469,6 +2469,15 @@ static inline unsigned int i915_sg_segment_size(void)
> #define IS_CNL_REVID(p, since, until) \
> (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
>
> +#define ICL_REVID_A0 0x0
> +#define ICL_REVID_A2 0x1
> +#define ICL_REVID_B0 0x3
> +#define ICL_REVID_B2 0x4
> +#define ICL_REVID_C0 0x5
> +
> +#define IS_ICL_REVID(p, since, until) \
> + (IS_ICELAKE(p) && IS_REVID(p, since, until))
> +
> /*
> * The genX designation typically refers to the render engine, so render
> * capability related checks should use IS_GEN, while display and other checks
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index c879bfd..ea30e84 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2137,15 +2137,15 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
> * called on driver load and after a GPU reset, so you can place
> * workarounds here even if they get overwritten by GPU reset.
> */
> - /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
> + /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
> if (IS_BROADWELL(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
> else if (IS_CHERRYVIEW(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
> - else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
> - I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
> else if (IS_GEN9_LP(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
> + else if (INTEL_GEN(dev_priv) >= 9)
> + I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
>
> /*
> * To support 64K PTEs we need to first enable the use of the
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 085928c..2b22d4d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7238,6 +7238,7 @@ enum {
> /* GEN8 chicken */
> #define HDC_CHICKEN0 _MMIO(0x7300)
> #define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
> +#define ICL_HDC_MODE _MMIO(0xE5F4)
> #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
> #define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
> #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 911f288..920752a 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1665,6 +1665,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
> return -EINVAL;
>
> switch (INTEL_GEN(engine->i915)) {
> + case 11:
> + return 0;
> case 10:
> wa_bb_fn[0] = gen10_init_indirectctx_bb;
> wa_bb_fn[1] = NULL;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 4126132..9c6e48c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -9190,7 +9190,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
> */
> void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
> {
> - if (IS_CANNONLAKE(dev_priv))
> + if (IS_ICELAKE(dev_priv))
> + dev_priv->display.init_clock_gating = nop_init_clock_gating;
> + else if (IS_CANNONLAKE(dev_priv))
> dev_priv->display.init_clock_gating = cnl_init_clock_gating;
> else if (IS_COFFEELAKE(dev_priv))
> dev_priv->display.init_clock_gating = cfl_init_clock_gating;
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index d6e20f0..448293e 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -139,7 +139,9 @@ enum ack_type {
> * in the hope that the original ack will be delivered along with
> * the fallback ack.
> *
> - * This workaround is described in HSDES #1604254524
> + * This workaround is described in HSDES #1604254524 and it's known as:
> + * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
> + * although the name is a bit misleading.
> */
>
> pass = 1;
> @@ -1394,7 +1396,8 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
> if (INTEL_GEN(dev_priv) >= 11) {
> int i;
>
> - dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
> + dev_priv->uncore.funcs.force_wake_get =
> + fw_domains_get_with_fallback;
> dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
> fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
> FORCEWAKE_RENDER_GEN9,
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index ec9d340..73d02d3 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -441,6 +441,27 @@ static int cnl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
> return 0;
> }
>
> +static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
> +{
> + /* Wa_1604370585:icl (pre-prod)
> + * Formerly known as WaPushConstantDereferenceHoldDisable
> + */
> + if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
> + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> + PUSH_CONSTANT_DEREF_DISABLE);
> +
> + /* WaForceEnableNonCoherent:icl
> + * This is not the same workaround as in early Gen9 platforms, where
> + * lacking this could cause system hangs, but coherency performance
> + * overhead is high and only a few compute workloads really need it
> + * (the register is whitelisted in hardware now, so UMDs can opt in
> + * for coherency if they have a good reason).
> + */
> + WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
> +
> + return 0;
> +}
> +
> int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
> {
> int err = 0;
> @@ -465,6 +486,8 @@ int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
> err = cfl_ctx_workarounds_init(dev_priv);
> else if (IS_CANNONLAKE(dev_priv))
> err = cnl_ctx_workarounds_init(dev_priv);
> + else if (IS_ICELAKE(dev_priv))
> + err = icl_ctx_workarounds_init(dev_priv);
> else
> MISSING_CASE(INTEL_GEN(dev_priv));
> if (err)
> @@ -663,6 +686,21 @@ static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
> }
>
> +static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> +{
> + /* This is not an Wa. Enable for better image quality */
> + I915_WRITE(_3D_CHICKEN3,
> + _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
> +
> + /* WaInPlaceDecompressionHang:icl */
> + I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
> + GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
> +
> + /* WaPipelineFlushCoherentLines:icl */
> + I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
> + GEN8_LQSC_FLUSH_COHERENT_LINES);
Ok, for icl, this is needed. And like you said, it is different
than what the WaFlushCoherentL3CacheLinesAtContextSwitch does.
There is more to this saga, as WaPipelineFlushCoherentLines
is needed also for other platforms, and we don't have it.
And it will collide with how we do per bb workarounds around this reg.
A thing we much recheck also on icl, if we add indirect context bb's.
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> +}
> +
> void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> {
> if (INTEL_GEN(dev_priv) < 8)
> @@ -683,6 +721,8 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> cfl_gt_workarounds_apply(dev_priv);
> else if (IS_CANNONLAKE(dev_priv))
> cnl_gt_workarounds_apply(dev_priv);
> + else if (IS_ICELAKE(dev_priv))
> + icl_gt_workarounds_apply(dev_priv);
> else
> MISSING_CASE(INTEL_GEN(dev_priv));
> }
> @@ -761,6 +801,10 @@ static void cnl_whitelist_build(struct whitelist *w)
> whitelist_reg(w, GEN8_CS_CHICKEN1);
> }
>
> +static void icl_whitelist_build(struct whitelist *w)
> +{
> +}
> +
> static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
> struct whitelist *w)
> {
> @@ -789,6 +833,8 @@ static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
> cfl_whitelist_build(w);
> else if (IS_CANNONLAKE(i915))
> cnl_whitelist_build(w);
> + else if (IS_ICELAKE(i915))
> + icl_whitelist_build(w);
> else
> MISSING_CASE(INTEL_GEN(i915));
>
> --
> 1.9.1
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^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 02/22] drm/i915/icl: Enable Sampler DFR
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
2018-05-08 21:29 ` [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
@ 2018-05-08 21:29 ` Oscar Mateo
2018-05-08 21:29 ` [PATCH 03/22] drm/i915/icl: WaGAPZPriorityScheme Oscar Mateo
` (24 subsequent siblings)
26 siblings, 0 replies; 42+ messages in thread
From: Oscar Mateo @ 2018-05-08 21:29 UTC (permalink / raw)
To: intel-gfx; +Cc: Praveen Paneri
Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
power by dynamically changing its clock frequency in low-throughput
conditions. This patches enables it by default on Gen11.
v2: Wrong operation to clear the bit (Praveen)
v3: Rebased on top of the WA refactoring
v4: Move to icl_init_clock_gating, since it's not a WA (Rodrigo)
v5: C, not lisp (Chris)
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Cc: Praveen Paneri <praveen.paneri@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 9 ++++++++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2b22d4d..6aad16e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8253,6 +8253,9 @@ enum {
#define GEN8_GARBCNTL _MMIO(0xB004)
#define GEN9_GAPS_TSV_CREDIT_DISABLE (1<<7)
+#define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
+#define DFR_DISABLE (1 << 9)
+
/* IVYBRIDGE DPF */
#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9c6e48c..b85229e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8664,6 +8664,13 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
I915_WRITE(GEN7_MISCCPCTL, misccpctl);
}
+static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+ /* This is not an Wa. Enable to reduce Sampler power */
+ I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
+ I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);
+}
+
static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
{
if (!HAS_PCH_CNP(dev_priv))
@@ -9191,7 +9198,7 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
if (IS_ICELAKE(dev_priv))
- dev_priv->display.init_clock_gating = nop_init_clock_gating;
+ dev_priv->display.init_clock_gating = icl_init_clock_gating;
else if (IS_CANNONLAKE(dev_priv))
dev_priv->display.init_clock_gating = cnl_init_clock_gating;
else if (IS_COFFEELAKE(dev_priv))
--
1.9.1
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^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 03/22] drm/i915/icl: WaGAPZPriorityScheme
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
2018-05-08 21:29 ` [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
2018-05-08 21:29 ` [PATCH 02/22] drm/i915/icl: Enable Sampler DFR Oscar Mateo
@ 2018-05-08 21:29 ` Oscar Mateo
2018-05-08 21:29 ` [PATCH 04/22] drm/i915/icl: WaL3BankAddressHashing Oscar Mateo
` (23 subsequent siblings)
26 siblings, 0 replies; 42+ messages in thread
From: Oscar Mateo @ 2018-05-08 21:29 UTC (permalink / raw)
To: intel-gfx
The default GAPZ arbitrer priority value at power-on has been found
to be incorrect.
v2: Now renamed to Wa_1405543622
v3: Rebased on top of the WA refactoring
v4: Added HSDES reference number (Mika)
v5:
- Rebased
- C, not lisp (Chris)
References: HSDES#1405543622
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6aad16e..c9c2ad5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8250,8 +8250,9 @@ enum {
#define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1<<4)
#define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1<<6)
-#define GEN8_GARBCNTL _MMIO(0xB004)
-#define GEN9_GAPS_TSV_CREDIT_DISABLE (1<<7)
+#define GEN8_GARBCNTL _MMIO(0xB004)
+#define GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
+#define GEN11_ARBITRATION_PRIO_ORDER_MASK (0x3f << 22)
#define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
#define DFR_DISABLE (1 << 9)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 73d02d3..44ae0b4 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -699,6 +699,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
/* WaPipelineFlushCoherentLines:icl */
I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_FLUSH_COHERENT_LINES);
+
+ /* Wa_1405543622:icl
+ * Formerly known as WaGAPZPriorityScheme
+ */
+ I915_WRITE(GEN8_GARBCNTL, I915_READ(GEN8_GARBCNTL) |
+ GEN11_ARBITRATION_PRIO_ORDER_MASK);
}
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
--
1.9.1
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^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 04/22] drm/i915/icl: WaL3BankAddressHashing
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
` (2 preceding siblings ...)
2018-05-08 21:29 ` [PATCH 03/22] drm/i915/icl: WaGAPZPriorityScheme Oscar Mateo
@ 2018-05-08 21:29 ` Oscar Mateo
2018-05-08 21:29 ` [PATCH 05/22] drm/i915/icl: WaModifyGamTlbPartitioning Oscar Mateo
` (22 subsequent siblings)
26 siblings, 0 replies; 42+ messages in thread
From: Oscar Mateo @ 2018-05-08 21:29 UTC (permalink / raw)
To: intel-gfx
Revert to an L3 non-hash model, for performance reasons.
v2:
- Place the WA name above the actual change
- Improve the register naming
v3:
- Rebased
- Renamed to Wa_1604223664
v4: Rebased on top of the WA refactoring
v5:
- Added References (Mika)
- Fixed wrong mask and value (Mika)
- Do not apply together with another WA for the same
register (not worth the hassle)
v6:
- Rebased
- C, not lisp (Chris)
References: HSDES#1604223664
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
drivers/gpu/drm/i915/intel_workarounds.c | 10 ++++++++++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c9c2ad5..81f1a8c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8253,6 +8253,12 @@ enum {
#define GEN8_GARBCNTL _MMIO(0xB004)
#define GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
#define GEN11_ARBITRATION_PRIO_ORDER_MASK (0x3f << 22)
+#define GEN11_HASH_CTRL_EXCL_MASK (0x7f << 0)
+#define GEN11_HASH_CTRL_EXCL_BIT0 (1 << 0)
+
+#define GEN11_GLBLINVL _MMIO(0xB404)
+#define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5)
+#define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5)
#define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
#define DFR_DISABLE (1 << 9)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 44ae0b4..3b03729 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -705,6 +705,16 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
*/
I915_WRITE(GEN8_GARBCNTL, I915_READ(GEN8_GARBCNTL) |
GEN11_ARBITRATION_PRIO_ORDER_MASK);
+
+ /* Wa_1604223664:icl
+ * Formerly known as WaL3BankAddressHashing
+ */
+ I915_WRITE(GEN8_GARBCNTL,
+ (I915_READ(GEN8_GARBCNTL) & ~GEN11_HASH_CTRL_EXCL_MASK) |
+ GEN11_HASH_CTRL_EXCL_BIT0);
+ I915_WRITE(GEN11_GLBLINVL,
+ (I915_READ(GEN11_GLBLINVL) & ~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
+ GEN11_BANK_HASH_ADDR_EXCL_BIT0);
}
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
--
1.9.1
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^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 05/22] drm/i915/icl: WaModifyGamTlbPartitioning
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
` (3 preceding siblings ...)
2018-05-08 21:29 ` [PATCH 04/22] drm/i915/icl: WaL3BankAddressHashing Oscar Mateo
@ 2018-05-08 21:29 ` Oscar Mateo
2018-05-08 21:29 ` [PATCH 06/22] drm/i915/icl: WaDisableCleanEvicts Oscar Mateo
` (21 subsequent siblings)
26 siblings, 0 replies; 42+ messages in thread
From: Oscar Mateo @ 2018-05-08 21:29 UTC (permalink / raw)
To: intel-gfx
Adjust default GAM TLB partitioning for performance reasons.
v2: Only touch the bits that we really need
v3: Rebased on top of the WA refactoring
v4:
- Added References (Mika)
- Rebased
v5:
- Rebased
- C, not lisp (Chris)
- Correct reference number (Mika)
References: HSDES#220160670
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++++
drivers/gpu/drm/i915/intel_workarounds.c | 5 +++++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 81f1a8c..7fe505c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8263,6 +8263,11 @@ enum {
#define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
#define DFR_DISABLE (1 << 9)
+#define GEN11_GACB_PERF_CTRL _MMIO(0x4B80)
+#define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
+#define GEN11_HASH_CTRL_BIT0 (1 << 0)
+#define GEN11_HASH_CTRL_BIT4 (1 << 12)
+
/* IVYBRIDGE DPF */
#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 3b03729..2561c55 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -715,6 +715,11 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
I915_WRITE(GEN11_GLBLINVL,
(I915_READ(GEN11_GLBLINVL) & ~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
GEN11_BANK_HASH_ADDR_EXCL_BIT0);
+
+ /* WaModifyGamTlbPartitioning:icl */
+ I915_WRITE(GEN11_GACB_PERF_CTRL,
+ (I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
+ GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4);
}
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
--
1.9.1
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^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 06/22] drm/i915/icl: WaDisableCleanEvicts
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
` (4 preceding siblings ...)
2018-05-08 21:29 ` [PATCH 05/22] drm/i915/icl: WaModifyGamTlbPartitioning Oscar Mateo
@ 2018-05-08 21:29 ` Oscar Mateo
2018-05-08 21:29 ` [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc Oscar Mateo
` (20 subsequent siblings)
26 siblings, 0 replies; 42+ messages in thread
From: Oscar Mateo @ 2018-05-08 21:29 UTC (permalink / raw)
To: intel-gfx
Avoids an undefined LLC behavior.
BSpec: 9613
v2: Renamed to Wa_1405733216
v3: Spaces around '<<' and fix surrounding code
v4: Rebased on top of the WA refactoring
v5: Added References (Mika)
v6:
- Rebased
- C, not lisp (Chris)
References: HSDES#1405733216
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7fe505c..a7bd739 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7232,8 +7232,9 @@ enum {
#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
#define GEN8_L3SQCREG4 _MMIO(0xb118)
-#define GEN8_LQSC_RO_PERF_DIS (1<<27)
-#define GEN8_LQSC_FLUSH_COHERENT_LINES (1<<21)
+#define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6)
+#define GEN8_LQSC_RO_PERF_DIS (1 << 27)
+#define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21)
/* GEN8 chicken */
#define HDC_CHICKEN0 _MMIO(0x7300)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 2561c55..7e8bcc2 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -720,6 +720,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
I915_WRITE(GEN11_GACB_PERF_CTRL,
(I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4);
+
+ /* Wa_1405733216:icl
+ * Formerly known as WaDisableCleanEvicts
+ */
+ I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
+ GEN11_LQSC_CLEAN_EVICT_DISABLE);
}
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
--
1.9.1
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^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
` (5 preceding siblings ...)
2018-05-08 21:29 ` [PATCH 06/22] drm/i915/icl: WaDisableCleanEvicts Oscar Mateo
@ 2018-05-08 21:29 ` Oscar Mateo
2018-05-08 21:29 ` [PATCH 08/22] drm/i915/icl: WaDisCtxReload Oscar Mateo
` (19 subsequent siblings)
26 siblings, 0 replies; 42+ messages in thread
From: Oscar Mateo @ 2018-05-08 21:29 UTC (permalink / raw)
To: intel-gfx
This workarounds an issue with insufficient storage for the
CL2 and SF units.
v2: Renamed to Wa_1405766107
v3: Wrapped the commit message
v4: Rebased on top of the WA refactoring
v5: Added References (Mika)
v6:
- Rebased
- s/MACALLOC/MAXALLOC (Mika)
- C, not lisp (Chris)
References: HSDES#1405766107
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
drivers/gpu/drm/i915/intel_workarounds.c | 7 +++++++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a7bd739..d325fad 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8269,6 +8269,10 @@ enum {
#define GEN11_HASH_CTRL_BIT0 (1 << 0)
#define GEN11_HASH_CTRL_BIT4 (1 << 12)
+#define GEN11_LSN_UNSLCVC _MMIO(0xB43C)
+#define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9)
+#define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7)
+
/* IVYBRIDGE DPF */
#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 7e8bcc2..a6758bd 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -726,6 +726,13 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
*/
I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
GEN11_LQSC_CLEAN_EVICT_DISABLE);
+
+ /* Wa_1405766107:icl
+ * Formerly known as WaCL2SFHalfMaxAlloc
+ */
+ I915_WRITE(GEN11_LSN_UNSLCVC, I915_READ(GEN11_LSN_UNSLCVC) |
+ GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
+ GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC);
}
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
--
1.9.1
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^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 08/22] drm/i915/icl: WaDisCtxReload
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
` (6 preceding siblings ...)
2018-05-08 21:29 ` [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc Oscar Mateo
@ 2018-05-08 21:29 ` Oscar Mateo
2018-05-08 21:29 ` [PATCH 09/22] drm/i915/icl: Wa_1405779004 Oscar Mateo
` (18 subsequent siblings)
26 siblings, 0 replies; 42+ messages in thread
From: Oscar Mateo @ 2018-05-08 21:29 UTC (permalink / raw)
To: intel-gfx
Revert to the legacy implementation to avoid a system hang.
v2: Correct the address for GAMW_ECO_DEV_RW_IA_REG
v3: Renamed to Wa_220166154
v4: Rebased on top of the WA refactoring
v5: Added References (Mika)
v6:
- Rebased
- C, not lisp (Chris)
References: HSDES#220166154
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d325fad..dd23af3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8273,6 +8273,9 @@ enum {
#define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9)
#define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7)
+#define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080)
+#define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
+
/* IVYBRIDGE DPF */
#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index a6758bd..3547403 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -733,6 +733,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
I915_WRITE(GEN11_LSN_UNSLCVC, I915_READ(GEN11_LSN_UNSLCVC) |
GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC);
+
+ /* Wa_220166154:icl
+ * Formerly known as WaDisCtxReload
+ */
+ I915_WRITE(GAMW_ECO_DEV_RW_IA_REG, I915_READ(GAMW_ECO_DEV_RW_IA_REG) |
+ GAMW_ECO_DEV_CTX_RELOAD_DISABLE);
}
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
--
1.9.1
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^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 09/22] drm/i915/icl: Wa_1405779004
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
` (7 preceding siblings ...)
2018-05-08 21:29 ` [PATCH 08/22] drm/i915/icl: WaDisCtxReload Oscar Mateo
@ 2018-05-08 21:29 ` Oscar Mateo
2018-05-08 21:29 ` [PATCH 10/22] drm/i915/icl: Wa_1406680159 Oscar Mateo
` (17 subsequent siblings)
26 siblings, 0 replies; 42+ messages in thread
From: Oscar Mateo @ 2018-05-08 21:29 UTC (permalink / raw)
To: intel-gfx
Disable MSC clock gating to prevent data corruption.
BSpec: 19257
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
v4:
- Rebased
- C, not lisp (Chris)
- A0 only (Mika)
References: HSDES#1405779004
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dd23af3..950ec8e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3840,6 +3840,7 @@ enum {
#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
#define SARBUNIT_CLKGATE_DIS (1 << 5)
#define RCCUNIT_CLKGATE_DIS (1 << 7)
+#define MSCUNIT_CLKGATE_DIS (1 << 10)
#define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
#define GWUNIT_CLKGATE_DIS (1 << 16)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 3547403..469a83d 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -739,6 +739,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
*/
I915_WRITE(GAMW_ECO_DEV_RW_IA_REG, I915_READ(GAMW_ECO_DEV_RW_IA_REG) |
GAMW_ECO_DEV_CTX_RELOAD_DISABLE);
+
+ /* Wa_1405779004:icl (pre-prod) */
+ if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_A0))
+ I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
+ I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
+ MSCUNIT_CLKGATE_DIS);
}
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
--
1.9.1
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^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 10/22] drm/i915/icl: Wa_1406680159
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
` (8 preceding siblings ...)
2018-05-08 21:29 ` [PATCH 09/22] drm/i915/icl: Wa_1405779004 Oscar Mateo
@ 2018-05-08 21:29 ` Oscar Mateo
2018-05-08 21:29 ` [PATCH 11/22] drm/i915/icl: Wa_1604302699 Oscar Mateo
` (16 subsequent siblings)
26 siblings, 0 replies; 42+ messages in thread
From: Oscar Mateo @ 2018-05-08 21:29 UTC (permalink / raw)
To: intel-gfx
Disable GWL clock gating to prevent an issue that might
cause hangs.
v2: Rebased on top of the WA refactoring
v3: Wa_2201832410 officially merged with Wa_1406680159
v4: Added References (Mika)
v5:
- Rebased
- C, not lisp (Chris)
- Add reference where WA is better explained (Rodrigo)
- Add reference to WA that got merged with this
References: HSDES#1406681710
References: HSDES#1406680159
References: HSDES#2201832410
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_workarounds.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 469a83d..a3fa01a 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -745,6 +745,11 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
MSCUNIT_CLKGATE_DIS);
+
+ /* Wa_1406680159:icl */
+ I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
+ I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
+ GWUNIT_CLKGATE_DIS);
}
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
--
1.9.1
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^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 11/22] drm/i915/icl: Wa_1604302699
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
` (9 preceding siblings ...)
2018-05-08 21:29 ` [PATCH 10/22] drm/i915/icl: Wa_1406680159 Oscar Mateo
@ 2018-05-08 21:29 ` Oscar Mateo
2018-05-08 21:29 ` [PATCH 12/22] drm/i915/icl: Wa_1406838659 Oscar Mateo
` (15 subsequent siblings)
26 siblings, 0 replies; 42+ messages in thread
From: Oscar Mateo @ 2018-05-08 21:29 UTC (permalink / raw)
To: intel-gfx
Disable I2M Write for performance reasons.
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
v4:
- Rebased
- C, not lisp (Chris)
- GEN7 chicken bit in the wrong side of the fence (Mika)
- Use two spaces to align bit macros
References: HSDES#1604302699
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
drivers/gpu/drm/i915/intel_workarounds.c | 5 +++++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 950ec8e..7cb2ddc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7227,7 +7227,9 @@ enum {
#define GEN7_L3CNTLREG3 _MMIO(0xB024)
#define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030)
-#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
+#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
+#define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xB114)
+#define GEN11_I2M_WRITE_DISABLE (1 << 28)
#define GEN7_L3SQCREG4 _MMIO(0xb034)
#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index a3fa01a..2a4e3ee 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -750,6 +750,11 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
GWUNIT_CLKGATE_DIS);
+
+ /* Wa_1604302699:icl */
+ I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER,
+ I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) |
+ GEN11_I2M_WRITE_DISABLE);
}
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
--
1.9.1
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^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 12/22] drm/i915/icl: Wa_1406838659
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
` (10 preceding siblings ...)
2018-05-08 21:29 ` [PATCH 11/22] drm/i915/icl: Wa_1604302699 Oscar Mateo
@ 2018-05-08 21:29 ` Oscar Mateo
2018-05-08 21:29 ` [PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset Oscar Mateo
` (14 subsequent siblings)
26 siblings, 0 replies; 42+ messages in thread
From: Oscar Mateo @ 2018-05-08 21:29 UTC (permalink / raw)
To: intel-gfx
Disable CGPSF unit clock gating to prevent an issue.
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
v4:
- Rebased
- C, not lisp (Chris)
- Remove unintentional whitespaces (Mika)
- Fixed in C0 (Mika)
References: HSDES#1406838659
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7cb2ddc..ce48427 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3848,6 +3848,9 @@ enum {
#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
#define VFUNIT_CLKGATE_DIS (1 << 20)
+#define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)
+#define CGPSF_CLKGATE_DIS (1 << 3)
+
/*
* Display engine regs
*/
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 2a4e3ee..942d322 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -755,6 +755,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER,
I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) |
GEN11_I2M_WRITE_DISABLE);
+
+ /* Wa_1406838659:icl (pre-prod) */
+ if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+ I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
+ I915_READ(INF_UNIT_LEVEL_CLKGATE) |
+ CGPSF_CLKGATE_DIS);
}
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
--
1.9.1
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^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
` (11 preceding siblings ...)
2018-05-08 21:29 ` [PATCH 12/22] drm/i915/icl: Wa_1406838659 Oscar Mateo
@ 2018-05-08 21:29 ` Oscar Mateo
2018-05-09 11:18 ` Mika Kuoppala
2018-05-08 21:29 ` [PATCH 14/22] drm/i915/icl: WaDisableImprovedTdlClkGating Oscar Mateo
` (13 subsequent siblings)
26 siblings, 1 reply; 42+ messages in thread
From: Oscar Mateo @ 2018-05-08 21:29 UTC (permalink / raw)
To: intel-gfx
Avoids a hang during soft reset.
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
v4:
- Rebased
- C, not lisp (Chris)
- Which steppings affected by this are not clear.
For the moment, apply unconditionally as per the
BSpec (Mika)
- Add reference to another HSD also related
References: HSDES#1405476379
References: HSDES#2006612137
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++++
drivers/gpu/drm/i915/intel_workarounds.c | 7 +++++++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ce48427..1449178 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9897,6 +9897,11 @@ enum skl_power_gate {
/* Media decoder 2 MOCS registers */
#define GEN11_MFX2_MOCS(i) _MMIO(0x10000 + (i) * 4)
+#define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0)
+#define PMFLUSHDONE_LNICRSDROP (1 << 20)
+#define PMFLUSH_GAPL3UNBLOCK (1 << 21)
+#define PMFLUSHDONE_LNEBLK (1 << 22)
+
/* gamt regs */
#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 942d322..5eec4ce 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -761,6 +761,13 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
I915_READ(INF_UNIT_LEVEL_CLKGATE) |
CGPSF_CLKGATE_DIS);
+
+ /* WaForwardProgressSoftReset:icl */
+ I915_WRITE(GEN10_SCRATCH_LNCF2,
+ I915_READ(GEN10_SCRATCH_LNCF2) |
+ PMFLUSHDONE_LNICRSDROP |
+ PMFLUSH_GAPL3UNBLOCK |
+ PMFLUSHDONE_LNEBLK);
}
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
--
1.9.1
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^ permalink raw reply related [flat|nested] 42+ messages in thread
* Re: [PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset
2018-05-08 21:29 ` [PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset Oscar Mateo
@ 2018-05-09 11:18 ` Mika Kuoppala
0 siblings, 0 replies; 42+ messages in thread
From: Mika Kuoppala @ 2018-05-09 11:18 UTC (permalink / raw)
To: Oscar Mateo, intel-gfx
Oscar Mateo <oscar.mateo@intel.com> writes:
> Avoids a hang during soft reset.
>
> v2: Rebased on top of the WA refactoring
> v3: Added References (Mika)
> v4:
> - Rebased
> - C, not lisp (Chris)
> - Which steppings affected by this are not clear.
> For the moment, apply unconditionally as per the
> BSpec (Mika)
> - Add reference to another HSD also related
>
> References: HSDES#1405476379
> References: HSDES#2006612137
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 +++++
> drivers/gpu/drm/i915/intel_workarounds.c | 7 +++++++
> 2 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ce48427..1449178 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9897,6 +9897,11 @@ enum skl_power_gate {
> /* Media decoder 2 MOCS registers */
> #define GEN11_MFX2_MOCS(i) _MMIO(0x10000 + (i) * 4)
>
> +#define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0)
> +#define PMFLUSHDONE_LNICRSDROP (1 << 20)
> +#define PMFLUSH_GAPL3UNBLOCK (1 << 21)
> +#define PMFLUSHDONE_LNEBLK (1 << 22)
> +
> /* gamt regs */
> #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
> #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 942d322..5eec4ce 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -761,6 +761,13 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
> I915_READ(INF_UNIT_LEVEL_CLKGATE) |
> CGPSF_CLKGATE_DIS);
> +
> + /* WaForwardProgressSoftReset:icl */
> + I915_WRITE(GEN10_SCRATCH_LNCF2,
> + I915_READ(GEN10_SCRATCH_LNCF2) |
> + PMFLUSHDONE_LNICRSDROP |
> + PMFLUSH_GAPL3UNBLOCK |
> + PMFLUSHDONE_LNEBLK);
> }
>
> void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> --
> 1.9.1
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^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 14/22] drm/i915/icl: WaDisableImprovedTdlClkGating
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
` (12 preceding siblings ...)
2018-05-08 21:29 ` [PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset Oscar Mateo
@ 2018-05-08 21:29 ` Oscar Mateo
2018-05-16 11:05 ` Mika Kuoppala
2018-05-08 21:29 ` [PATCH 15/22] drm/i915/icl: WaEnableStateCacheRedirectToCS Oscar Mateo
` (12 subsequent siblings)
26 siblings, 1 reply; 42+ messages in thread
From: Oscar Mateo @ 2018-05-08 21:29 UTC (permalink / raw)
To: intel-gfx
Revert to the legacy implementation.
v2: GEN7_ROW_CHICKEN2 is masked
v3:
- Rebased
- Renamed to Wa_2006611047
- A0 and B0 only
v4:
- Add spaces around '<<' (and fix the surrounding code as well)
- Mark the WA as pre-prod
v5: Rebased on top of the WA refactoring
v6: Added References (Mika)
v7: Fixed in B0
References: HSDES#2006611047
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
drivers/gpu/drm/i915/intel_workarounds.c | 7 +++++++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1449178..7f6f328 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8319,8 +8319,9 @@ enum {
#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
-#define DOP_CLOCK_GATING_DISABLE (1<<0)
-#define PUSH_CONSTANT_DEREF_DISABLE (1<<8)
+#define DOP_CLOCK_GATING_DISABLE (1 << 0)
+#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
+#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 5eec4ce..3913b6a 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -459,6 +459,13 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
*/
WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
+ /* Wa_2006611047:icl (pre-prod)
+ * Formerly known as WaDisableImprovedTdlClkGating
+ */
+ if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_A0))
+ WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+ GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
+
return 0;
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 42+ messages in thread
* Re: [PATCH 14/22] drm/i915/icl: WaDisableImprovedTdlClkGating
2018-05-08 21:29 ` [PATCH 14/22] drm/i915/icl: WaDisableImprovedTdlClkGating Oscar Mateo
@ 2018-05-16 11:05 ` Mika Kuoppala
2018-05-16 19:41 ` Oscar Mateo
0 siblings, 1 reply; 42+ messages in thread
From: Mika Kuoppala @ 2018-05-16 11:05 UTC (permalink / raw)
To: Oscar Mateo, intel-gfx
Oscar Mateo <oscar.mateo@intel.com> writes:
> Revert to the legacy implementation.
>
> v2: GEN7_ROW_CHICKEN2 is masked
> v3:
> - Rebased
> - Renamed to Wa_2006611047
> - A0 and B0 only
> v4:
> - Add spaces around '<<' (and fix the surrounding code as well)
> - Mark the WA as pre-prod
> v5: Rebased on top of the WA refactoring
> v6: Added References (Mika)
> v7: Fixed in B0
Could you recheck from bspec?
I read it like we need this for all
-Mika
>
> References: HSDES#2006611047
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 +++--
> drivers/gpu/drm/i915/intel_workarounds.c | 7 +++++++
> 2 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1449178..7f6f328 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8319,8 +8319,9 @@ enum {
>
> #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
> #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
> -#define DOP_CLOCK_GATING_DISABLE (1<<0)
> -#define PUSH_CONSTANT_DEREF_DISABLE (1<<8)
> +#define DOP_CLOCK_GATING_DISABLE (1 << 0)
> +#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
> +#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
>
> #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
> #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 5eec4ce..3913b6a 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -459,6 +459,13 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
> */
> WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
>
> + /* Wa_2006611047:icl (pre-prod)
> + * Formerly known as WaDisableImprovedTdlClkGating
> + */
> + if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_A0))
> + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> + GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
> +
> return 0;
> }
>
> --
> 1.9.1
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^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 14/22] drm/i915/icl: WaDisableImprovedTdlClkGating
2018-05-16 11:05 ` Mika Kuoppala
@ 2018-05-16 19:41 ` Oscar Mateo
0 siblings, 0 replies; 42+ messages in thread
From: Oscar Mateo @ 2018-05-16 19:41 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
On 05/16/2018 04:05 AM, Mika Kuoppala wrote:
> Oscar Mateo <oscar.mateo@intel.com> writes:
>
>> Revert to the legacy implementation.
>>
>> v2: GEN7_ROW_CHICKEN2 is masked
>> v3:
>> - Rebased
>> - Renamed to Wa_2006611047
>> - A0 and B0 only
>> v4:
>> - Add spaces around '<<' (and fix the surrounding code as well)
>> - Mark the WA as pre-prod
>> v5: Rebased on top of the WA refactoring
>> v6: Added References (Mika)
>> v7: Fixed in B0
> Could you recheck from bspec?
> I read it like we need this for all
I was going by the HSD (#2006611047), which says this was fixed in B0...
> -Mika
>
>> References: HSDES#2006611047
>> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 5 +++--
>> drivers/gpu/drm/i915/intel_workarounds.c | 7 +++++++
>> 2 files changed, 10 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 1449178..7f6f328 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -8319,8 +8319,9 @@ enum {
>>
>> #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
>> #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
>> -#define DOP_CLOCK_GATING_DISABLE (1<<0)
>> -#define PUSH_CONSTANT_DEREF_DISABLE (1<<8)
>> +#define DOP_CLOCK_GATING_DISABLE (1 << 0)
>> +#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
>> +#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
>>
>> #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
>> #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
>> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
>> index 5eec4ce..3913b6a 100644
>> --- a/drivers/gpu/drm/i915/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
>> @@ -459,6 +459,13 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
>> */
>> WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
>>
>> + /* Wa_2006611047:icl (pre-prod)
>> + * Formerly known as WaDisableImprovedTdlClkGating
>> + */
>> + if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_A0))
>> + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
>> + GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
>> +
>> return 0;
>> }
>>
>> --
>> 1.9.1
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^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 15/22] drm/i915/icl: WaEnableStateCacheRedirectToCS
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
` (13 preceding siblings ...)
2018-05-08 21:29 ` [PATCH 14/22] drm/i915/icl: WaDisableImprovedTdlClkGating Oscar Mateo
@ 2018-05-08 21:29 ` Oscar Mateo
2018-05-08 21:29 ` [PATCH 16/22] drm/i915/icl: Wa_2006665173 Oscar Mateo
` (11 subsequent siblings)
26 siblings, 0 replies; 42+ messages in thread
From: Oscar Mateo @ 2018-05-08 21:29 UTC (permalink / raw)
To: intel-gfx
Redirects the state cache to the CS Command buffer section for
performance reasons.
v2: Rebased
v3: Rebased on top of the WA refactoring
v3: Added References (Mika)
References: HSDES#1604325460
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7f6f328..e1fe6ba 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7208,6 +7208,7 @@ enum {
#define DISABLE_PIXEL_MASK_CAMMING (1<<14)
#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
+#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
#define GEN7_L3SQCREG1 _MMIO(0xB010)
#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 3913b6a..162d219 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -466,6 +466,10 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
+ /* WaEnableStateCacheRedirectToCS:icl */
+ WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1,
+ GEN11_STATE_CACHE_REDIRECT_TO_CS);
+
return 0;
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 16/22] drm/i915/icl: Wa_2006665173
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
` (14 preceding siblings ...)
2018-05-08 21:29 ` [PATCH 15/22] drm/i915/icl: WaEnableStateCacheRedirectToCS Oscar Mateo
@ 2018-05-08 21:29 ` Oscar Mateo
2018-05-08 21:29 ` [PATCH 17/22] drm/i915/icl: WaEnableFloatBlendOptimization Oscar Mateo
` (10 subsequent siblings)
26 siblings, 0 replies; 42+ messages in thread
From: Oscar Mateo @ 2018-05-08 21:29 UTC (permalink / raw)
To: intel-gfx
Disable blend embellishment in RCC.
Also, some other registers style fixed in passing.
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
v4:
- Fixed in B0
- Mentioned style fixes in commit message
References: HSDES#2006665173
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 18 +++++++++++-------
drivers/gpu/drm/i915/intel_workarounds.c | 5 +++++
2 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e1fe6ba..e4c3461 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7192,13 +7192,17 @@ enum {
/* GEN7 chicken */
#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
-# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
-# define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
-#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
-# define GEN9_PBE_COMPRESSED_HASH_SELECTION (1<<13)
-# define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1<<12)
-# define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)
-# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
+ #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1 << 10) | (1 << 26))
+ #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14)
+
+#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
+ #define GEN9_PBE_COMPRESSED_HASH_SELECTION (1 << 13)
+ #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1 << 12)
+ #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8)
+ #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0)
+
+#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
+ #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11)
#define HIZ_CHICKEN _MMIO(0x7018)
# define CHV_HZ_8X8_MODE_IN_1X (1<<15)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 162d219..c392c33 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -470,6 +470,11 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1,
GEN11_STATE_CACHE_REDIRECT_TO_CS);
+ /* Wa_2006665173:icl (pre-prod) */
+ if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_A0))
+ WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
+ GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
+
return 0;
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 17/22] drm/i915/icl: WaEnableFloatBlendOptimization
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
` (15 preceding siblings ...)
2018-05-08 21:29 ` [PATCH 16/22] drm/i915/icl: Wa_2006665173 Oscar Mateo
@ 2018-05-08 21:29 ` Oscar Mateo
2018-05-08 21:29 ` [PATCH 18/22] drm/i915/icl: WaSendPushConstantsFromMMIO Oscar Mateo
` (9 subsequent siblings)
26 siblings, 0 replies; 42+ messages in thread
From: Oscar Mateo @ 2018-05-08 21:29 UTC (permalink / raw)
To: intel-gfx
Enables blend optimization for floating point RTs
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
References: HSDES#1406393558
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e4c3461..e8005bd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2663,6 +2663,9 @@ enum i915_power_well_id {
#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1)
+#define GEN10_CACHE_MODE_SS _MMIO(0xe420)
+#define FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
+
#define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
#define GEN6_BLITTER_LOCK_SHIFT 16
#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index c392c33..bf7c972 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -475,6 +475,9 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
+ /* WaEnableFloatBlendOptimization:icl */
+ WA_SET_BIT_MASKED(GEN10_CACHE_MODE_SS, FLOAT_BLEND_OPTIMIZATION_ENABLE);
+
return 0;
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 18/22] drm/i915/icl: WaSendPushConstantsFromMMIO
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
` (16 preceding siblings ...)
2018-05-08 21:29 ` [PATCH 17/22] drm/i915/icl: WaEnableFloatBlendOptimization Oscar Mateo
@ 2018-05-08 21:29 ` Oscar Mateo
2018-05-08 21:29 ` [PATCH 19/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2 Oscar Mateo
` (8 subsequent siblings)
26 siblings, 0 replies; 42+ messages in thread
From: Oscar Mateo @ 2018-05-08 21:29 UTC (permalink / raw)
To: intel-gfx
Allows UMDs to set 'Disable Gather at Set Shader Common Slice'.
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it...
v2: Rebased
v3: Rebased on top of the WA refactoring
v4: Rebased on top of the WA whitelist reg refactoring (Michel)
v5: Added References (Mika)
References: HSDES#1405764967
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/intel_workarounds.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index bf7c972..12ab0ca 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -891,6 +891,8 @@ static void cnl_whitelist_build(struct whitelist *w)
static void icl_whitelist_build(struct whitelist *w)
{
+ /* WaSendPushConstantsFromMMIO:icl */
+ whitelist_reg(w, COMMON_SLICE_CHICKEN2);
}
static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
--
1.9.1
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^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 19/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
` (17 preceding siblings ...)
2018-05-08 21:29 ` [PATCH 18/22] drm/i915/icl: WaSendPushConstantsFromMMIO Oscar Mateo
@ 2018-05-08 21:29 ` Oscar Mateo
2018-05-08 21:29 ` [PATCH 20/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7 Oscar Mateo
` (7 subsequent siblings)
26 siblings, 0 replies; 42+ messages in thread
From: Oscar Mateo @ 2018-05-08 21:29 UTC (permalink / raw)
To: intel-gfx
Required to dinamically set 'Small PL Lossless Fix Enable'
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA refactoring
v4: Rebased on top of whitelist reg refactoring (Michel)
v5: Added References (Mika)
References: HSDES#1804860039
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 12ab0ca..7782b36 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -893,6 +893,9 @@ static void icl_whitelist_build(struct whitelist *w)
{
/* WaSendPushConstantsFromMMIO:icl */
whitelist_reg(w, COMMON_SLICE_CHICKEN2);
+
+ /* WaAllowUMDToModifyHalfSliceChicken2:icl */
+ whitelist_reg(w, HALF_SLICE_CHICKEN2);
}
static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
--
1.9.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 20/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
` (18 preceding siblings ...)
2018-05-08 21:29 ` [PATCH 19/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2 Oscar Mateo
@ 2018-05-08 21:29 ` Oscar Mateo
2018-05-08 21:29 ` [PATCH 21/22] drm/i915/icl: WaAllowUmdWriteTRTTRootTable Oscar Mateo
` (6 subsequent siblings)
26 siblings, 0 replies; 42+ messages in thread
From: Oscar Mateo @ 2018-05-08 21:29 UTC (permalink / raw)
To: intel-gfx
Required to dinamically set 'Trilinear Filter Quality Mode'
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA refactoring
v4: Rebased on top of the whitelist reg refactoring (Michel)
v5: Added References (Mika)
References: HSDES#1804860157
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 7782b36..a6a3410 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -896,6 +896,9 @@ static void icl_whitelist_build(struct whitelist *w)
/* WaAllowUMDToModifyHalfSliceChicken2:icl */
whitelist_reg(w, HALF_SLICE_CHICKEN2);
+
+ /* WaAllowUMDToModifyHalfSliceChicken7:icl */
+ whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
}
static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 21/22] drm/i915/icl: WaAllowUmdWriteTRTTRootTable
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
` (19 preceding siblings ...)
2018-05-08 21:29 ` [PATCH 20/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7 Oscar Mateo
@ 2018-05-08 21:29 ` Oscar Mateo
2018-05-08 21:29 ` [PATCH 22/22] drm/i915/icl: WaAllowUMDToModifySamplerMode Oscar Mateo
` (5 subsequent siblings)
26 siblings, 0 replies; 42+ messages in thread
From: Oscar Mateo @ 2018-05-08 21:29 UTC (permalink / raw)
To: intel-gfx
Required for TR-TT (Tiled Resource Translation Table) support.
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA refactoring
v4: Rebased on top of whitelist reg refactoring (Michel)
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e8005bd..e41076f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8290,6 +8290,9 @@ enum {
#define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080)
#define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
+#define TR_VA_TTL3_PTR_DW0 _MMIO(0x4DE0)
+#define TR_VA_TTL3_PTR_DW1 _MMIO(0x4DE4)
+
/* IVYBRIDGE DPF */
#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index a6a3410..571b87a 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -899,6 +899,10 @@ static void icl_whitelist_build(struct whitelist *w)
/* WaAllowUMDToModifyHalfSliceChicken7:icl */
whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
+
+ /* WaAllowUmdWriteTRTTRootTable:icl */
+ whitelist_reg(w, TR_VA_TTL3_PTR_DW0);
+ whitelist_reg(w, TR_VA_TTL3_PTR_DW1);
}
static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 22/22] drm/i915/icl: WaAllowUMDToModifySamplerMode
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
` (20 preceding siblings ...)
2018-05-08 21:29 ` [PATCH 21/22] drm/i915/icl: WaAllowUmdWriteTRTTRootTable Oscar Mateo
@ 2018-05-08 21:29 ` Oscar Mateo
2018-05-08 22:28 ` ✗ Fi.CI.CHECKPATCH: warning for Workarounds for Icelake (rev3) Patchwork
` (4 subsequent siblings)
26 siblings, 0 replies; 42+ messages in thread
From: Oscar Mateo @ 2018-05-08 21:29 UTC (permalink / raw)
To: intel-gfx
Required for Bindless samplers.
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
v2: Rebased on top of the WA refactoring (Michel)
v3: Added References (Mika)
References: HSDES#1404695891
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e41076f..c3e464c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8293,6 +8293,8 @@ enum {
#define TR_VA_TTL3_PTR_DW0 _MMIO(0x4DE0)
#define TR_VA_TTL3_PTR_DW1 _MMIO(0x4DE4)
+#define GEN10_SAMPLER_MODE _MMIO(0xE18C)
+
/* IVYBRIDGE DPF */
#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 571b87a..f76ab3c 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -903,6 +903,9 @@ static void icl_whitelist_build(struct whitelist *w)
/* WaAllowUmdWriteTRTTRootTable:icl */
whitelist_reg(w, TR_VA_TTL3_PTR_DW0);
whitelist_reg(w, TR_VA_TTL3_PTR_DW1);
+
+ /* WaAllowUMDToModifySamplerMode:icl */
+ whitelist_reg(w, GEN10_SAMPLER_MODE);
}
static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Workarounds for Icelake (rev3)
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
` (21 preceding siblings ...)
2018-05-08 21:29 ` [PATCH 22/22] drm/i915/icl: WaAllowUMDToModifySamplerMode Oscar Mateo
@ 2018-05-08 22:28 ` Patchwork
2018-05-08 22:35 ` ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
26 siblings, 0 replies; 42+ messages in thread
From: Patchwork @ 2018-05-08 22:28 UTC (permalink / raw)
To: Oscar Mateo; +Cc: intel-gfx
== Series Details ==
Series: Workarounds for Icelake (rev3)
URL : https://patchwork.freedesktop.org/series/42055/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e15ebaa57f79 drm/i915/icl: Introduce initial Icelake Workarounds
-:54: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#54: FILE: drivers/gpu/drm/i915/i915_drv.h:2478:
+#define IS_ICL_REVID(p, since, until) \
+ (IS_ICELAKE(p) && IS_REVID(p, since, until))
total: 0 errors, 0 warnings, 1 checks, 159 lines checked
81af04257725 drm/i915/icl: Enable Sampler DFR
d056c0a6184d drm/i915/icl: WaGAPZPriorityScheme
16668cca3d31 drm/i915/icl: WaL3BankAddressHashing
71b492177fb8 drm/i915/icl: WaModifyGamTlbPartitioning
95098d8144e7 drm/i915/icl: WaDisableCleanEvicts
4eabc0165b9f drm/i915/icl: WaCL2SFHalfMaxAlloc
228bb60a8743 drm/i915/icl: WaDisCtxReload
5a05a81044c2 drm/i915/icl: Wa_1405779004
77e246e55a00 drm/i915/icl: Wa_1406680159
5bfd01f40304 drm/i915/icl: Wa_1604302699
f2b42238328a drm/i915/icl: Wa_1406838659
08a43ed718f1 drm/i915/icl: WaForwardProgressSoftReset
b3a93f743a5f drm/i915/icl: WaDisableImprovedTdlClkGating
fc59701816c2 drm/i915/icl: WaEnableStateCacheRedirectToCS
b7ccf4adaf7d drm/i915/icl: Wa_2006665173
56f83663a4f3 drm/i915/icl: WaEnableFloatBlendOptimization
acee94ee0706 drm/i915/icl: WaSendPushConstantsFromMMIO
f298fa0c7607 drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
2192e7959b88 drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
fbf2254dd8d1 drm/i915/icl: WaAllowUmdWriteTRTTRootTable
2cf3133f67dc drm/i915/icl: WaAllowUMDToModifySamplerMode
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread
* ✗ Fi.CI.SPARSE: warning for Workarounds for Icelake (rev3)
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
` (22 preceding siblings ...)
2018-05-08 22:28 ` ✗ Fi.CI.CHECKPATCH: warning for Workarounds for Icelake (rev3) Patchwork
@ 2018-05-08 22:35 ` Patchwork
2018-05-08 22:44 ` ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
26 siblings, 0 replies; 42+ messages in thread
From: Patchwork @ 2018-05-08 22:35 UTC (permalink / raw)
To: Oscar Mateo; +Cc: intel-gfx
== Series Details ==
Series: Workarounds for Icelake (rev3)
URL : https://patchwork.freedesktop.org/series/42055/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/icl: Introduce initial Icelake Workarounds
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3653:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3662:16: warning: expression using sizeof(void)
Commit: drm/i915/icl: Enable Sampler DFR
Okay!
Commit: drm/i915/icl: WaGAPZPriorityScheme
Okay!
Commit: drm/i915/icl: WaL3BankAddressHashing
Okay!
Commit: drm/i915/icl: WaModifyGamTlbPartitioning
Okay!
Commit: drm/i915/icl: WaDisableCleanEvicts
Okay!
Commit: drm/i915/icl: WaCL2SFHalfMaxAlloc
Okay!
Commit: drm/i915/icl: WaDisCtxReload
Okay!
Commit: drm/i915/icl: Wa_1405779004
Okay!
Commit: drm/i915/icl: Wa_1406680159
Okay!
Commit: drm/i915/icl: Wa_1604302699
Okay!
Commit: drm/i915/icl: Wa_1406838659
Okay!
Commit: drm/i915/icl: WaForwardProgressSoftReset
Okay!
Commit: drm/i915/icl: WaDisableImprovedTdlClkGating
Okay!
Commit: drm/i915/icl: WaEnableStateCacheRedirectToCS
Okay!
Commit: drm/i915/icl: Wa_2006665173
Okay!
Commit: drm/i915/icl: WaEnableFloatBlendOptimization
Okay!
Commit: drm/i915/icl: WaSendPushConstantsFromMMIO
Okay!
Commit: drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
Okay!
Commit: drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
Okay!
Commit: drm/i915/icl: WaAllowUmdWriteTRTTRootTable
Okay!
Commit: drm/i915/icl: WaAllowUMDToModifySamplerMode
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread
* ✓ Fi.CI.BAT: success for Workarounds for Icelake (rev3)
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
` (23 preceding siblings ...)
2018-05-08 22:35 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2018-05-08 22:44 ` Patchwork
2018-05-09 3:21 ` ✓ Fi.CI.IGT: " Patchwork
2018-05-11 13:24 ` [PATCH v3 00/22] Workarounds for Icelake Mika Kuoppala
26 siblings, 0 replies; 42+ messages in thread
From: Patchwork @ 2018-05-08 22:44 UTC (permalink / raw)
To: Oscar Mateo; +Cc: intel-gfx
== Series Details ==
Series: Workarounds for Icelake (rev3)
URL : https://patchwork.freedesktop.org/series/42055/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4160 -> Patchwork_8952 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/42055/revisions/3/mbox/
== Known issues ==
Here are the changes found in Patchwork_8952 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@debugfs_test@read_all_entries:
fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713)
==== Possible fixes ====
igt@gem_exec_suspend@basic-s4-devices:
fi-kbl-7500u: DMESG-WARN (fdo#105128) -> PASS
igt@kms_chamelium@hdmi-hpd-fast:
fi-kbl-7500u: FAIL (fdo#103841, fdo#102672) -> SKIP
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
fi-glk-j4005: DMESG-WARN (fdo#106235) -> PASS +1
igt@pm_rpm@basic-pci-d3-state:
fi-glk-j4005: DMESG-WARN (fdo#106097) -> PASS
igt@prime_vgem@basic-fence-flip:
fi-ilk-650: FAIL (fdo#104008) -> PASS
fdo#102672 https://bugs.freedesktop.org/show_bug.cgi?id=102672
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128
fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097
fdo#106235 https://bugs.freedesktop.org/show_bug.cgi?id=106235
== Participating hosts (41 -> 37) ==
Missing (4): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-skl-6700hq
== Build changes ==
* Linux: CI_DRM_4160 -> Patchwork_8952
CI_DRM_4160: 6d9a2ccf9fca7c006f24b7ff6193ee356b6d3503 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4467: 548a894dc904c4628522dbbc77cb179a4c965ebc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_8952: 2cf3133f67dceaa7537f488113ae7d2c2da550e9 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4467: dd20daa579c816498f61e08c819117ad6eb4b4a5 @ git://anongit.freedesktop.org/piglit
== Linux commits ==
2cf3133f67dc drm/i915/icl: WaAllowUMDToModifySamplerMode
fbf2254dd8d1 drm/i915/icl: WaAllowUmdWriteTRTTRootTable
2192e7959b88 drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
f298fa0c7607 drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
acee94ee0706 drm/i915/icl: WaSendPushConstantsFromMMIO
56f83663a4f3 drm/i915/icl: WaEnableFloatBlendOptimization
b7ccf4adaf7d drm/i915/icl: Wa_2006665173
fc59701816c2 drm/i915/icl: WaEnableStateCacheRedirectToCS
b3a93f743a5f drm/i915/icl: WaDisableImprovedTdlClkGating
08a43ed718f1 drm/i915/icl: WaForwardProgressSoftReset
f2b42238328a drm/i915/icl: Wa_1406838659
5bfd01f40304 drm/i915/icl: Wa_1604302699
77e246e55a00 drm/i915/icl: Wa_1406680159
5a05a81044c2 drm/i915/icl: Wa_1405779004
228bb60a8743 drm/i915/icl: WaDisCtxReload
4eabc0165b9f drm/i915/icl: WaCL2SFHalfMaxAlloc
95098d8144e7 drm/i915/icl: WaDisableCleanEvicts
71b492177fb8 drm/i915/icl: WaModifyGamTlbPartitioning
16668cca3d31 drm/i915/icl: WaL3BankAddressHashing
d056c0a6184d drm/i915/icl: WaGAPZPriorityScheme
81af04257725 drm/i915/icl: Enable Sampler DFR
e15ebaa57f79 drm/i915/icl: Introduce initial Icelake Workarounds
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8952/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread
* ✓ Fi.CI.IGT: success for Workarounds for Icelake (rev3)
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
` (24 preceding siblings ...)
2018-05-08 22:44 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-05-09 3:21 ` Patchwork
2018-05-11 13:24 ` [PATCH v3 00/22] Workarounds for Icelake Mika Kuoppala
26 siblings, 0 replies; 42+ messages in thread
From: Patchwork @ 2018-05-09 3:21 UTC (permalink / raw)
To: Oscar Mateo; +Cc: intel-gfx
== Series Details ==
Series: Workarounds for Icelake (rev3)
URL : https://patchwork.freedesktop.org/series/42055/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4160_full -> Patchwork_8952_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_8952_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_8952_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/42055/revisions/3/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_8952_full:
=== IGT changes ===
==== Warnings ====
igt@drv_selftest@live_execlists:
shard-apl: PASS -> SKIP +1
igt@drv_selftest@live_hangcheck:
shard-apl: DMESG-WARN -> DMESG-FAIL
igt@gem_exec_schedule@deep-bsd2:
shard-kbl: SKIP -> PASS +2
igt@gem_mocs_settings@mocs-rc6-bsd1:
shard-kbl: PASS -> SKIP
igt@kms_cursor_crc@cursor-size-change:
shard-snb: PASS -> SKIP
igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt:
shard-snb: SKIP -> PASS
== Known issues ==
Here are the changes found in Patchwork_8952_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_flip@absolute-wf_vblank-interruptible:
shard-glk: PASS -> FAIL (fdo#106087)
igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
shard-apl: PASS -> FAIL (fdo#100368)
shard-glk: PASS -> FAIL (fdo#100368)
igt@kms_flip@modeset-vs-vblank-race:
shard-hsw: PASS -> FAIL (fdo#103060) +1
igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-pwrite:
shard-apl: PASS -> FAIL (fdo#104724, fdo#103167)
igt@kms_sysfs_edid_timing:
shard-apl: PASS -> WARN (fdo#100047)
==== Possible fixes ====
igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
shard-kbl: DMESG-WARN (fdo#105602, fdo#103313, fdo#103558) -> PASS +1
igt@kms_flip@wf_vblank-ts-check-interruptible:
shard-glk: FAIL (fdo#100368) -> PASS
igt@kms_vblank@pipe-c-query-forked-busy-hang:
shard-kbl: DMESG-WARN (fdo#105602, fdo#103558) -> PASS +22
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313
fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
fdo#106087 https://bugs.freedesktop.org/show_bug.cgi?id=106087
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4160 -> Patchwork_8952
CI_DRM_4160: 6d9a2ccf9fca7c006f24b7ff6193ee356b6d3503 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4467: 548a894dc904c4628522dbbc77cb179a4c965ebc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_8952: 2cf3133f67dceaa7537f488113ae7d2c2da550e9 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4467: dd20daa579c816498f61e08c819117ad6eb4b4a5 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8952/shards.html
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* Re: [PATCH v3 00/22] Workarounds for Icelake
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
` (25 preceding siblings ...)
2018-05-09 3:21 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-05-11 13:24 ` Mika Kuoppala
26 siblings, 0 replies; 42+ messages in thread
From: Mika Kuoppala @ 2018-05-11 13:24 UTC (permalink / raw)
To: Oscar Mateo, intel-gfx
Oscar Mateo <oscar.mateo@intel.com> writes:
> List of GT workarounds for Icelake that we have been carrying in internal.
> Applied lots of review comments from Mika and stamped rv-b's from him and
> Rodrigo.
>
> Oscar Mateo (22):
> drm/i915/icl: Introduce initial Icelake Workarounds
> drm/i915/icl: Enable Sampler DFR
> drm/i915/icl: WaGAPZPriorityScheme
> drm/i915/icl: WaL3BankAddressHashing
> drm/i915/icl: WaModifyGamTlbPartitioning
> drm/i915/icl: WaDisableCleanEvicts
> drm/i915/icl: WaCL2SFHalfMaxAlloc
> drm/i915/icl: WaDisCtxReload
> drm/i915/icl: Wa_1405779004
> drm/i915/icl: Wa_1406680159
> drm/i915/icl: Wa_1604302699
> drm/i915/icl: Wa_1406838659
> drm/i915/icl: WaForwardProgressSoftReset
Pushed up to this. Thank you for patches and review.
-Mika
> drm/i915/icl: WaDisableImprovedTdlClkGating
> drm/i915/icl: WaEnableStateCacheRedirectToCS
> drm/i915/icl: Wa_2006665173
> drm/i915/icl: WaEnableFloatBlendOptimization
> drm/i915/icl: WaSendPushConstantsFromMMIO
> drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
> drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
> drm/i915/icl: WaAllowUmdWriteTRTTRootTable
> drm/i915/icl: WaAllowUMDToModifySamplerMode
>
> drivers/gpu/drm/i915/i915_drv.h | 9 ++
> drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +-
> drivers/gpu/drm/i915/i915_reg.h | 77 +++++++++++++---
> drivers/gpu/drm/i915/intel_lrc.c | 2 +
> drivers/gpu/drm/i915/intel_pm.c | 11 ++-
> drivers/gpu/drm/i915/intel_uncore.c | 7 +-
> drivers/gpu/drm/i915/intel_workarounds.c | 149 +++++++++++++++++++++++++++++++
> 7 files changed, 241 insertions(+), 20 deletions(-)
>
> --
> 1.9.1
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