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From: Manish Narani <manish.narani@xilinx.com>
To: <robh+dt@kernel.org>, <mark.rutland@arm.com>,
	<catalin.marinas@arm.com>, <will.deacon@arm.com>,
	<mdf@kernel.org>, <stefan.krsmanovic@aggios.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <linux-mmc@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <adrian.hunter@intel.com>,
	<michal.simek@xilinx.com>, <ulf.hansson@linaro.org>
Cc: Manish Narani <manish.narani@xilinx.com>
Subject: [RFC PATCH 1/3] arm64: zynqmp: dt: Add support for setting SD tap delays
Date: Thu, 7 Jun 2018 17:41:38 +0530	[thread overview]
Message-ID: <1528373500-24663-1-git-send-email-manish.narani@xilinx.com> (raw)

This patch adds support for setting SD tap delays from Device Tree.
Earlier, these tap values were made static via macros in the driver.
So changing the tap values in the device tree makes the driver free
from handling different tap values inside it.

Signed-off-by: Manish Narani <manish.narani@xilinx.com>
---
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 40 ++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index a091e6f..696aac8 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -491,6 +491,26 @@
                        interrupts = <0 48 4>;
                        reg = <0x0 0xff160000 0x0 0x1000>;
                        clock-names = "clk_xin", "clk_ahb";
+                       xlnx,itap_delay_sd_hsd = <0x15>;
+                       xlnx,otap_delay_sd_hsd = <0x5>;
+                       xlnx,itap_delay_sdr25 = <0x15>;
+                       xlnx,otap_delay_sdr25 = <0x5>;
+                       xlnx,itap_delay_sdr50 = <0>;
+                       xlnx,otap_delay_sdr50 = <0x3>;
+                       xlnx,itap_delay_sd_ddr50 = <0x3D>;
+                       xlnx,otap_delay_sd_ddr50 = <0x4>;
+                       xlnx,itap_delay_mmc_hsd = <0x15>;
+                       xlnx,otap_delay_mmc_hsd = <0x6>;
+                       xlnx,itap_delay_mmc_ddr50 = <0x12>;
+                       xlnx,otap_delay_mmc_ddr50 = <0x6>;
+                       xlnx,itap_delay_sdr104_b0 = <0>;
+                       xlnx,otap_delay_sdr104_b0 = <0x3>;
+                       xlnx,itap_delay_sdr104_b2 = <0>;
+                       xlnx,otap_delay_sdr104_b2 = <0x2>;
+                       xlnx,itap_delay_mmc_hs200_b0 = <0>;
+                       xlnx,otap_delay_mmc_hs200_b0 = <0x3>;
+                       xlnx,itap_delay_mmc_hs200_b2 = <0>;
+                       xlnx,otap_delay_mmc_hs200_b2 = <0x2>;
                };

                sdhci1: sdhci@ff170000 {
@@ -500,6 +520,26 @@
                        interrupts = <0 49 4>;
                        reg = <0x0 0xff170000 0x0 0x1000>;
                        clock-names = "clk_xin", "clk_ahb";
+                       xlnx,itap_delay_sd_hsd = <0x15>;
+                       xlnx,otap_delay_sd_hsd = <0x5>;
+                       xlnx,itap_delay_sdr25 = <0x15>;
+                       xlnx,otap_delay_sdr25 = <0x5>;
+                       xlnx,itap_delay_sdr50 = <0>;
+                       xlnx,otap_delay_sdr50 = <0x3>;
+                       xlnx,itap_delay_sd_ddr50 = <0x3D>;
+                       xlnx,otap_delay_sd_ddr50 = <0x4>;
+                       xlnx,itap_delay_mmc_hsd = <0x15>;
+                       xlnx,otap_delay_mmc_hsd = <0x6>;
+                       xlnx,itap_delay_mmc_ddr50 = <0x12>;
+                       xlnx,otap_delay_mmc_ddr50 = <0x6>;
+                       xlnx,itap_delay_sdr104_b0 = <0>;
+                       xlnx,otap_delay_sdr104_b0 = <0x3>;
+                       xlnx,itap_delay_sdr104_b2 = <0>;
+                       xlnx,otap_delay_sdr104_b2 = <0x2>;
+                       xlnx,itap_delay_mmc_hs200_b0 = <0>;
+                       xlnx,otap_delay_mmc_hs200_b0 = <0x3>;
+                       xlnx,itap_delay_mmc_hs200_b2 = <0>;
+                       xlnx,otap_delay_mmc_hs200_b2 = <0x2>;
                };

                smmu: smmu@fd800000 {
--
2.7.4

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WARNING: multiple messages have this Message-ID (diff)
From: Manish Narani <manish.narani@xilinx.com>
To: robh+dt@kernel.org, mark.rutland@arm.com,
	catalin.marinas@arm.com, will.deacon@arm.com, mdf@kernel.org,
	stefan.krsmanovic@aggios.com,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org,
	devicetree@vger.kernel.org, adrian.hunter@intel.com,
	michal.simek@xilinx.com, ulf.hansson@linaro.org
Cc: Manish Narani <manish.narani@xilinx.com>
Subject: [RFC PATCH 1/3] arm64: zynqmp: dt: Add support for setting SD tap delays
Date: Thu, 7 Jun 2018 17:41:38 +0530	[thread overview]
Message-ID: <1528373500-24663-1-git-send-email-manish.narani@xilinx.com> (raw)

This patch adds support for setting SD tap delays from Device Tree.
Earlier, these tap values were made static via macros in the driver.
So changing the tap values in the device tree makes the driver free
from handling different tap values inside it.

Signed-off-by: Manish Narani <manish.narani@xilinx.com>
---
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 40 ++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index a091e6f..696aac8 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -491,6 +491,26 @@
                        interrupts = <0 48 4>;
                        reg = <0x0 0xff160000 0x0 0x1000>;
                        clock-names = "clk_xin", "clk_ahb";
+                       xlnx,itap_delay_sd_hsd = <0x15>;
+                       xlnx,otap_delay_sd_hsd = <0x5>;
+                       xlnx,itap_delay_sdr25 = <0x15>;
+                       xlnx,otap_delay_sdr25 = <0x5>;
+                       xlnx,itap_delay_sdr50 = <0>;
+                       xlnx,otap_delay_sdr50 = <0x3>;
+                       xlnx,itap_delay_sd_ddr50 = <0x3D>;
+                       xlnx,otap_delay_sd_ddr50 = <0x4>;
+                       xlnx,itap_delay_mmc_hsd = <0x15>;
+                       xlnx,otap_delay_mmc_hsd = <0x6>;
+                       xlnx,itap_delay_mmc_ddr50 = <0x12>;
+                       xlnx,otap_delay_mmc_ddr50 = <0x6>;
+                       xlnx,itap_delay_sdr104_b0 = <0>;
+                       xlnx,otap_delay_sdr104_b0 = <0x3>;
+                       xlnx,itap_delay_sdr104_b2 = <0>;
+                       xlnx,otap_delay_sdr104_b2 = <0x2>;
+                       xlnx,itap_delay_mmc_hs200_b0 = <0>;
+                       xlnx,otap_delay_mmc_hs200_b0 = <0x3>;
+                       xlnx,itap_delay_mmc_hs200_b2 = <0>;
+                       xlnx,otap_delay_mmc_hs200_b2 = <0x2>;
                };

                sdhci1: sdhci@ff170000 {
@@ -500,6 +520,26 @@
                        interrupts = <0 49 4>;
                        reg = <0x0 0xff170000 0x0 0x1000>;
                        clock-names = "clk_xin", "clk_ahb";
+                       xlnx,itap_delay_sd_hsd = <0x15>;
+                       xlnx,otap_delay_sd_hsd = <0x5>;
+                       xlnx,itap_delay_sdr25 = <0x15>;
+                       xlnx,otap_delay_sdr25 = <0x5>;
+                       xlnx,itap_delay_sdr50 = <0>;
+                       xlnx,otap_delay_sdr50 = <0x3>;
+                       xlnx,itap_delay_sd_ddr50 = <0x3D>;
+                       xlnx,otap_delay_sd_ddr50 = <0x4>;
+                       xlnx,itap_delay_mmc_hsd = <0x15>;
+                       xlnx,otap_delay_mmc_hsd = <0x6>;
+                       xlnx,itap_delay_mmc_ddr50 = <0x12>;
+                       xlnx,otap_delay_mmc_ddr50 = <0x6>;
+                       xlnx,itap_delay_sdr104_b0 = <0>;
+                       xlnx,otap_delay_sdr104_b0 = <0x3>;
+                       xlnx,itap_delay_sdr104_b2 = <0>;
+                       xlnx,otap_delay_sdr104_b2 = <0x2>;
+                       xlnx,itap_delay_mmc_hs200_b0 = <0>;
+                       xlnx,otap_delay_mmc_hs200_b0 = <0x3>;
+                       xlnx,itap_delay_mmc_hs200_b2 = <0>;
+                       xlnx,otap_delay_mmc_hs200_b2 = <0x2>;
                };

                smmu: smmu@fd800000 {
--
2.7.4

This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.

WARNING: multiple messages have this Message-ID (diff)
From: manish.narani@xilinx.com (Manish Narani)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH 1/3] arm64: zynqmp: dt: Add support for setting SD tap delays
Date: Thu, 7 Jun 2018 17:41:38 +0530	[thread overview]
Message-ID: <1528373500-24663-1-git-send-email-manish.narani@xilinx.com> (raw)

This patch adds support for setting SD tap delays from Device Tree.
Earlier, these tap values were made static via macros in the driver.
So changing the tap values in the device tree makes the driver free
from handling different tap values inside it.

Signed-off-by: Manish Narani <manish.narani@xilinx.com>
---
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 40 ++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index a091e6f..696aac8 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -491,6 +491,26 @@
                        interrupts = <0 48 4>;
                        reg = <0x0 0xff160000 0x0 0x1000>;
                        clock-names = "clk_xin", "clk_ahb";
+                       xlnx,itap_delay_sd_hsd = <0x15>;
+                       xlnx,otap_delay_sd_hsd = <0x5>;
+                       xlnx,itap_delay_sdr25 = <0x15>;
+                       xlnx,otap_delay_sdr25 = <0x5>;
+                       xlnx,itap_delay_sdr50 = <0>;
+                       xlnx,otap_delay_sdr50 = <0x3>;
+                       xlnx,itap_delay_sd_ddr50 = <0x3D>;
+                       xlnx,otap_delay_sd_ddr50 = <0x4>;
+                       xlnx,itap_delay_mmc_hsd = <0x15>;
+                       xlnx,otap_delay_mmc_hsd = <0x6>;
+                       xlnx,itap_delay_mmc_ddr50 = <0x12>;
+                       xlnx,otap_delay_mmc_ddr50 = <0x6>;
+                       xlnx,itap_delay_sdr104_b0 = <0>;
+                       xlnx,otap_delay_sdr104_b0 = <0x3>;
+                       xlnx,itap_delay_sdr104_b2 = <0>;
+                       xlnx,otap_delay_sdr104_b2 = <0x2>;
+                       xlnx,itap_delay_mmc_hs200_b0 = <0>;
+                       xlnx,otap_delay_mmc_hs200_b0 = <0x3>;
+                       xlnx,itap_delay_mmc_hs200_b2 = <0>;
+                       xlnx,otap_delay_mmc_hs200_b2 = <0x2>;
                };

                sdhci1: sdhci at ff170000 {
@@ -500,6 +520,26 @@
                        interrupts = <0 49 4>;
                        reg = <0x0 0xff170000 0x0 0x1000>;
                        clock-names = "clk_xin", "clk_ahb";
+                       xlnx,itap_delay_sd_hsd = <0x15>;
+                       xlnx,otap_delay_sd_hsd = <0x5>;
+                       xlnx,itap_delay_sdr25 = <0x15>;
+                       xlnx,otap_delay_sdr25 = <0x5>;
+                       xlnx,itap_delay_sdr50 = <0>;
+                       xlnx,otap_delay_sdr50 = <0x3>;
+                       xlnx,itap_delay_sd_ddr50 = <0x3D>;
+                       xlnx,otap_delay_sd_ddr50 = <0x4>;
+                       xlnx,itap_delay_mmc_hsd = <0x15>;
+                       xlnx,otap_delay_mmc_hsd = <0x6>;
+                       xlnx,itap_delay_mmc_ddr50 = <0x12>;
+                       xlnx,otap_delay_mmc_ddr50 = <0x6>;
+                       xlnx,itap_delay_sdr104_b0 = <0>;
+                       xlnx,otap_delay_sdr104_b0 = <0x3>;
+                       xlnx,itap_delay_sdr104_b2 = <0>;
+                       xlnx,otap_delay_sdr104_b2 = <0x2>;
+                       xlnx,itap_delay_mmc_hs200_b0 = <0>;
+                       xlnx,otap_delay_mmc_hs200_b0 = <0x3>;
+                       xlnx,itap_delay_mmc_hs200_b2 = <0>;
+                       xlnx,otap_delay_mmc_hs200_b2 = <0x2>;
                };

                smmu: smmu at fd800000 {
--
2.7.4

This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.

             reply	other threads:[~2018-06-07 12:12 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-07 12:11 Manish Narani [this message]
2018-06-07 12:11 ` [RFC PATCH 1/3] arm64: zynqmp: dt: Add support for setting SD tap delays Manish Narani
2018-06-07 12:11 ` Manish Narani
2018-06-07 12:11 ` [RFC PATCH 2/3] dt: bindings: Add SD tap value properties details Manish Narani
2018-06-07 12:11   ` Manish Narani
2018-06-07 12:11   ` Manish Narani
2018-06-07 12:47   ` Mark Rutland
2018-06-07 12:47     ` Mark Rutland
2018-06-21 12:41     ` Manish Narani
2018-06-21 12:41       ` Manish Narani
2018-06-21 12:41       ` Manish Narani
2018-06-07 12:11 ` [RFC PATCH 3/3] sdhci: arasan: Add support to read Tap Delay values from DT Manish Narani
2018-06-07 12:11   ` Manish Narani
2018-06-07 12:11   ` Manish Narani
2018-06-14  5:38   ` Manish Narani
2018-06-14  5:38     ` Manish Narani
2018-06-14  5:38     ` Manish Narani
2018-06-19 11:38     ` Adrian Hunter
2018-06-19 11:38       ` Adrian Hunter
2018-06-19 11:38       ` Adrian Hunter
2018-06-21 12:54       ` Manish Narani
2018-06-21 12:54         ` Manish Narani
2018-06-21 12:54         ` Manish Narani
2018-07-09 10:38       ` Manish Narani
2018-07-09 10:38         ` Manish Narani
2018-07-09 10:38         ` Manish Narani
2018-07-10  8:31   ` Ulf Hansson
2018-07-10  8:31     ` Ulf Hansson
2018-07-20  6:23     ` Manish Narani
2018-07-20  6:23       ` Manish Narani

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