[PATCH 0/5] PCI: cadence: Host and EP driver updates for PHY and power management

[PATCH 0/5] PCI: cadence: Host and EP driver updates for PHY and power management

[Alan Douglas]

This is a series of patches for the cadence PCIe host and EP drivers, to:
 - Add optional list of generic PHYs to host and EP drivers
 - Add PHY bindings to devicetree
 - Add Power Management ops, which will enable/disable PHYs if present
 - Add shutdown handler to host driver
 - Update cdns_pcie_writel function signature

Changes in v3:
	Use devm_phy_optional_get() to get optional PHY
	Updated decription in DT bindings to cover use of single/multiple PHYs
	Split patch to add shutdown callback in separate patch
	Re-based on v4.18-rc1

Changes in v2:
	Split commit into four patches
	Re-based on v4.17-rc1

Alan Douglas (5):
  PCI: cadence: Update cdns_pcie_writel function signature
  PCI: cadence: Add generic PHY support to host and EP drivers
  dt-bindings: PCI: cadence: Add DT bindings for optional PHYs
  PCI: cadence: Add Power Management ops for host and EP
  PCI: cadence: Add shutdown callback to host driver

 .../devicetree/bindings/pci/cdns,cdns-pcie-ep.txt  |    5 +
 .../bindings/pci/cdns,cdns-pcie-host.txt           |    6 +
 drivers/pci/controller/pcie-cadence-ep.c           |   15 +++-
 drivers/pci/controller/pcie-cadence-host.c         |   33 +++++
 drivers/pci/controller/pcie-cadence.c              |  123 ++++++++++++++++++++
 drivers/pci/controller/pcie-cadence.h              |   13 ++-
 6 files changed, 193 insertions(+), 2 deletions(-)

[PATCH 0/5] PCI: cadence: Host and EP driver updates for PHY and power management

[Alan Douglas]

This is a series of patches for the cadence PCIe host and EP drivers, to:
 - Add optional list of generic PHYs to host and EP drivers
 - Add PHY bindings to devicetree
 - Add Power Management ops, which will enable/disable PHYs if present
 - Add shutdown handler to host driver
 - Update cdns_pcie_writel function signature

Changes in v3:
	Use devm_phy_optional_get() to get optional PHY
	Updated decription in DT bindings to cover use of single/multiple PHYs
	Split patch to add shutdown callback in separate patch
	Re-based on v4.18-rc1

Changes in v2:
	Split commit into four patches
	Re-based on v4.17-rc1

Alan Douglas (5):
  PCI: cadence: Update cdns_pcie_writel function signature
  PCI: cadence: Add generic PHY support to host and EP drivers
  dt-bindings: PCI: cadence: Add DT bindings for optional PHYs
  PCI: cadence: Add Power Management ops for host and EP
  PCI: cadence: Add shutdown callback to host driver

 .../devicetree/bindings/pci/cdns,cdns-pcie-ep.txt  |    5 +
 .../bindings/pci/cdns,cdns-pcie-host.txt           |    6 +
 drivers/pci/controller/pcie-cadence-ep.c           |   15 +++-
 drivers/pci/controller/pcie-cadence-host.c         |   33 +++++
 drivers/pci/controller/pcie-cadence.c              |  123 ++++++++++++++++++++
 drivers/pci/controller/pcie-cadence.h              |   13 ++-
 6 files changed, 193 insertions(+), 2 deletions(-)

[PATCH 1/5] PCI: cadence: Update cdns_pcie_writel function signature

[Alan Douglas]

Change cdns_pcie_writel() signature, u16 value changed to u32, since
this function should write a long value

Signed-off-by: Alan Douglas <adouglas@cadence.com>
---
 drivers/pci/controller/pcie-cadence.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/pci/controller/pcie-cadence.h b/drivers/pci/controller/pcie-cadence.h
index 4bb2733..ed336cc 100644
--- a/drivers/pci/controller/pcie-cadence.h
+++ b/drivers/pci/controller/pcie-cadence.h
@@ -279,7 +279,7 @@ static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn,
 }
 
 static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn,
-					  u32 reg, u16 value)
+					  u32 reg, u32 value)
 {
 	writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
 }
-- 
1.7.1

[PATCH 1/5] PCI: cadence: Update cdns_pcie_writel function signature

[Alan Douglas]

Change cdns_pcie_writel() signature, u16 value changed to u32, since
this function should write a long value

Signed-off-by: Alan Douglas <adouglas@cadence.com>
---
 drivers/pci/controller/pcie-cadence.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/pci/controller/pcie-cadence.h b/drivers/pci/controller/pcie-cadence.h
index 4bb2733..ed336cc 100644
--- a/drivers/pci/controller/pcie-cadence.h
+++ b/drivers/pci/controller/pcie-cadence.h
@@ -279,7 +279,7 @@ static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn,
 }
 
 static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn,
-					  u32 reg, u16 value)
+					  u32 reg, u32 value)
 {
 	writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
 }
-- 
1.7.1

[PATCH 2/5] PCI: cadence: Add generic PHY support to host and EP drivers

[Alan Douglas]

If PHYs are present, they will be initialized and enabled in driver probe

Signed-off-by: Alan Douglas <adouglas@cadence.com>
---
 drivers/pci/controller/pcie-cadence-ep.c   |   14 ++++-
 drivers/pci/controller/pcie-cadence-host.c |   15 +++++
 drivers/pci/controller/pcie-cadence.c      |   93 ++++++++++++++++++++++++++++
 drivers/pci/controller/pcie-cadence.h      |    7 ++
 4 files changed, 128 insertions(+), 1 deletions(-)

diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c
index e3fe412..c02f33d 100644
--- a/drivers/pci/controller/pcie-cadence-ep.c
+++ b/drivers/pci/controller/pcie-cadence-ep.c
@@ -439,6 +439,7 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
 	struct pci_epc *epc;
 	struct resource *res;
 	int ret;
+	int phy_count;
 
 	ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
 	if (!ep)
@@ -473,6 +474,12 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
 	if (!ep->ob_addr)
 		return -ENOMEM;
 
+	ret = cdns_pcie_init_phy(dev, pcie);
+	if (ret) {
+		dev_err(dev, "failed to init phy\n");
+		return ret;
+	}
+	platform_set_drvdata(pdev, pcie);
 	pm_runtime_enable(dev);
 	ret = pm_runtime_get_sync(dev);
 	if (ret < 0) {
@@ -521,6 +528,10 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
 
  err_get_sync:
 	pm_runtime_disable(dev);
+	cdns_pcie_disable_phy(pcie);
+	phy_count = pcie->phy_count;
+	while (phy_count--)
+		device_link_del(pcie->link[phy_count]);
 
 	return ret;
 }
@@ -528,6 +539,7 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
 static void cdns_pcie_ep_shutdown(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
+	struct cdns_pcie *pcie = dev_get_drvdata(dev);
 	int ret;
 
 	ret = pm_runtime_put_sync(dev);
@@ -536,7 +548,7 @@ static void cdns_pcie_ep_shutdown(struct platform_device *pdev)
 
 	pm_runtime_disable(dev);
 
-	/* The PCIe controller can't be disabled. */
+	cdns_pcie_disable_phy(pcie);
 }
 
 static struct platform_driver cdns_pcie_ep_driver = {
diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c
index a4ebbd3..36f3109 100644
--- a/drivers/pci/controller/pcie-cadence-host.c
+++ b/drivers/pci/controller/pcie-cadence-host.c
@@ -58,6 +58,9 @@ struct cdns_pcie_rc {
 
 		return pcie->reg_base + (where & 0xfff);
 	}
+	/* Check that the link is up */
+	if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1))
+		return NULL;
 
 	/* Update Output registers for AXI region 0. */
 	addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) |
@@ -239,6 +242,7 @@ static int cdns_pcie_host_probe(struct platform_device *pdev)
 	struct cdns_pcie *pcie;
 	struct resource *res;
 	int ret;
+	int phy_count;
 
 	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
 	if (!bridge)
@@ -290,6 +294,13 @@ static int cdns_pcie_host_probe(struct platform_device *pdev)
 	}
 	pcie->mem_res = res;
 
+	ret = cdns_pcie_init_phy(dev, pcie);
+	if (ret) {
+		dev_err(dev, "failed to init phy\n");
+		return ret;
+	}
+	platform_set_drvdata(pdev, pcie);
+
 	pm_runtime_enable(dev);
 	ret = pm_runtime_get_sync(dev);
 	if (ret < 0) {
@@ -322,6 +333,10 @@ static int cdns_pcie_host_probe(struct platform_device *pdev)
 
  err_get_sync:
 	pm_runtime_disable(dev);
+	cdns_pcie_disable_phy(pcie);
+	phy_count = pcie->phy_count;
+	while (phy_count--)
+		device_link_del(pcie->link[phy_count]);
 
 	return ret;
 }
diff --git a/drivers/pci/controller/pcie-cadence.c b/drivers/pci/controller/pcie-cadence.c
index 138d113..2edc126 100644
--- a/drivers/pci/controller/pcie-cadence.c
+++ b/drivers/pci/controller/pcie-cadence.c
@@ -124,3 +124,96 @@ void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r)
 	cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), 0);
 	cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), 0);
 }
+
+void cdns_pcie_disable_phy(struct cdns_pcie *pcie)
+{
+	int i = pcie->phy_count;
+
+	while (i--) {
+		phy_power_off(pcie->phy[i]);
+		phy_exit(pcie->phy[i]);
+	}
+}
+
+int cdns_pcie_enable_phy(struct cdns_pcie *pcie)
+{
+	int ret;
+	int i;
+
+	for (i = 0; i < pcie->phy_count; i++) {
+		ret = phy_init(pcie->phy[i]);
+		if (ret < 0)
+			goto err_phy;
+
+		ret = phy_power_on(pcie->phy[i]);
+		if (ret < 0) {
+			phy_exit(pcie->phy[i]);
+			goto err_phy;
+		}
+	}
+
+	return 0;
+
+err_phy:
+	while (--i >= 0) {
+		phy_power_off(pcie->phy[i]);
+		phy_exit(pcie->phy[i]);
+	}
+
+	return ret;
+}
+
+int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
+{
+	struct device_node *np = dev->of_node;
+	int phy_count;
+	struct phy **phy;
+	struct device_link **link;
+	int i;
+	int ret;
+	const char *name;
+
+	phy_count = of_property_count_strings(np, "phy-names");
+	if (phy_count < 1) {
+		dev_err(dev, "no phy-names.  PHY will not be initialized\n");
+		pcie->phy_count = 0;
+		return 0;
+	}
+
+	phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL);
+	if (!phy)
+		return -ENOMEM;
+
+	link = devm_kzalloc(dev, sizeof(*link) * phy_count, GFP_KERNEL);
+	if (!link)
+		return -ENOMEM;
+
+	for (i = 0; i < phy_count; i++) {
+		of_property_read_string_index(np, "phy-names", i, &name);
+		phy[i] = devm_phy_optional_get(dev, name);
+		if (IS_ERR(phy))
+			return PTR_ERR(phy);
+
+		link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
+		if (!link[i]) {
+			ret = -EINVAL;
+			goto err_link;
+		}
+	}
+
+	pcie->phy_count = phy_count;
+	pcie->phy = phy;
+	pcie->link = link;
+
+	ret =  cdns_pcie_enable_phy(pcie);
+	if (ret)
+		goto err_link;
+
+	return 0;
+
+err_link:
+	while (--i >= 0)
+		device_link_del(link[i]);
+
+	return ret;
+}
diff --git a/drivers/pci/controller/pcie-cadence.h b/drivers/pci/controller/pcie-cadence.h
index ed336cc..b342c80 100644
--- a/drivers/pci/controller/pcie-cadence.h
+++ b/drivers/pci/controller/pcie-cadence.h
@@ -8,6 +8,7 @@
 
 #include <linux/kernel.h>
 #include <linux/pci.h>
+#include <linux/phy/phy.h>
 
 /*
  * Local Management Registers
@@ -229,6 +230,9 @@ struct cdns_pcie {
 	struct resource		*mem_res;
 	bool			is_rc;
 	u8			bus;
+	int			phy_count;
+	struct phy		**phy;
+	struct device_link	**link;
 };
 
 /* Register access */
@@ -307,5 +311,8 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn,
 						  u32 r, u64 cpu_addr);
 
 void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r);
+void cdns_pcie_disable_phy(struct cdns_pcie *pcie);
+int cdns_pcie_enable_phy(struct cdns_pcie *pcie);
+int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie);
 
 #endif /* _PCIE_CADENCE_H */
-- 
1.7.1

[PATCH 2/5] PCI: cadence: Add generic PHY support to host and EP drivers

[Alan Douglas]

If PHYs are present, they will be initialized and enabled in driver probe

Signed-off-by: Alan Douglas <adouglas@cadence.com>
---
 drivers/pci/controller/pcie-cadence-ep.c   |   14 ++++-
 drivers/pci/controller/pcie-cadence-host.c |   15 +++++
 drivers/pci/controller/pcie-cadence.c      |   93 ++++++++++++++++++++++++++++
 drivers/pci/controller/pcie-cadence.h      |    7 ++
 4 files changed, 128 insertions(+), 1 deletions(-)

diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c
index e3fe412..c02f33d 100644
--- a/drivers/pci/controller/pcie-cadence-ep.c
+++ b/drivers/pci/controller/pcie-cadence-ep.c
@@ -439,6 +439,7 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
 	struct pci_epc *epc;
 	struct resource *res;
 	int ret;
+	int phy_count;
 
 	ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
 	if (!ep)
@@ -473,6 +474,12 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
 	if (!ep->ob_addr)
 		return -ENOMEM;
 
+	ret = cdns_pcie_init_phy(dev, pcie);
+	if (ret) {
+		dev_err(dev, "failed to init phy\n");
+		return ret;
+	}
+	platform_set_drvdata(pdev, pcie);
 	pm_runtime_enable(dev);
 	ret = pm_runtime_get_sync(dev);
 	if (ret < 0) {
@@ -521,6 +528,10 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
 
  err_get_sync:
 	pm_runtime_disable(dev);
+	cdns_pcie_disable_phy(pcie);
+	phy_count = pcie->phy_count;
+	while (phy_count--)
+		device_link_del(pcie->link[phy_count]);
 
 	return ret;
 }
@@ -528,6 +539,7 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
 static void cdns_pcie_ep_shutdown(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
+	struct cdns_pcie *pcie = dev_get_drvdata(dev);
 	int ret;
 
 	ret = pm_runtime_put_sync(dev);
@@ -536,7 +548,7 @@ static void cdns_pcie_ep_shutdown(struct platform_device *pdev)
 
 	pm_runtime_disable(dev);
 
-	/* The PCIe controller can't be disabled. */
+	cdns_pcie_disable_phy(pcie);
 }
 
 static struct platform_driver cdns_pcie_ep_driver = {
diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c
index a4ebbd3..36f3109 100644
--- a/drivers/pci/controller/pcie-cadence-host.c
+++ b/drivers/pci/controller/pcie-cadence-host.c
@@ -58,6 +58,9 @@ struct cdns_pcie_rc {
 
 		return pcie->reg_base + (where & 0xfff);
 	}
+	/* Check that the link is up */
+	if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1))
+		return NULL;
 
 	/* Update Output registers for AXI region 0. */
 	addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) |
@@ -239,6 +242,7 @@ static int cdns_pcie_host_probe(struct platform_device *pdev)
 	struct cdns_pcie *pcie;
 	struct resource *res;
 	int ret;
+	int phy_count;
 
 	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
 	if (!bridge)
@@ -290,6 +294,13 @@ static int cdns_pcie_host_probe(struct platform_device *pdev)
 	}
 	pcie->mem_res = res;
 
+	ret = cdns_pcie_init_phy(dev, pcie);
+	if (ret) {
+		dev_err(dev, "failed to init phy\n");
+		return ret;
+	}
+	platform_set_drvdata(pdev, pcie);
+
 	pm_runtime_enable(dev);
 	ret = pm_runtime_get_sync(dev);
 	if (ret < 0) {
@@ -322,6 +333,10 @@ static int cdns_pcie_host_probe(struct platform_device *pdev)
 
  err_get_sync:
 	pm_runtime_disable(dev);
+	cdns_pcie_disable_phy(pcie);
+	phy_count = pcie->phy_count;
+	while (phy_count--)
+		device_link_del(pcie->link[phy_count]);
 
 	return ret;
 }
diff --git a/drivers/pci/controller/pcie-cadence.c b/drivers/pci/controller/pcie-cadence.c
index 138d113..2edc126 100644
--- a/drivers/pci/controller/pcie-cadence.c
+++ b/drivers/pci/controller/pcie-cadence.c
@@ -124,3 +124,96 @@ void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r)
 	cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), 0);
 	cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), 0);
 }
+
+void cdns_pcie_disable_phy(struct cdns_pcie *pcie)
+{
+	int i = pcie->phy_count;
+
+	while (i--) {
+		phy_power_off(pcie->phy[i]);
+		phy_exit(pcie->phy[i]);
+	}
+}
+
+int cdns_pcie_enable_phy(struct cdns_pcie *pcie)
+{
+	int ret;
+	int i;
+
+	for (i = 0; i < pcie->phy_count; i++) {
+		ret = phy_init(pcie->phy[i]);
+		if (ret < 0)
+			goto err_phy;
+
+		ret = phy_power_on(pcie->phy[i]);
+		if (ret < 0) {
+			phy_exit(pcie->phy[i]);
+			goto err_phy;
+		}
+	}
+
+	return 0;
+
+err_phy:
+	while (--i >= 0) {
+		phy_power_off(pcie->phy[i]);
+		phy_exit(pcie->phy[i]);
+	}
+
+	return ret;
+}
+
+int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
+{
+	struct device_node *np = dev->of_node;
+	int phy_count;
+	struct phy **phy;
+	struct device_link **link;
+	int i;
+	int ret;
+	const char *name;
+
+	phy_count = of_property_count_strings(np, "phy-names");
+	if (phy_count < 1) {
+		dev_err(dev, "no phy-names.  PHY will not be initialized\n");
+		pcie->phy_count = 0;
+		return 0;
+	}
+
+	phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL);
+	if (!phy)
+		return -ENOMEM;
+
+	link = devm_kzalloc(dev, sizeof(*link) * phy_count, GFP_KERNEL);
+	if (!link)
+		return -ENOMEM;
+
+	for (i = 0; i < phy_count; i++) {
+		of_property_read_string_index(np, "phy-names", i, &name);
+		phy[i] = devm_phy_optional_get(dev, name);
+		if (IS_ERR(phy))
+			return PTR_ERR(phy);
+
+		link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
+		if (!link[i]) {
+			ret = -EINVAL;
+			goto err_link;
+		}
+	}
+
+	pcie->phy_count = phy_count;
+	pcie->phy = phy;
+	pcie->link = link;
+
+	ret =  cdns_pcie_enable_phy(pcie);
+	if (ret)
+		goto err_link;
+
+	return 0;
+
+err_link:
+	while (--i >= 0)
+		device_link_del(link[i]);
+
+	return ret;
+}
diff --git a/drivers/pci/controller/pcie-cadence.h b/drivers/pci/controller/pcie-cadence.h
index ed336cc..b342c80 100644
--- a/drivers/pci/controller/pcie-cadence.h
+++ b/drivers/pci/controller/pcie-cadence.h
@@ -8,6 +8,7 @@
 
 #include <linux/kernel.h>
 #include <linux/pci.h>
+#include <linux/phy/phy.h>
 
 /*
  * Local Management Registers
@@ -229,6 +230,9 @@ struct cdns_pcie {
 	struct resource		*mem_res;
 	bool			is_rc;
 	u8			bus;
+	int			phy_count;
+	struct phy		**phy;
+	struct device_link	**link;
 };
 
 /* Register access */
@@ -307,5 +311,8 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn,
 						  u32 r, u64 cpu_addr);
 
 void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r);
+void cdns_pcie_disable_phy(struct cdns_pcie *pcie);
+int cdns_pcie_enable_phy(struct cdns_pcie *pcie);
+int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie);
 
 #endif /* _PCIE_CADENCE_H */
-- 
1.7.1

[PATCH 3/5] dt-bindings: PCI: cadence: Add DT bindings for optional PHYs

[Alan Douglas]

Update DT documentation to include optional PHYs for cadence PCIe
host and endpoint controllers.

Signed-off-by: Alan Douglas <adouglas@cadence.com>
---
 .../devicetree/bindings/pci/cdns,cdns-pcie-ep.txt  |    5 +++++
 .../bindings/pci/cdns,cdns-pcie-host.txt           |    6 ++++++
 2 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
index 9a30523..4a0475e 100644
--- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
@@ -9,6 +9,9 @@ Required properties:
 
 Optional properties:
 - max-functions: Maximum number of functions that can be configured (default 1).
+- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
+  than one in the list.  If only one PHY listed it must manage all lanes. 
+- phy-names:  List of names to identify the PHY.
 
 Example:
 
@@ -19,4 +22,6 @@ pcie@fc000000 {
 	reg-names = "reg", "mem";
 	cdns,max-outbound-regions = <16>;
 	max-functions = /bits/ 8 <8>;
+	phys = <&ep_phy0 &ep_phy1>;
+	phy-names = "pcie-lane0","pcie-lane1";
 };
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
index 20a33f3..91de69c 100644
--- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
@@ -24,6 +24,9 @@ Optional properties:
   translations (default 32)
 - vendor-id: The PCI vendor ID (16 bits, default is design dependent)
 - device-id: The PCI device ID (16 bits, default is design dependent)
+- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
+  than one in the list.  If only one PHY listed it must manage all lanes. 
+- phy-names:  List of names to identify the PHY.
 
 Example:
 
@@ -57,4 +60,7 @@ pcie@fb000000 {
 	interrupt-map-mask = <0x0 0x0 0x0  0x7>;
 
 	msi-parent = <&its_pci>;
+
+	phys = <&pcie_phy0>;
+	phy-names = "pcie-phy";
 };
-- 
1.7.1

[PATCH 3/5] dt-bindings: PCI: cadence: Add DT bindings for optional PHYs

[Alan Douglas]

Update DT documentation to include optional PHYs for cadence PCIe
host and endpoint controllers.

Signed-off-by: Alan Douglas <adouglas@cadence.com>
---
 .../devicetree/bindings/pci/cdns,cdns-pcie-ep.txt  |    5 +++++
 .../bindings/pci/cdns,cdns-pcie-host.txt           |    6 ++++++
 2 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
index 9a30523..4a0475e 100644
--- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
@@ -9,6 +9,9 @@ Required properties:
 
 Optional properties:
 - max-functions: Maximum number of functions that can be configured (default 1).
+- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
+  than one in the list.  If only one PHY listed it must manage all lanes. 
+- phy-names:  List of names to identify the PHY.
 
 Example:
 
@@ -19,4 +22,6 @@ pcie@fc000000 {
 	reg-names = "reg", "mem";
 	cdns,max-outbound-regions = <16>;
 	max-functions = /bits/ 8 <8>;
+	phys = <&ep_phy0 &ep_phy1>;
+	phy-names = "pcie-lane0","pcie-lane1";
 };
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
index 20a33f3..91de69c 100644
--- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
@@ -24,6 +24,9 @@ Optional properties:
   translations (default 32)
 - vendor-id: The PCI vendor ID (16 bits, default is design dependent)
 - device-id: The PCI device ID (16 bits, default is design dependent)
+- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
+  than one in the list.  If only one PHY listed it must manage all lanes. 
+- phy-names:  List of names to identify the PHY.
 
 Example:
 
@@ -57,4 +60,7 @@ pcie@fb000000 {
 	interrupt-map-mask = <0x0 0x0 0x0  0x7>;
 
 	msi-parent = <&its_pci>;
+
+	phys = <&pcie_phy0>;
+	phy-names = "pcie-phy";
 };
-- 
1.7.1

Re: [PATCH 3/5] dt-bindings: PCI: cadence: Add DT bindings for optional PHYs

[Rob Herring]

On Mon, Jun 25, 2018 at 09:30:51AM +0100, Alan Douglas wrote:
> Update DT documentation to include optional PHYs for cadence PCIe
> host and endpoint controllers.
> 
> Signed-off-by: Alan Douglas <adouglas@cadence.com>
> ---
>  .../devicetree/bindings/pci/cdns,cdns-pcie-ep.txt  |    5 +++++
>  .../bindings/pci/cdns,cdns-pcie-host.txt           |    6 ++++++
>  2 files changed, 11 insertions(+), 0 deletions(-)

Reviewed-by: Rob Herring <robh@kernel.org>

[PATCH 4/5] PCI: cadence: Add Power Management ops for host and EP

[Alan Douglas]

These PM ops will enable/disable the optional PHYs if present.  The
AXI link-down register in the host driver is now cleared in
cdns_pci_map_bus since the link-down bit will be set if the PHY has
been disabled.  It is not cleared when enabling the PHY, since the
link will not yet be up.

Signed-off-by: Alan Douglas <adouglas@cadence.com>
---
 drivers/pci/controller/pcie-cadence-ep.c   |    1 +
 drivers/pci/controller/pcie-cadence-host.c |    3 ++
 drivers/pci/controller/pcie-cadence.c      |   30 ++++++++++++++++++++++++++++
 drivers/pci/controller/pcie-cadence.h      |    4 +++
 4 files changed, 38 insertions(+), 0 deletions(-)

diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c
index c02f33d..3eabd99 100644
--- a/drivers/pci/controller/pcie-cadence-ep.c
+++ b/drivers/pci/controller/pcie-cadence-ep.c
@@ -555,6 +555,7 @@ static void cdns_pcie_ep_shutdown(struct platform_device *pdev)
 	.driver = {
 		.name = "cdns-pcie-ep",
 		.of_match_table = cdns_pcie_ep_of_match,
+		.pm	= &cdns_pcie_pm_ops,
 	},
 	.probe = cdns_pcie_ep_probe,
 	.shutdown = cdns_pcie_ep_shutdown,
diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c
index 36f3109..e3e9b7d 100644
--- a/drivers/pci/controller/pcie-cadence-host.c
+++ b/drivers/pci/controller/pcie-cadence-host.c
@@ -61,6 +61,8 @@ struct cdns_pcie_rc {
 	/* Check that the link is up */
 	if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1))
 		return NULL;
+	/* Clear AXI link-down status */
+	cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0);
 
 	/* Update Output registers for AXI region 0. */
 	addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) |
@@ -345,6 +347,7 @@ static int cdns_pcie_host_probe(struct platform_device *pdev)
 	.driver = {
 		.name = "cdns-pcie-host",
 		.of_match_table = cdns_pcie_host_of_match,
+		.pm	= &cdns_pcie_pm_ops,
 	},
 	.probe = cdns_pcie_host_probe,
 };
diff --git a/drivers/pci/controller/pcie-cadence.c b/drivers/pci/controller/pcie-cadence.c
index 2edc126..86f1b00 100644
--- a/drivers/pci/controller/pcie-cadence.c
+++ b/drivers/pci/controller/pcie-cadence.c
@@ -217,3 +217,33 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
 
 	return ret;
 }
+
+#ifdef CONFIG_PM_SLEEP
+static int cdns_pcie_suspend_noirq(struct device *dev)
+{
+	struct cdns_pcie *pcie = dev_get_drvdata(dev);
+
+	cdns_pcie_disable_phy(pcie);
+
+	return 0;
+}
+
+static int cdns_pcie_resume_noirq(struct device *dev)
+{
+	struct cdns_pcie *pcie = dev_get_drvdata(dev);
+	int ret;
+
+	ret = cdns_pcie_enable_phy(pcie);
+	if (ret) {
+		dev_err(dev, "failed to enable phy\n");
+		return ret;
+	}
+
+	return 0;
+}
+#endif
+
+const struct dev_pm_ops cdns_pcie_pm_ops = {
+	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq,
+				      cdns_pcie_resume_noirq)
+};
diff --git a/drivers/pci/controller/pcie-cadence.h b/drivers/pci/controller/pcie-cadence.h
index b342c80..ae6bf2a 100644
--- a/drivers/pci/controller/pcie-cadence.h
+++ b/drivers/pci/controller/pcie-cadence.h
@@ -166,6 +166,9 @@
 #define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \
 	(CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008)
 
+/* AXI link down register */
+#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824)
+
 enum cdns_pcie_rp_bar {
 	RP_BAR0,
 	RP_BAR1,
@@ -314,5 +317,6 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn,
 void cdns_pcie_disable_phy(struct cdns_pcie *pcie);
 int cdns_pcie_enable_phy(struct cdns_pcie *pcie);
 int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie);
+extern const struct dev_pm_ops cdns_pcie_pm_ops;
 
 #endif /* _PCIE_CADENCE_H */
-- 
1.7.1

[PATCH 4/5] PCI: cadence: Add Power Management ops for host and EP

[Alan Douglas]

These PM ops will enable/disable the optional PHYs if present.  The
AXI link-down register in the host driver is now cleared in
cdns_pci_map_bus since the link-down bit will be set if the PHY has
been disabled.  It is not cleared when enabling the PHY, since the
link will not yet be up.

Signed-off-by: Alan Douglas <adouglas@cadence.com>
---
 drivers/pci/controller/pcie-cadence-ep.c   |    1 +
 drivers/pci/controller/pcie-cadence-host.c |    3 ++
 drivers/pci/controller/pcie-cadence.c      |   30 ++++++++++++++++++++++++++++
 drivers/pci/controller/pcie-cadence.h      |    4 +++
 4 files changed, 38 insertions(+), 0 deletions(-)

diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c
index c02f33d..3eabd99 100644
--- a/drivers/pci/controller/pcie-cadence-ep.c
+++ b/drivers/pci/controller/pcie-cadence-ep.c
@@ -555,6 +555,7 @@ static void cdns_pcie_ep_shutdown(struct platform_device *pdev)
 	.driver = {
 		.name = "cdns-pcie-ep",
 		.of_match_table = cdns_pcie_ep_of_match,
+		.pm	= &cdns_pcie_pm_ops,
 	},
 	.probe = cdns_pcie_ep_probe,
 	.shutdown = cdns_pcie_ep_shutdown,
diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c
index 36f3109..e3e9b7d 100644
--- a/drivers/pci/controller/pcie-cadence-host.c
+++ b/drivers/pci/controller/pcie-cadence-host.c
@@ -61,6 +61,8 @@ struct cdns_pcie_rc {
 	/* Check that the link is up */
 	if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1))
 		return NULL;
+	/* Clear AXI link-down status */
+	cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0);
 
 	/* Update Output registers for AXI region 0. */
 	addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) |
@@ -345,6 +347,7 @@ static int cdns_pcie_host_probe(struct platform_device *pdev)
 	.driver = {
 		.name = "cdns-pcie-host",
 		.of_match_table = cdns_pcie_host_of_match,
+		.pm	= &cdns_pcie_pm_ops,
 	},
 	.probe = cdns_pcie_host_probe,
 };
diff --git a/drivers/pci/controller/pcie-cadence.c b/drivers/pci/controller/pcie-cadence.c
index 2edc126..86f1b00 100644
--- a/drivers/pci/controller/pcie-cadence.c
+++ b/drivers/pci/controller/pcie-cadence.c
@@ -217,3 +217,33 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
 
 	return ret;
 }
+
+#ifdef CONFIG_PM_SLEEP
+static int cdns_pcie_suspend_noirq(struct device *dev)
+{
+	struct cdns_pcie *pcie = dev_get_drvdata(dev);
+
+	cdns_pcie_disable_phy(pcie);
+
+	return 0;
+}
+
+static int cdns_pcie_resume_noirq(struct device *dev)
+{
+	struct cdns_pcie *pcie = dev_get_drvdata(dev);
+	int ret;
+
+	ret = cdns_pcie_enable_phy(pcie);
+	if (ret) {
+		dev_err(dev, "failed to enable phy\n");
+		return ret;
+	}
+
+	return 0;
+}
+#endif
+
+const struct dev_pm_ops cdns_pcie_pm_ops = {
+	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq,
+				      cdns_pcie_resume_noirq)
+};
diff --git a/drivers/pci/controller/pcie-cadence.h b/drivers/pci/controller/pcie-cadence.h
index b342c80..ae6bf2a 100644
--- a/drivers/pci/controller/pcie-cadence.h
+++ b/drivers/pci/controller/pcie-cadence.h
@@ -166,6 +166,9 @@
 #define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \
 	(CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008)
 
+/* AXI link down register */
+#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824)
+
 enum cdns_pcie_rp_bar {
 	RP_BAR0,
 	RP_BAR1,
@@ -314,5 +317,6 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn,
 void cdns_pcie_disable_phy(struct cdns_pcie *pcie);
 int cdns_pcie_enable_phy(struct cdns_pcie *pcie);
 int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie);
+extern const struct dev_pm_ops cdns_pcie_pm_ops;
 
 #endif /* _PCIE_CADENCE_H */
-- 
1.7.1

Re: [PATCH 4/5] PCI: cadence: Add Power Management ops for host and EP

[Lorenzo Pieralisi]

On Mon, Jun 25, 2018 at 09:30:52AM +0100, Alan Douglas wrote:
> These PM ops will enable/disable the optional PHYs if present.  The
> AXI link-down register in the host driver is now cleared in
> cdns_pci_map_bus since the link-down bit will be set if the PHY has
> been disabled.  It is not cleared when enabling the PHY, since the
> link will not yet be up.

It is not entirely clear what you mean here, can you elaborate please ?

Thank you,
Lorenzo

> Signed-off-by: Alan Douglas <adouglas@cadence.com>
> ---
>  drivers/pci/controller/pcie-cadence-ep.c   |    1 +
>  drivers/pci/controller/pcie-cadence-host.c |    3 ++
>  drivers/pci/controller/pcie-cadence.c      |   30 ++++++++++++++++++++++++++++
>  drivers/pci/controller/pcie-cadence.h      |    4 +++
>  4 files changed, 38 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c
> index c02f33d..3eabd99 100644
> --- a/drivers/pci/controller/pcie-cadence-ep.c
> +++ b/drivers/pci/controller/pcie-cadence-ep.c
> @@ -555,6 +555,7 @@ static void cdns_pcie_ep_shutdown(struct platform_device *pdev)
>  	.driver = {
>  		.name = "cdns-pcie-ep",
>  		.of_match_table = cdns_pcie_ep_of_match,
> +		.pm	= &cdns_pcie_pm_ops,
>  	},
>  	.probe = cdns_pcie_ep_probe,
>  	.shutdown = cdns_pcie_ep_shutdown,
> diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c
> index 36f3109..e3e9b7d 100644
> --- a/drivers/pci/controller/pcie-cadence-host.c
> +++ b/drivers/pci/controller/pcie-cadence-host.c
> @@ -61,6 +61,8 @@ struct cdns_pcie_rc {
>  	/* Check that the link is up */
>  	if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1))
>  		return NULL;
> +	/* Clear AXI link-down status */
> +	cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0);
>  
>  	/* Update Output registers for AXI region 0. */
>  	addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) |
> @@ -345,6 +347,7 @@ static int cdns_pcie_host_probe(struct platform_device *pdev)
>  	.driver = {
>  		.name = "cdns-pcie-host",
>  		.of_match_table = cdns_pcie_host_of_match,
> +		.pm	= &cdns_pcie_pm_ops,
>  	},
>  	.probe = cdns_pcie_host_probe,
>  };
> diff --git a/drivers/pci/controller/pcie-cadence.c b/drivers/pci/controller/pcie-cadence.c
> index 2edc126..86f1b00 100644
> --- a/drivers/pci/controller/pcie-cadence.c
> +++ b/drivers/pci/controller/pcie-cadence.c
> @@ -217,3 +217,33 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
>  
>  	return ret;
>  }
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int cdns_pcie_suspend_noirq(struct device *dev)
> +{
> +	struct cdns_pcie *pcie = dev_get_drvdata(dev);
> +
> +	cdns_pcie_disable_phy(pcie);
> +
> +	return 0;
> +}
> +
> +static int cdns_pcie_resume_noirq(struct device *dev)
> +{
> +	struct cdns_pcie *pcie = dev_get_drvdata(dev);
> +	int ret;
> +
> +	ret = cdns_pcie_enable_phy(pcie);
> +	if (ret) {
> +		dev_err(dev, "failed to enable phy\n");
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +#endif
> +
> +const struct dev_pm_ops cdns_pcie_pm_ops = {
> +	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq,
> +				      cdns_pcie_resume_noirq)
> +};
> diff --git a/drivers/pci/controller/pcie-cadence.h b/drivers/pci/controller/pcie-cadence.h
> index b342c80..ae6bf2a 100644
> --- a/drivers/pci/controller/pcie-cadence.h
> +++ b/drivers/pci/controller/pcie-cadence.h
> @@ -166,6 +166,9 @@
>  #define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \
>  	(CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008)
>  
> +/* AXI link down register */
> +#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824)
> +
>  enum cdns_pcie_rp_bar {
>  	RP_BAR0,
>  	RP_BAR1,
> @@ -314,5 +317,6 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn,
>  void cdns_pcie_disable_phy(struct cdns_pcie *pcie);
>  int cdns_pcie_enable_phy(struct cdns_pcie *pcie);
>  int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie);
> +extern const struct dev_pm_ops cdns_pcie_pm_ops;
>  
>  #endif /* _PCIE_CADENCE_H */
> -- 
> 1.7.1
> 

RE: [PATCH 4/5] PCI: cadence: Add Power Management ops for host and EP

[Alan Douglas]

On 09 July 2018 16:34, Lorenzo Pieralisi wrote:
> On Mon, Jun 25, 2018 at 09:30:52AM +0100, Alan Douglas wrote:
> > These PM ops will enable/disable the optional PHYs if present.  The
> > AXI link-down register in the host driver is now cleared in
> > cdns_pci_map_bus since the link-down bit will be set if the PHY has
> > been disabled.  It is not cleared when enabling the PHY, since the
> > link will not yet be up.
> 
> It is not entirely clear what you mean here, can you elaborate please ?
Thanks for taking a look at this.
There is a "Link down indication bit" register in the cadence PCIe IP AXI
Configuration  Registers, which will be set by the PCIe IP after each link-
down occurrence.  This bit must be cleared before continuing, or accesses
will hang.  When the PHY is disabled, the link will go down and this bit will
be set by HW.  It will also be set after a secondary bus reset.

We cannot simply clear this bit when enabling the PHY, since at this stage
the link may not come up (e.g. because the EP PHY is disabled), and so we
need to clear it on the first access after link-up. In order to ensure this, I
simply clear it on every config access, in cdns_pci_map_bus, I couldn't think
of a good way to just do it once.

Regards,
Alan
> Thank you,
> Lorenzo
> 
> > Signed-off-by: Alan Douglas <adouglas@cadence.com>
> > ---
> >  drivers/pci/controller/pcie-cadence-ep.c   |    1 +
> >  drivers/pci/controller/pcie-cadence-host.c |    3 ++
> >  drivers/pci/controller/pcie-cadence.c      |   30 ++++++++++++++++++++++++++++
> >  drivers/pci/controller/pcie-cadence.h      |    4 +++
> >  4 files changed, 38 insertions(+), 0 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c
> > index c02f33d..3eabd99 100644
> > --- a/drivers/pci/controller/pcie-cadence-ep.c
> > +++ b/drivers/pci/controller/pcie-cadence-ep.c
> > @@ -555,6 +555,7 @@ static void cdns_pcie_ep_shutdown(struct platform_device *pdev)
> >  	.driver = {
> >  		.name = "cdns-pcie-ep",
> >  		.of_match_table = cdns_pcie_ep_of_match,
> > +		.pm	= &cdns_pcie_pm_ops,
> >  	},
> >  	.probe = cdns_pcie_ep_probe,
> >  	.shutdown = cdns_pcie_ep_shutdown,
> > diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c
> > index 36f3109..e3e9b7d 100644
> > --- a/drivers/pci/controller/pcie-cadence-host.c
> > +++ b/drivers/pci/controller/pcie-cadence-host.c
> > @@ -61,6 +61,8 @@ struct cdns_pcie_rc {
> >  	/* Check that the link is up */
> >  	if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1))
> >  		return NULL;
> > +	/* Clear AXI link-down status */
> > +	cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0);
> >
> >  	/* Update Output registers for AXI region 0. */
> >  	addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) |
> > @@ -345,6 +347,7 @@ static int cdns_pcie_host_probe(struct platform_device *pdev)
> >  	.driver = {
> >  		.name = "cdns-pcie-host",
> >  		.of_match_table = cdns_pcie_host_of_match,
> > +		.pm	= &cdns_pcie_pm_ops,
> >  	},
> >  	.probe = cdns_pcie_host_probe,
> >  };
> > diff --git a/drivers/pci/controller/pcie-cadence.c b/drivers/pci/controller/pcie-cadence.c
> > index 2edc126..86f1b00 100644
> > --- a/drivers/pci/controller/pcie-cadence.c
> > +++ b/drivers/pci/controller/pcie-cadence.c
> > @@ -217,3 +217,33 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
> >
> >  	return ret;
> >  }
> > +
> > +#ifdef CONFIG_PM_SLEEP
> > +static int cdns_pcie_suspend_noirq(struct device *dev)
> > +{
> > +	struct cdns_pcie *pcie = dev_get_drvdata(dev);
> > +
> > +	cdns_pcie_disable_phy(pcie);
> > +
> > +	return 0;
> > +}
> > +
> > +static int cdns_pcie_resume_noirq(struct device *dev)
> > +{
> > +	struct cdns_pcie *pcie = dev_get_drvdata(dev);
> > +	int ret;
> > +
> > +	ret = cdns_pcie_enable_phy(pcie);
> > +	if (ret) {
> > +		dev_err(dev, "failed to enable phy\n");
> > +		return ret;
> > +	}
> > +
> > +	return 0;
> > +}
> > +#endif
> > +
> > +const struct dev_pm_ops cdns_pcie_pm_ops = {
> > +	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq,
> > +				      cdns_pcie_resume_noirq)
> > +};
> > diff --git a/drivers/pci/controller/pcie-cadence.h b/drivers/pci/controller/pcie-cadence.h
> > index b342c80..ae6bf2a 100644
> > --- a/drivers/pci/controller/pcie-cadence.h
> > +++ b/drivers/pci/controller/pcie-cadence.h
> > @@ -166,6 +166,9 @@
> >  #define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \
> >  	(CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008)
> >
> > +/* AXI link down register */
> > +#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824)
> > +
> >  enum cdns_pcie_rp_bar {
> >  	RP_BAR0,
> >  	RP_BAR1,
> > @@ -314,5 +317,6 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn,
> >  void cdns_pcie_disable_phy(struct cdns_pcie *pcie);
> >  int cdns_pcie_enable_phy(struct cdns_pcie *pcie);
> >  int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie);
> > +extern const struct dev_pm_ops cdns_pcie_pm_ops;
> >
> >  #endif /* _PCIE_CADENCE_H */
> > --
> > 1.7.1
> >

RE: [PATCH 4/5] PCI: cadence: Add Power Management ops for host and EP

[Alan Douglas]

On 09 July 2018 16:34, Lorenzo Pieralisi wrote:
> On Mon, Jun 25, 2018 at 09:30:52AM +0100, Alan Douglas wrote:
> > These PM ops will enable/disable the optional PHYs if present.  The
> > AXI link-down register in the host driver is now cleared in
> > cdns_pci_map_bus since the link-down bit will be set if the PHY has
> > been disabled.  It is not cleared when enabling the PHY, since the
> > link will not yet be up.
>=20
> It is not entirely clear what you mean here, can you elaborate please ?
Thanks for taking a look at this.
There is a "Link down indication bit" register in the cadence PCIe IP AXI
Configuration  Registers, which will be set by the PCIe IP after each link-
down occurrence.  This bit must be cleared before continuing, or accesses
will hang.  When the PHY is disabled, the link will go down and this bit wi=
ll
be set by HW.  It will also be set after a secondary bus reset.

We cannot simply clear this bit when enabling the PHY, since at this stage
the link may not come up (e.g. because the EP PHY is disabled), and so we
need to clear it on the first access after link-up. In order to ensure this=
, I
simply clear it on every config access, in cdns_pci_map_bus, I couldn't thi=
nk
of a good way to just do it once.

Regards,
Alan
> Thank you,
> Lorenzo
>=20
> > Signed-off-by: Alan Douglas <adouglas@cadence.com>
> > ---
> >  drivers/pci/controller/pcie-cadence-ep.c   |    1 +
> >  drivers/pci/controller/pcie-cadence-host.c |    3 ++
> >  drivers/pci/controller/pcie-cadence.c      |   30 ++++++++++++++++++++=
++++++++
> >  drivers/pci/controller/pcie-cadence.h      |    4 +++
> >  4 files changed, 38 insertions(+), 0 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/con=
troller/pcie-cadence-ep.c
> > index c02f33d..3eabd99 100644
> > --- a/drivers/pci/controller/pcie-cadence-ep.c
> > +++ b/drivers/pci/controller/pcie-cadence-ep.c
> > @@ -555,6 +555,7 @@ static void cdns_pcie_ep_shutdown(struct platform_d=
evice *pdev)
> >  	.driver =3D {
> >  		.name =3D "cdns-pcie-ep",
> >  		.of_match_table =3D cdns_pcie_ep_of_match,
> > +		.pm	=3D &cdns_pcie_pm_ops,
> >  	},
> >  	.probe =3D cdns_pcie_ep_probe,
> >  	.shutdown =3D cdns_pcie_ep_shutdown,
> > diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/c=
ontroller/pcie-cadence-host.c
> > index 36f3109..e3e9b7d 100644
> > --- a/drivers/pci/controller/pcie-cadence-host.c
> > +++ b/drivers/pci/controller/pcie-cadence-host.c
> > @@ -61,6 +61,8 @@ struct cdns_pcie_rc {
> >  	/* Check that the link is up */
> >  	if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1))
> >  		return NULL;
> > +	/* Clear AXI link-down status */
> > +	cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0);
> >
> >  	/* Update Output registers for AXI region 0. */
> >  	addr0 =3D CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) |
> > @@ -345,6 +347,7 @@ static int cdns_pcie_host_probe(struct platform_dev=
ice *pdev)
> >  	.driver =3D {
> >  		.name =3D "cdns-pcie-host",
> >  		.of_match_table =3D cdns_pcie_host_of_match,
> > +		.pm	=3D &cdns_pcie_pm_ops,
> >  	},
> >  	.probe =3D cdns_pcie_host_probe,
> >  };
> > diff --git a/drivers/pci/controller/pcie-cadence.c b/drivers/pci/contro=
ller/pcie-cadence.c
> > index 2edc126..86f1b00 100644
> > --- a/drivers/pci/controller/pcie-cadence.c
> > +++ b/drivers/pci/controller/pcie-cadence.c
> > @@ -217,3 +217,33 @@ int cdns_pcie_init_phy(struct device *dev, struct =
cdns_pcie *pcie)
> >
> >  	return ret;
> >  }
> > +
> > +#ifdef CONFIG_PM_SLEEP
> > +static int cdns_pcie_suspend_noirq(struct device *dev)
> > +{
> > +	struct cdns_pcie *pcie =3D dev_get_drvdata(dev);
> > +
> > +	cdns_pcie_disable_phy(pcie);
> > +
> > +	return 0;
> > +}
> > +
> > +static int cdns_pcie_resume_noirq(struct device *dev)
> > +{
> > +	struct cdns_pcie *pcie =3D dev_get_drvdata(dev);
> > +	int ret;
> > +
> > +	ret =3D cdns_pcie_enable_phy(pcie);
> > +	if (ret) {
> > +		dev_err(dev, "failed to enable phy\n");
> > +		return ret;
> > +	}
> > +
> > +	return 0;
> > +}
> > +#endif
> > +
> > +const struct dev_pm_ops cdns_pcie_pm_ops =3D {
> > +	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq,
> > +				      cdns_pcie_resume_noirq)
> > +};
> > diff --git a/drivers/pci/controller/pcie-cadence.h b/drivers/pci/contro=
ller/pcie-cadence.h
> > index b342c80..ae6bf2a 100644
> > --- a/drivers/pci/controller/pcie-cadence.h
> > +++ b/drivers/pci/controller/pcie-cadence.h
> > @@ -166,6 +166,9 @@
> >  #define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \
> >  	(CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008)
> >
> > +/* AXI link down register */
> > +#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824)
> > +
> >  enum cdns_pcie_rp_bar {
> >  	RP_BAR0,
> >  	RP_BAR1,
> > @@ -314,5 +317,6 @@ void cdns_pcie_set_outbound_region_for_normal_msg(s=
truct cdns_pcie *pcie, u8 fn,
> >  void cdns_pcie_disable_phy(struct cdns_pcie *pcie);
> >  int cdns_pcie_enable_phy(struct cdns_pcie *pcie);
> >  int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie);
> > +extern const struct dev_pm_ops cdns_pcie_pm_ops;
> >
> >  #endif /* _PCIE_CADENCE_H */
> > --
> > 1.7.1
> >

Re: [PATCH 4/5] PCI: cadence: Add Power Management ops for host and EP

[Lorenzo Pieralisi]

On Mon, Jul 09, 2018 at 03:56:11PM +0000, Alan Douglas wrote:
> On 09 July 2018 16:34, Lorenzo Pieralisi wrote:
> > On Mon, Jun 25, 2018 at 09:30:52AM +0100, Alan Douglas wrote:
> > > These PM ops will enable/disable the optional PHYs if present.  The
> > > AXI link-down register in the host driver is now cleared in
> > > cdns_pci_map_bus since the link-down bit will be set if the PHY has
> > > been disabled.  It is not cleared when enabling the PHY, since the
> > > link will not yet be up.
> > 
> > It is not entirely clear what you mean here, can you elaborate please ?
> Thanks for taking a look at this.
> There is a "Link down indication bit" register in the cadence PCIe IP
> AXI Configuration  Registers, which will be set by the PCIe IP after
> each link- down occurrence.  This bit must be cleared before
> continuing, or accesses will hang.  When the PHY is disabled, the link
> will go down and this bit will be set by HW.  It will also be set
> after a secondary bus reset.
> 
> We cannot simply clear this bit when enabling the PHY, since at this
> stage the link may not come up (e.g. because the EP PHY is disabled),

I understand the approach and the reasoning, I still would like to
understand the use case that explains "because the EP PHY is disabled"
above and, related to the same question, why isn't this needed in
current driver version given that the host controller is probed out
of reset, I will apply the series then and update the commit log.

Lorenzo

> and so we need to clear it on the first access after link-up. In order
> to ensure this, I simply clear it on every config access, in
> cdns_pci_map_bus, I couldn't think of a good way to just do it once.
> 
> Regards,
> Alan
> > Thank you,
> > Lorenzo
> > 
> > > Signed-off-by: Alan Douglas <adouglas@cadence.com>
> > > ---
> > >  drivers/pci/controller/pcie-cadence-ep.c   |    1 +
> > >  drivers/pci/controller/pcie-cadence-host.c |    3 ++
> > >  drivers/pci/controller/pcie-cadence.c      |   30 ++++++++++++++++++++++++++++
> > >  drivers/pci/controller/pcie-cadence.h      |    4 +++
> > >  4 files changed, 38 insertions(+), 0 deletions(-)
> > >
> > > diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c
> > > index c02f33d..3eabd99 100644
> > > --- a/drivers/pci/controller/pcie-cadence-ep.c
> > > +++ b/drivers/pci/controller/pcie-cadence-ep.c
> > > @@ -555,6 +555,7 @@ static void cdns_pcie_ep_shutdown(struct platform_device *pdev)
> > >  	.driver = {
> > >  		.name = "cdns-pcie-ep",
> > >  		.of_match_table = cdns_pcie_ep_of_match,
> > > +		.pm	= &cdns_pcie_pm_ops,
> > >  	},
> > >  	.probe = cdns_pcie_ep_probe,
> > >  	.shutdown = cdns_pcie_ep_shutdown,
> > > diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c
> > > index 36f3109..e3e9b7d 100644
> > > --- a/drivers/pci/controller/pcie-cadence-host.c
> > > +++ b/drivers/pci/controller/pcie-cadence-host.c
> > > @@ -61,6 +61,8 @@ struct cdns_pcie_rc {
> > >  	/* Check that the link is up */
> > >  	if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1))
> > >  		return NULL;
> > > +	/* Clear AXI link-down status */
> > > +	cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0);
> > >
> > >  	/* Update Output registers for AXI region 0. */
> > >  	addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) |
> > > @@ -345,6 +347,7 @@ static int cdns_pcie_host_probe(struct platform_device *pdev)
> > >  	.driver = {
> > >  		.name = "cdns-pcie-host",
> > >  		.of_match_table = cdns_pcie_host_of_match,
> > > +		.pm	= &cdns_pcie_pm_ops,
> > >  	},
> > >  	.probe = cdns_pcie_host_probe,
> > >  };
> > > diff --git a/drivers/pci/controller/pcie-cadence.c b/drivers/pci/controller/pcie-cadence.c
> > > index 2edc126..86f1b00 100644
> > > --- a/drivers/pci/controller/pcie-cadence.c
> > > +++ b/drivers/pci/controller/pcie-cadence.c
> > > @@ -217,3 +217,33 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
> > >
> > >  	return ret;
> > >  }
> > > +
> > > +#ifdef CONFIG_PM_SLEEP
> > > +static int cdns_pcie_suspend_noirq(struct device *dev)
> > > +{
> > > +	struct cdns_pcie *pcie = dev_get_drvdata(dev);
> > > +
> > > +	cdns_pcie_disable_phy(pcie);
> > > +
> > > +	return 0;
> > > +}
> > > +
> > > +static int cdns_pcie_resume_noirq(struct device *dev)
> > > +{
> > > +	struct cdns_pcie *pcie = dev_get_drvdata(dev);
> > > +	int ret;
> > > +
> > > +	ret = cdns_pcie_enable_phy(pcie);
> > > +	if (ret) {
> > > +		dev_err(dev, "failed to enable phy\n");
> > > +		return ret;
> > > +	}
> > > +
> > > +	return 0;
> > > +}
> > > +#endif
> > > +
> > > +const struct dev_pm_ops cdns_pcie_pm_ops = {
> > > +	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq,
> > > +				      cdns_pcie_resume_noirq)
> > > +};
> > > diff --git a/drivers/pci/controller/pcie-cadence.h b/drivers/pci/controller/pcie-cadence.h
> > > index b342c80..ae6bf2a 100644
> > > --- a/drivers/pci/controller/pcie-cadence.h
> > > +++ b/drivers/pci/controller/pcie-cadence.h
> > > @@ -166,6 +166,9 @@
> > >  #define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \
> > >  	(CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008)
> > >
> > > +/* AXI link down register */
> > > +#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824)
> > > +
> > >  enum cdns_pcie_rp_bar {
> > >  	RP_BAR0,
> > >  	RP_BAR1,
> > > @@ -314,5 +317,6 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn,
> > >  void cdns_pcie_disable_phy(struct cdns_pcie *pcie);
> > >  int cdns_pcie_enable_phy(struct cdns_pcie *pcie);
> > >  int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie);
> > > +extern const struct dev_pm_ops cdns_pcie_pm_ops;
> > >
> > >  #endif /* _PCIE_CADENCE_H */
> > > --
> > > 1.7.1
> > >

RE: [PATCH 4/5] PCI: cadence: Add Power Management ops for host and EP

[Alan Douglas]

On 11 July 2018 11:58, Lorenzo Pieralisi wrote:
> On Mon, Jul 09, 2018 at 03:56:11PM +0000, Alan Douglas wrote:
> > On 09 July 2018 16:34, Lorenzo Pieralisi wrote:
> > > On Mon, Jun 25, 2018 at 09:30:52AM +0100, Alan Douglas wrote:
> > > > These PM ops will enable/disable the optional PHYs if present.  The
> > > > AXI link-down register in the host driver is now cleared in
> > > > cdns_pci_map_bus since the link-down bit will be set if the PHY has
> > > > been disabled.  It is not cleared when enabling the PHY, since the
> > > > link will not yet be up.
> > >
> > > It is not entirely clear what you mean here, can you elaborate please ?
> > Thanks for taking a look at this.
> > There is a "Link down indication bit" register in the cadence PCIe IP
> > AXI Configuration  Registers, which will be set by the PCIe IP after
> > each link- down occurrence.  This bit must be cleared before
> > continuing, or accesses will hang.  When the PHY is disabled, the link
> > will go down and this bit will be set by HW.  It will also be set
> > after a secondary bus reset.
> >
> > We cannot simply clear this bit when enabling the PHY, since at this
> > stage the link may not come up (e.g. because the EP PHY is disabled),
> 
> I understand the approach and the reasoning, I still would like to
> understand the use case that explains "because the EP PHY is disabled"
> above and, related to the same question, why isn't this needed in
> current driver version given that the host controller is probed out
> of reset, I will apply the series then and update the commit log.
> 
> Lorenzo
> 
Why isn't it needed with current?
The current driver version can only be used where there is no Linux PHY
required (e.g. in simulation or if the PHY was controlled in hardware
or firmware.)  Right now, I'm only aware of this driver being used in
simulation and the only use-case that will lead to link-down is a
secondary bus reset.  In this case, there is a recovery time, and the
PCIe HW can be configured to clear the link-down indication bit during
that time using a hardware timer.  If there is an implementation with the
PHY controlled by hardware or firmware, the link-down indication bit
should also be cleared external to the Linux driver.

Use-case?
The addition of PHY & PM ops to the driver allows it to be used for hw
where the PHY is not being managed externally.  There is a possible use 
case  where two cadence RP & EP are running in a back-to-back configuration,
and the  link will not be established until both PHY have been enabled.  At
first power-up this is fine, because the link will not have gone down, and
the link-down bit will not be set.  During suspend/resume, the RP and EP
will both power-down/up their respective PHYs, and so the link-down bit
will be set.  However, the EP will not power up its PHY until its resume is
called, and this may be after the RP.  This is what I mean by: 
"e.g. because the EP PHY is disabled", i.e. it's still disabled while resuming
the RP.

Thanks for asking about this, hope the explanation makes sense.  One thing
that I am now wondering about is the validity of powering down/up the EP
PHY when handling suspend/resume.

> > and so we need to clear it on the first access after link-up. In order
> > to ensure this, I simply clear it on every config access, in
> > cdns_pci_map_bus, I couldn't think of a good way to just do it once.
> >
> > Regards,
> > Alan
> > > Thank you,
> > > Lorenzo
> > >
> > > > Signed-off-by: Alan Douglas <adouglas@cadence.com>
> > > > ---
> > > >  drivers/pci/controller/pcie-cadence-ep.c   |    1 +
> > > >  drivers/pci/controller/pcie-cadence-host.c |    3 ++
> > > >  drivers/pci/controller/pcie-cadence.c      |   30 ++++++++++++++++++++++++++++
> > > >  drivers/pci/controller/pcie-cadence.h      |    4 +++
> > > >  4 files changed, 38 insertions(+), 0 deletions(-)
> > > >
> > > > diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c
> > > > index c02f33d..3eabd99 100644
> > > > --- a/drivers/pci/controller/pcie-cadence-ep.c
> > > > +++ b/drivers/pci/controller/pcie-cadence-ep.c
> > > > @@ -555,6 +555,7 @@ static void cdns_pcie_ep_shutdown(struct platform_device *pdev)
> > > >  	.driver = {
> > > >  		.name = "cdns-pcie-ep",
> > > >  		.of_match_table = cdns_pcie_ep_of_match,
> > > > +		.pm	= &cdns_pcie_pm_ops,
> > > >  	},
> > > >  	.probe = cdns_pcie_ep_probe,
> > > >  	.shutdown = cdns_pcie_ep_shutdown,
> > > > diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c
> > > > index 36f3109..e3e9b7d 100644
> > > > --- a/drivers/pci/controller/pcie-cadence-host.c
> > > > +++ b/drivers/pci/controller/pcie-cadence-host.c
> > > > @@ -61,6 +61,8 @@ struct cdns_pcie_rc {
> > > >  	/* Check that the link is up */
> > > >  	if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1))
> > > >  		return NULL;
> > > > +	/* Clear AXI link-down status */
> > > > +	cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0);
> > > >
> > > >  	/* Update Output registers for AXI region 0. */
> > > >  	addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) |
> > > > @@ -345,6 +347,7 @@ static int cdns_pcie_host_probe(struct platform_device *pdev)
> > > >  	.driver = {
> > > >  		.name = "cdns-pcie-host",
> > > >  		.of_match_table = cdns_pcie_host_of_match,
> > > > +		.pm	= &cdns_pcie_pm_ops,
> > > >  	},
> > > >  	.probe = cdns_pcie_host_probe,
> > > >  };
> > > > diff --git a/drivers/pci/controller/pcie-cadence.c b/drivers/pci/controller/pcie-cadence.c
> > > > index 2edc126..86f1b00 100644
> > > > --- a/drivers/pci/controller/pcie-cadence.c
> > > > +++ b/drivers/pci/controller/pcie-cadence.c
> > > > @@ -217,3 +217,33 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
> > > >
> > > >  	return ret;
> > > >  }
> > > > +
> > > > +#ifdef CONFIG_PM_SLEEP
> > > > +static int cdns_pcie_suspend_noirq(struct device *dev)
> > > > +{
> > > > +	struct cdns_pcie *pcie = dev_get_drvdata(dev);
> > > > +
> > > > +	cdns_pcie_disable_phy(pcie);
> > > > +
> > > > +	return 0;
> > > > +}
> > > > +
> > > > +static int cdns_pcie_resume_noirq(struct device *dev)
> > > > +{
> > > > +	struct cdns_pcie *pcie = dev_get_drvdata(dev);
> > > > +	int ret;
> > > > +
> > > > +	ret = cdns_pcie_enable_phy(pcie);
> > > > +	if (ret) {
> > > > +		dev_err(dev, "failed to enable phy\n");
> > > > +		return ret;
> > > > +	}
> > > > +
> > > > +	return 0;
> > > > +}
> > > > +#endif
> > > > +
> > > > +const struct dev_pm_ops cdns_pcie_pm_ops = {
> > > > +	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq,
> > > > +				      cdns_pcie_resume_noirq)
> > > > +};
> > > > diff --git a/drivers/pci/controller/pcie-cadence.h b/drivers/pci/controller/pcie-cadence.h
> > > > index b342c80..ae6bf2a 100644
> > > > --- a/drivers/pci/controller/pcie-cadence.h
> > > > +++ b/drivers/pci/controller/pcie-cadence.h
> > > > @@ -166,6 +166,9 @@
> > > >  #define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \
> > > >  	(CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008)
> > > >
> > > > +/* AXI link down register */
> > > > +#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824)
> > > > +
> > > >  enum cdns_pcie_rp_bar {
> > > >  	RP_BAR0,
> > > >  	RP_BAR1,
> > > > @@ -314,5 +317,6 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn,
> > > >  void cdns_pcie_disable_phy(struct cdns_pcie *pcie);
> > > >  int cdns_pcie_enable_phy(struct cdns_pcie *pcie);
> > > >  int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie);
> > > > +extern const struct dev_pm_ops cdns_pcie_pm_ops;
> > > >
> > > >  #endif /* _PCIE_CADENCE_H */
> > > > --
> > > > 1.7.1
> > > >

RE: [PATCH 4/5] PCI: cadence: Add Power Management ops for host and EP

[Alan Douglas]

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LjENCj4gPiA+ID4NCg==

[PATCH 5/5] PCI: cadence: Add shutdown callback to host driver

[Alan Douglas]

Add shutdown callback to host driver which will disable PHY and
PM runtime.

Signed-off-by: Alan Douglas <adouglas@cadence.com>
---
 drivers/pci/controller/pcie-cadence-host.c |   15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c
index e3e9b7d..ec394f6 100644
--- a/drivers/pci/controller/pcie-cadence-host.c
+++ b/drivers/pci/controller/pcie-cadence-host.c
@@ -343,6 +343,20 @@ static int cdns_pcie_host_probe(struct platform_device *pdev)
 	return ret;
 }
 
+static void cdns_pcie_shutdown(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct cdns_pcie *pcie = dev_get_drvdata(dev);
+	int ret;
+
+	ret = pm_runtime_put_sync(dev);
+	if (ret < 0)
+		dev_dbg(dev, "pm_runtime_put_sync failed\n");
+
+	pm_runtime_disable(dev);
+	cdns_pcie_disable_phy(pcie);
+}
+
 static struct platform_driver cdns_pcie_host_driver = {
 	.driver = {
 		.name = "cdns-pcie-host",
@@ -350,5 +364,6 @@ static int cdns_pcie_host_probe(struct platform_device *pdev)
 		.pm	= &cdns_pcie_pm_ops,
 	},
 	.probe = cdns_pcie_host_probe,
+	.shutdown = cdns_pcie_shutdown,
 };
 builtin_platform_driver(cdns_pcie_host_driver);
-- 
1.7.1

[PATCH 5/5] PCI: cadence: Add shutdown callback to host driver

[Alan Douglas]

Add shutdown callback to host driver which will disable PHY and
PM runtime.

Signed-off-by: Alan Douglas <adouglas@cadence.com>
---
 drivers/pci/controller/pcie-cadence-host.c |   15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c
index e3e9b7d..ec394f6 100644
--- a/drivers/pci/controller/pcie-cadence-host.c
+++ b/drivers/pci/controller/pcie-cadence-host.c
@@ -343,6 +343,20 @@ static int cdns_pcie_host_probe(struct platform_device *pdev)
 	return ret;
 }
 
+static void cdns_pcie_shutdown(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct cdns_pcie *pcie = dev_get_drvdata(dev);
+	int ret;
+
+	ret = pm_runtime_put_sync(dev);
+	if (ret < 0)
+		dev_dbg(dev, "pm_runtime_put_sync failed\n");
+
+	pm_runtime_disable(dev);
+	cdns_pcie_disable_phy(pcie);
+}
+
 static struct platform_driver cdns_pcie_host_driver = {
 	.driver = {
 		.name = "cdns-pcie-host",
@@ -350,5 +364,6 @@ static int cdns_pcie_host_probe(struct platform_device *pdev)
 		.pm	= &cdns_pcie_pm_ops,
 	},
 	.probe = cdns_pcie_host_probe,
+	.shutdown = cdns_pcie_shutdown,
 };
 builtin_platform_driver(cdns_pcie_host_driver);
-- 
1.7.1

Re: [PATCH 0/5] PCI: cadence: Host and EP driver updates for PHY and power management

[Lorenzo Pieralisi]

On Mon, Jun 25, 2018 at 09:30:48AM +0100, Alan Douglas wrote:
> This is a series of patches for the cadence PCIe host and EP drivers, to:
>  - Add optional list of generic PHYs to host and EP drivers
>  - Add PHY bindings to devicetree
>  - Add Power Management ops, which will enable/disable PHYs if present
>  - Add shutdown handler to host driver
>  - Update cdns_pcie_writel function signature
> 
> Changes in v3:
> 	Use devm_phy_optional_get() to get optional PHY
> 	Updated decription in DT bindings to cover use of single/multiple PHYs
> 	Split patch to add shutdown callback in separate patch
> 	Re-based on v4.18-rc1
> 
> Changes in v2:
> 	Split commit into four patches
> 	Re-based on v4.17-rc1
> 
> Alan Douglas (5):
>   PCI: cadence: Update cdns_pcie_writel function signature
>   PCI: cadence: Add generic PHY support to host and EP drivers
>   dt-bindings: PCI: cadence: Add DT bindings for optional PHYs
>   PCI: cadence: Add Power Management ops for host and EP
>   PCI: cadence: Add shutdown callback to host driver
> 
>  .../devicetree/bindings/pci/cdns,cdns-pcie-ep.txt  |    5 +
>  .../bindings/pci/cdns,cdns-pcie-host.txt           |    6 +
>  drivers/pci/controller/pcie-cadence-ep.c           |   15 +++-
>  drivers/pci/controller/pcie-cadence-host.c         |   33 +++++
>  drivers/pci/controller/pcie-cadence.c              |  123 ++++++++++++++++++++
>  drivers/pci/controller/pcie-cadence.h              |   13 ++-
>  6 files changed, 193 insertions(+), 2 deletions(-)

Applied to pci/cadence for v4.19, thank you very much.

Lorenzo
>