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From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL v2 8/9] target/mips: Fix data type for offset
Date: Wed, 27 Jun 2018 20:29:08 +0200	[thread overview]
Message-ID: <1530124149-3900-9-git-send-email-aleksandar.markovic@rt-rk.com> (raw)
In-Reply-To: <1530124149-3900-1-git-send-email-aleksandar.markovic@rt-rk.com>

From: Yongbok Kim <yongbok.kim@mips.com>

Offset can be larger than 16 bit from nanoMIPS,
and immediate field can be larger than 16 bits as well.

Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aleksandar Markovic <aleksandar.markovic@mips.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@mips.com>
---
 target/mips/translate.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index e923d27..20b43c0 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2112,7 +2112,7 @@ OP_ST_ATOMIC(scd,st64,ld64,0x7);
 #undef OP_ST_ATOMIC
 
 static void gen_base_offset_addr (DisasContext *ctx, TCGv addr,
-                                  int base, int16_t offset)
+                                  int base, int offset)
 {
     if (base == 0) {
         tcg_gen_movi_tl(addr, offset);
@@ -2140,7 +2140,7 @@ static target_ulong pc_relative_pc (DisasContext *ctx)
 
 /* Load */
 static void gen_ld(DisasContext *ctx, uint32_t opc,
-                   int rt, int base, int16_t offset)
+                   int rt, int base, int offset)
 {
     TCGv t0, t1, t2;
     int mem_idx = ctx->mem_idx;
@@ -2337,7 +2337,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
 
 /* Store */
 static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
-                    int base, int16_t offset)
+                    int base, int offset)
 {
     TCGv t0 = tcg_temp_new();
     TCGv t1 = tcg_temp_new();
@@ -2505,7 +2505,7 @@ static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt,
 
 /* Arithmetic with immediate operand */
 static void gen_arith_imm(DisasContext *ctx, uint32_t opc,
-                          int rt, int rs, int16_t imm)
+                          int rt, int rs, int imm)
 {
     target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
 
-- 
2.7.4

  parent reply	other threads:[~2018-06-27 18:29 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-27 18:29 [Qemu-devel] [PULL v2 0/9] MIPS queue 2018-06-27 Aleksandar Markovic
2018-06-27 18:29 ` [Qemu-devel] [PULL v2 1/9] MAINTAINERS: update target-mips maintainers Aleksandar Markovic
2018-06-27 18:29 ` [Qemu-devel] [PULL v2 2/9] hw/mips/boston: don't make flash region 'nomigrate' Aleksandar Markovic
2018-06-27 18:29 ` [Qemu-devel] [PULL v2 3/9] hw/mips/mips_malta: don't make bios " Aleksandar Markovic
2018-06-27 18:29 ` [Qemu-devel] [PULL v2 4/9] hw/pci-host/xilinx-pcie: don't make "io" region be RAM Aleksandar Markovic
2018-06-27 18:29 ` [Qemu-devel] [PULL v2 5/9] target/mips: Raise a RI when given fs is n/a from CTC1 Aleksandar Markovic
2018-06-27 18:29 ` [Qemu-devel] [PULL v2 6/9] target/mips: Fix microMIPS on reset Aleksandar Markovic
2018-06-27 18:29 ` [Qemu-devel] [PULL v2 7/9] target/mips: Update gen_flt_ldst() Aleksandar Markovic
2018-06-27 18:29 ` Aleksandar Markovic [this message]
2018-06-27 18:29 ` [Qemu-devel] [PULL v2 9/9] target/mips: Fix gdbstub to read/write 64 bit FP registers Aleksandar Markovic
2018-06-28 14:30 ` [Qemu-devel] [PULL v2 0/9] MIPS queue 2018-06-27 Peter Maydell

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