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From: Madhav Chauhan <madhav.chauhan@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com, paulo.r.zanoni@intel.com, rodrigo.vivi@intel.com
Subject: [PATCH v4 11/20] drm/i915/icl: Define T_INIT_MASTER registers
Date: Thu,  5 Jul 2018 19:19:42 +0530	[thread overview]
Message-ID: <1530798591-2077-12-git-send-email-madhav.chauhan@intel.com> (raw)
In-Reply-To: <1530798591-2077-1-git-send-email-madhav.chauhan@intel.com>

This patch defines DSI_T_INIT_MASTER register for DSI ports
0/1 which will be used in dphy programming.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f84e7ff..4be18e9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10053,6 +10053,12 @@ enum skl_power_gate {
 #define  PREPARE_COUNT_SHIFT				0
 #define  PREPARE_COUNT_MASK				(0x3f << 0)
 
+#define _ICL_DSI_T_INIT_MASTER_0	0x6b088
+#define _ICL_DSI_T_INIT_MASTER_1	0x6b888
+#define ICL_DSI_T_INIT_MASTER(port)	_MMIO_PORT(port,	\
+						   _ICL_DSI_T_INIT_MASTER_0,\
+						   _ICL_DSI_T_INIT_MASTER_1)
+
 /* bits 31:0 */
 #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
 #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
-- 
2.7.4

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  parent reply	other threads:[~2018-07-05 13:59 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-05 13:49 [PATCH v4 00/20] ICELAKE DSI DRIVER Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 01/20] drm/i915/icl: Define register for DSI PLL Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 02/20] drm/i915/icl: Program DSI Escape clock Divider Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 03/20] drm/i915/icl: Define DSI mode ctl register Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 04/20] drm/i915/icl: Enable DSI IO power Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 05/20] drm/i915/icl: Define PORT_CL_DW_10 register Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 06/20] drm/i915/icl: Power down unused DSI lanes Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 07/20] drm/i915/icl: Define AUX lane registers for Port A/B Madhav Chauhan
2018-07-06  9:16   ` Jani Nikula
2018-07-05 13:49 ` [PATCH v4 08/20] drm/i915/icl: Configure lane sequencing of combo phy transmitter Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 09/20] drm/i915/icl: DSI vswing programming sequence Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 10/20] drm/i915/icl: Enable DDI Buffer Madhav Chauhan
2018-07-05 13:49 ` Madhav Chauhan [this message]
2018-07-05 13:49 ` [PATCH v4 12/20] drm/i915/icl: Program T_INIT_MASTER registers Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 13/20] drm/i915/icl: Define data/clock lanes dphy timing registers Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 14/20] drm/i915/icl: Program DSI clock and data lane timing params Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 15/20] drm/i915/icl: Define TA_TIMING_PARAM registers Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 16/20] drm/i915/icl: Program " Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 17/20] drm/i915/icl: Get DSI transcoder for a given port Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 18/20] drm/i915/icl: Add macros for MMIO of DSI transcoder registers Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 19/20] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 20/20] drm/i915/icl: Configure DSI transcoders Madhav Chauhan
2018-07-05 14:58 ` ✗ Fi.CI.CHECKPATCH: warning for ICELAKE DSI DRIVER (rev4) Patchwork
2018-07-05 15:05 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-07-05 15:20 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-07-05 20:30 ` ✓ Fi.CI.BAT: success " Patchwork
2018-07-06  8:10 ` Patchwork
2018-07-06  8:14 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-07-06 22:22 ` ✓ Fi.CI.IGT: success " Patchwork

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