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From: Madhav Chauhan <madhav.chauhan@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com, paulo.r.zanoni@intel.com, rodrigo.vivi@intel.com
Subject: [PATCH v4 04/20] drm/i915/icl: Enable DSI IO power
Date: Thu,  5 Jul 2018 19:19:35 +0530	[thread overview]
Message-ID: <1530798591-2077-5-git-send-email-madhav.chauhan@intel.com> (raw)
In-Reply-To: <1530798591-2077-1-git-send-email-madhav.chauhan@intel.com>

This patch configures mode of operation for DSI
and enable DDI IO power by configuring power well.

v2: Use for_each_dsi_port() for power get (Jani N)

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index a890b36..64f97c7 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -54,11 +54,34 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
 	}
 }
 
+static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
+	u32 tmp;
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(ICL_DSI_IO_MODECTL(port));
+		tmp |= COMBO_PHY_MODE_DSI;
+		I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp);
+	}
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+		intel_display_power_get(dev_priv, port == PORT_A ?
+					POWER_DOMAIN_PORT_DDI_A_IO :
+					POWER_DOMAIN_PORT_DDI_B_IO);
+	}
+}
+
 static void __attribute__((unused))
 gen11_dsi_pre_enable(struct intel_encoder *encoder,
 		const struct intel_crtc_state *pipe_config,
 		const struct drm_connector_state *conn_state)
 {
+	/* step2: enable IO power */
+	gen11_dsi_enable_io_power(encoder);
+
 	/* step3: enable DSI PLL */
 	gen11_dsi_program_esc_clk_div(encoder);
 }
-- 
2.7.4

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  parent reply	other threads:[~2018-07-05 13:59 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-05 13:49 [PATCH v4 00/20] ICELAKE DSI DRIVER Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 01/20] drm/i915/icl: Define register for DSI PLL Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 02/20] drm/i915/icl: Program DSI Escape clock Divider Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 03/20] drm/i915/icl: Define DSI mode ctl register Madhav Chauhan
2018-07-05 13:49 ` Madhav Chauhan [this message]
2018-07-05 13:49 ` [PATCH v4 05/20] drm/i915/icl: Define PORT_CL_DW_10 register Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 06/20] drm/i915/icl: Power down unused DSI lanes Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 07/20] drm/i915/icl: Define AUX lane registers for Port A/B Madhav Chauhan
2018-07-06  9:16   ` Jani Nikula
2018-07-05 13:49 ` [PATCH v4 08/20] drm/i915/icl: Configure lane sequencing of combo phy transmitter Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 09/20] drm/i915/icl: DSI vswing programming sequence Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 10/20] drm/i915/icl: Enable DDI Buffer Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 11/20] drm/i915/icl: Define T_INIT_MASTER registers Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 12/20] drm/i915/icl: Program " Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 13/20] drm/i915/icl: Define data/clock lanes dphy timing registers Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 14/20] drm/i915/icl: Program DSI clock and data lane timing params Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 15/20] drm/i915/icl: Define TA_TIMING_PARAM registers Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 16/20] drm/i915/icl: Program " Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 17/20] drm/i915/icl: Get DSI transcoder for a given port Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 18/20] drm/i915/icl: Add macros for MMIO of DSI transcoder registers Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 19/20] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 20/20] drm/i915/icl: Configure DSI transcoders Madhav Chauhan
2018-07-05 14:58 ` ✗ Fi.CI.CHECKPATCH: warning for ICELAKE DSI DRIVER (rev4) Patchwork
2018-07-05 15:05 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-07-05 15:20 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-07-05 20:30 ` ✓ Fi.CI.BAT: success " Patchwork
2018-07-06  8:10 ` Patchwork
2018-07-06  8:14 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-07-06 22:22 ` ✓ Fi.CI.IGT: success " Patchwork

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