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From: Patchwork <patchwork@emeril.freedesktop.org>
To: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.CHECKPATCH: warning for ICELAKE DSI DRIVER (rev4)
Date: Thu, 05 Jul 2018 14:58:38 -0000	[thread overview]
Message-ID: <20180705145838.21738.85576@emeril.freedesktop.org> (raw)
In-Reply-To: <1530798591-2077-1-git-send-email-madhav.chauhan@intel.com>

== Series Details ==

Series: ICELAKE DSI DRIVER (rev4)
URL   : https://patchwork.freedesktop.org/series/44823/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
7965105a9368 drm/i915/icl: Program DSI Escape clock Divider
-:40: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#40: 
new file mode 100644

-:45: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#45: FILE: drivers/gpu/drm/i915/icl_dsi.c:1:
+/*

-:90: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#90: FILE: drivers/gpu/drm/i915/icl_dsi.c:46:
+		I915_WRITE(ICL_DSI_ESC_CLK_DIV(port),
+				esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);

-:96: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#96: FILE: drivers/gpu/drm/i915/icl_dsi.c:52:
+		I915_WRITE(ICL_DPHY_ESC_CLK_DIV(port),
+				esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);

-:103: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#103: FILE: drivers/gpu/drm/i915/icl_dsi.c:59:
+gen11_dsi_pre_enable(struct intel_encoder *encoder,
+		const struct intel_crtc_state *pipe_config,

total: 0 errors, 2 warnings, 3 checks, 78 lines checked
a6e4a07d66c3 drm/i915/icl: Define DSI mode ctl register
36690b677bdd drm/i915/icl: Enable DSI IO power
7bd13a360006 drm/i915/icl: Define PORT_CL_DW_10 register
6d7f00fc0f04 drm/i915/icl: Power down unused DSI lanes
bdec4dbb3075 drm/i915/icl: Define AUX lane registers for Port A/B
32ff7be15d67 drm/i915/icl: Configure lane sequencing of combo phy transmitter
10feaa6d3bb1 drm/i915/icl: DSI vswing programming sequence
-:33: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#33: FILE: drivers/gpu/drm/i915/icl_dsi.c:39:
+	for_each_dsi_port(port, intel_dsi->ports) {
+

total: 0 errors, 0 warnings, 1 checks, 132 lines checked
0a8df2a0c203 drm/i915/icl: Enable DDI Buffer
ba86db32cf89 drm/i915/icl: Define T_INIT_MASTER registers
ec7825ca4e71 drm/i915/icl: Program T_INIT_MASTER registers
afa8eaff75ed drm/i915/icl: Define data/clock lanes dphy timing registers
-:31: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#31: FILE: drivers/gpu/drm/i915/i915_reg.h:10089:
+#define  CLK_PREP_TIME(x)		(x << 28)

-:33: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#33: FILE: drivers/gpu/drm/i915/i915_reg.h:10091:
+#define  CLK_ZERO_TIME(x)		(x << 20)

-:35: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#35: FILE: drivers/gpu/drm/i915/i915_reg.h:10093:
+#define  CLK_PRE_TIME(x)		(x << 16)

-:37: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#37: FILE: drivers/gpu/drm/i915/i915_reg.h:10095:
+#define  CLK_POST_TIME(x)		(x << 8)

-:39: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#39: FILE: drivers/gpu/drm/i915/i915_reg.h:10097:
+#define  CLK_TRAIL_TIME(x)		(x << 0)

-:52: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#52: FILE: drivers/gpu/drm/i915/i915_reg.h:10110:
+#define  HS_PREP_TIME(x)		(x << 24)

-:54: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#54: FILE: drivers/gpu/drm/i915/i915_reg.h:10112:
+#define  HS_ZERO_TIME(x)		(x << 16)

-:56: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#56: FILE: drivers/gpu/drm/i915/i915_reg.h:10114:
+#define  HS_TRAIL_TIME(x)		(x << 8)

-:58: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#58: FILE: drivers/gpu/drm/i915/i915_reg.h:10116:
+#define  HS_EXIT_TIME(x)		(x << 0)

total: 0 errors, 0 warnings, 9 checks, 46 lines checked
199a130bdf5d drm/i915/icl: Program DSI clock and data lane timing params
-:80: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#80: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:631:
+	ths_prepare_ns = max(mipi_config->ths_prepare,
+				mipi_config->tclk_prepare);

-:114: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#114: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:655:
+		clk_zero_cnt = DIV_ROUND_UP(

-:128: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#128: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:669:
+		hs_zero_cnt = DIV_ROUND_UP(

-:190: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#190: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:727:
+		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den,
+							ui_num * mul);

-:196: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#196: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:731:
+			DRM_DEBUG_KMS("prepare count too high %u\n",
+								prepare_cnt);

-:201: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#201: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:736:
+		exit_zero_cnt = DIV_ROUND_UP(

-:226: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#226: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:748:
+		if (exit_zero_cnt < (55 * ui_den / ui_num) &&
+					(55 * ui_den) % ui_num)

-:231: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#231: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:753:
+			DRM_DEBUG_KMS("exit zero count too high %u\n",
+								exit_zero_cnt);

-:250: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#250: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:764:
+			DRM_DEBUG_KMS("clock zero count too high %u\n",
+								clk_zero_cnt);

total: 0 errors, 0 warnings, 9 checks, 293 lines checked
acc05e07764f drm/i915/icl: Define TA_TIMING_PARAM registers
-:31: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#31: FILE: drivers/gpu/drm/i915/i915_reg.h:10129:
+#define  TA_SURE_TIME(x)		(x << 16)

total: 0 errors, 0 warnings, 1 checks, 20 lines checked
2254cce6d683 drm/i915/icl: Program TA_TIMING_PARAM registers
b80a1ca80195 drm/i915/icl: Get DSI transcoder for a given port
-:20: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#20: FILE: drivers/gpu/drm/i915/icl_dsi.c:30:
+static enum transcoder __attribute__((unused)) dsi_port_to_transcoder(

total: 0 errors, 0 warnings, 1 checks, 27 lines checked
228524abf4ca drm/i915/icl: Add macros for MMIO of DSI transcoder registers
4282ae8762fb drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
-:26: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#26: FILE: drivers/gpu/drm/i915/i915_reg.h:10143:
+#define  OP_MODE(x)			(x << 28)

-:33: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#33: FILE: drivers/gpu/drm/i915/i915_reg.h:10150:
+#define  PIX_FMT(x)			(x << 16)

-:43: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#43: FILE: drivers/gpu/drm/i915/i915_reg.h:10160:
+#define  PIX_VIRT_CHAN(x)		(x << 12)

-:45: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#45: FILE: drivers/gpu/drm/i915/i915_reg.h:10162:
+#define  PIX_BUF_THRESHOLD(x)		((x & 0x3) << 10)

-:51: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#51: FILE: drivers/gpu/drm/i915/i915_reg.h:10168:
+#define  CONTINUOUS_CLK(x)		(x << 8)

-:56: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#56: FILE: drivers/gpu/drm/i915/i915_reg.h:10173:
+#define  LINK_CALIBRATION(x)		(x << 4)

-:61: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#61: FILE: drivers/gpu/drm/i915/i915_reg.h:10178:
+#define  S3D_ORIENTATION(x)		(x << 1)

total: 0 errors, 0 warnings, 7 checks, 53 lines checked
886bad0af462 drm/i915/icl: Configure DSI transcoders
-:54: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#54: FILE: drivers/gpu/drm/i915/icl_dsi.c:356:
+			tmp |= LINK_CALIBRATION(

total: 0 errors, 0 warnings, 1 checks, 121 lines checked

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  parent reply	other threads:[~2018-07-05 14:58 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-05 13:49 [PATCH v4 00/20] ICELAKE DSI DRIVER Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 01/20] drm/i915/icl: Define register for DSI PLL Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 02/20] drm/i915/icl: Program DSI Escape clock Divider Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 03/20] drm/i915/icl: Define DSI mode ctl register Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 04/20] drm/i915/icl: Enable DSI IO power Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 05/20] drm/i915/icl: Define PORT_CL_DW_10 register Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 06/20] drm/i915/icl: Power down unused DSI lanes Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 07/20] drm/i915/icl: Define AUX lane registers for Port A/B Madhav Chauhan
2018-07-06  9:16   ` Jani Nikula
2018-07-05 13:49 ` [PATCH v4 08/20] drm/i915/icl: Configure lane sequencing of combo phy transmitter Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 09/20] drm/i915/icl: DSI vswing programming sequence Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 10/20] drm/i915/icl: Enable DDI Buffer Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 11/20] drm/i915/icl: Define T_INIT_MASTER registers Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 12/20] drm/i915/icl: Program " Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 13/20] drm/i915/icl: Define data/clock lanes dphy timing registers Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 14/20] drm/i915/icl: Program DSI clock and data lane timing params Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 15/20] drm/i915/icl: Define TA_TIMING_PARAM registers Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 16/20] drm/i915/icl: Program " Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 17/20] drm/i915/icl: Get DSI transcoder for a given port Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 18/20] drm/i915/icl: Add macros for MMIO of DSI transcoder registers Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 19/20] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register Madhav Chauhan
2018-07-05 13:49 ` [PATCH v4 20/20] drm/i915/icl: Configure DSI transcoders Madhav Chauhan
2018-07-05 14:58 ` Patchwork [this message]
2018-07-05 15:05 ` ✗ Fi.CI.SPARSE: warning for ICELAKE DSI DRIVER (rev4) Patchwork
2018-07-05 15:20 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-07-05 20:30 ` ✓ Fi.CI.BAT: success " Patchwork
2018-07-06  8:10 ` Patchwork
2018-07-06  8:14 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-07-06 22:22 ` ✓ Fi.CI.IGT: success " Patchwork

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