From: Stu Hsieh <stu.hsieh@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>, Philipp Zabel <p.zabel@pengutronix.de>
Cc: David Airlie <airlied@linux.ie>,
Matthias Brugger <matthias.bgg@gmail.com>,
<dri-devel@lists.freedesktop.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <srv_heupstream@mediatek.com>,
Stu Hsieh <stu.hsieh@mediatek.com>
Subject: [PATCH v1 06/15] drm/mediatek: add memory mode for RDMA
Date: Tue, 24 Jul 2018 16:17:06 +0800 [thread overview]
Message-ID: <1532420235-22268-7-git-send-email-stu.hsieh@mediatek.com> (raw)
In-Reply-To: <1532420235-22268-1-git-send-email-stu.hsieh@mediatek.com>
This patch add memory mode for RDMA
If use RDMA to read data from memory, it should set memory mode to RDMA
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 60851bb2dd63..78a1a0057aff 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -31,6 +31,8 @@
#define RDMA_REG_UPDATE_INT BIT(0)
#define DISP_REG_RDMA_GLOBAL_CON 0x0010
#define RDMA_ENGINE_EN BIT(0)
+#define RDMA_SOFT_RESET BIT(4)
+#define RDMA_MODE_MEMORY BIT(1)
#define DISP_REG_RDMA_SIZE_CON_0 0x0014
#define DISP_REG_RDMA_SIZE_CON_1 0x0018
#define DISP_REG_RDMA_TARGET_LINE 0x001c
@@ -40,6 +42,8 @@
#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16)
#define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size)
+#define MATRIX_INT_MTX_SEL_DEFAULT 0xb00000
+
struct mtk_disp_rdma_data {
unsigned int fifo_size;
};
@@ -53,6 +57,7 @@ struct mtk_disp_rdma {
struct mtk_ddp_comp ddp_comp;
struct drm_crtc *crtc;
const struct mtk_disp_rdma_data *data;
+ bool rdma_memory_mode;
};
static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp)
@@ -111,7 +116,8 @@ static void mtk_rdma_start(struct mtk_ddp_comp *comp)
static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
{
- rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0);
+ writel(RDMA_SOFT_RESET, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
+ writel(0, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
}
static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
@@ -121,10 +127,18 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
unsigned int threshold;
unsigned int reg;
struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
+ bool *rdma_memory_mode = comp->comp_mode;
rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);
rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);
+ if (*rdma_memory_mode == true) {
+ rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xff0000,
+ MATRIX_INT_MTX_SEL_DEFAULT);
+ rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON,
+ RDMA_MODE_MEMORY, RDMA_MODE_MEMORY);
+ }
+
/*
* Enable FIFO underflow since DSI and DPI can't be blocked.
* Keep the FIFO pseudo size reset default of 8 KiB. Set the
--
2.12.5
WARNING: multiple messages have this Message-ID (diff)
From: Stu Hsieh <stu.hsieh@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>, Philipp Zabel <p.zabel@pengutronix.de>
Cc: srv_heupstream@mediatek.com, David Airlie <airlied@linux.ie>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
linux-mediatek@lists.infradead.org,
Stu Hsieh <stu.hsieh@mediatek.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v1 06/15] drm/mediatek: add memory mode for RDMA
Date: Tue, 24 Jul 2018 16:17:06 +0800 [thread overview]
Message-ID: <1532420235-22268-7-git-send-email-stu.hsieh@mediatek.com> (raw)
In-Reply-To: <1532420235-22268-1-git-send-email-stu.hsieh@mediatek.com>
This patch add memory mode for RDMA
If use RDMA to read data from memory, it should set memory mode to RDMA
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 60851bb2dd63..78a1a0057aff 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -31,6 +31,8 @@
#define RDMA_REG_UPDATE_INT BIT(0)
#define DISP_REG_RDMA_GLOBAL_CON 0x0010
#define RDMA_ENGINE_EN BIT(0)
+#define RDMA_SOFT_RESET BIT(4)
+#define RDMA_MODE_MEMORY BIT(1)
#define DISP_REG_RDMA_SIZE_CON_0 0x0014
#define DISP_REG_RDMA_SIZE_CON_1 0x0018
#define DISP_REG_RDMA_TARGET_LINE 0x001c
@@ -40,6 +42,8 @@
#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16)
#define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size)
+#define MATRIX_INT_MTX_SEL_DEFAULT 0xb00000
+
struct mtk_disp_rdma_data {
unsigned int fifo_size;
};
@@ -53,6 +57,7 @@ struct mtk_disp_rdma {
struct mtk_ddp_comp ddp_comp;
struct drm_crtc *crtc;
const struct mtk_disp_rdma_data *data;
+ bool rdma_memory_mode;
};
static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp)
@@ -111,7 +116,8 @@ static void mtk_rdma_start(struct mtk_ddp_comp *comp)
static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
{
- rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0);
+ writel(RDMA_SOFT_RESET, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
+ writel(0, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
}
static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
@@ -121,10 +127,18 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
unsigned int threshold;
unsigned int reg;
struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
+ bool *rdma_memory_mode = comp->comp_mode;
rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);
rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);
+ if (*rdma_memory_mode == true) {
+ rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xff0000,
+ MATRIX_INT_MTX_SEL_DEFAULT);
+ rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON,
+ RDMA_MODE_MEMORY, RDMA_MODE_MEMORY);
+ }
+
/*
* Enable FIFO underflow since DSI and DPI can't be blocked.
* Keep the FIFO pseudo size reset default of 8 KiB. Set the
--
2.12.5
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: stu.hsieh@mediatek.com (Stu Hsieh)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v1 06/15] drm/mediatek: add memory mode for RDMA
Date: Tue, 24 Jul 2018 16:17:06 +0800 [thread overview]
Message-ID: <1532420235-22268-7-git-send-email-stu.hsieh@mediatek.com> (raw)
In-Reply-To: <1532420235-22268-1-git-send-email-stu.hsieh@mediatek.com>
This patch add memory mode for RDMA
If use RDMA to read data from memory, it should set memory mode to RDMA
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 60851bb2dd63..78a1a0057aff 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -31,6 +31,8 @@
#define RDMA_REG_UPDATE_INT BIT(0)
#define DISP_REG_RDMA_GLOBAL_CON 0x0010
#define RDMA_ENGINE_EN BIT(0)
+#define RDMA_SOFT_RESET BIT(4)
+#define RDMA_MODE_MEMORY BIT(1)
#define DISP_REG_RDMA_SIZE_CON_0 0x0014
#define DISP_REG_RDMA_SIZE_CON_1 0x0018
#define DISP_REG_RDMA_TARGET_LINE 0x001c
@@ -40,6 +42,8 @@
#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16)
#define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size)
+#define MATRIX_INT_MTX_SEL_DEFAULT 0xb00000
+
struct mtk_disp_rdma_data {
unsigned int fifo_size;
};
@@ -53,6 +57,7 @@ struct mtk_disp_rdma {
struct mtk_ddp_comp ddp_comp;
struct drm_crtc *crtc;
const struct mtk_disp_rdma_data *data;
+ bool rdma_memory_mode;
};
static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp)
@@ -111,7 +116,8 @@ static void mtk_rdma_start(struct mtk_ddp_comp *comp)
static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
{
- rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0);
+ writel(RDMA_SOFT_RESET, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
+ writel(0, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
}
static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
@@ -121,10 +127,18 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
unsigned int threshold;
unsigned int reg;
struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
+ bool *rdma_memory_mode = comp->comp_mode;
rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);
rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);
+ if (*rdma_memory_mode == true) {
+ rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xff0000,
+ MATRIX_INT_MTX_SEL_DEFAULT);
+ rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON,
+ RDMA_MODE_MEMORY, RDMA_MODE_MEMORY);
+ }
+
/*
* Enable FIFO underflow since DSI and DPI can't be blocked.
* Keep the FIFO pseudo size reset default of 8 KiB. Set the
--
2.12.5
next prev parent reply other threads:[~2018-07-24 8:18 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-24 8:17 [PATCH v1 00/15] Add RDMA memory mode support for mediatek SOC MT2712 Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` [PATCH v1 01/15] drm/mediatek: add connection from RDMA0 to DPI1 Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` [PATCH v1 02/15] drm/mediatek: add connection from RDMA0 to DSI1 Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` [PATCH v1 03/15] drm/mediatek: add connection from RDMA1 to DSI0 Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` [PATCH v1 04/15] drm/mediatek: add connection from RDMA2 " Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` [PATCH v1 05/15] drm/mediatek: add RDMA memory mode for crtc created Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh [this message]
2018-07-24 8:17 ` [PATCH v1 06/15] drm/mediatek: add memory mode for RDMA Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-25 2:40 ` CK Hu
2018-07-25 2:40 ` CK Hu
2018-07-25 2:40 ` CK Hu
2018-08-02 11:36 ` Stu Hsieh
2018-08-02 11:36 ` Stu Hsieh
2018-08-02 11:36 ` Stu Hsieh
2018-08-03 7:30 ` CK Hu
2018-08-03 7:30 ` CK Hu
2018-08-03 7:30 ` CK Hu
2018-07-24 8:17 ` [PATCH v1 07/15] drm/mediatek: add layer config to set RDMA for plane setting Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` [PATCH v1 08/15] drm/mediatek: add RGB color format support for RDMA Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` [PATCH v1 09/15] drm/mediatek: add YUYV/UYVY " Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` [PATCH v1 10/15] drm/mediatek: add drm_device in RDMA for mamory mode to reaquest buffer Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` [PATCH v1 11/15] drm/mediatek: add dummy buffer for RDMA memory mode Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-25 5:42 ` CK Hu
2018-07-25 5:42 ` CK Hu
2018-07-25 5:42 ` CK Hu
2018-08-02 11:45 ` Stu Hsieh
2018-08-02 11:45 ` Stu Hsieh
2018-08-02 11:45 ` Stu Hsieh
2018-07-24 8:17 ` [PATCH v1 12/15] drm/mediatek: add layer number condition for RDMA to control plane Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-25 3:02 ` CK Hu
2018-07-25 3:02 ` CK Hu
2018-07-25 3:02 ` CK Hu
2018-08-02 11:38 ` Stu Hsieh
2018-08-02 11:38 ` Stu Hsieh
2018-08-02 11:38 ` Stu Hsieh
2018-07-24 8:17 ` [PATCH v1 13/15] drm/mediatek: Update some variable name from ovl to comp Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` [PATCH v1 14/15] drm/mediatek: fixed the error value for add DSI1 in mutex Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-25 5:10 ` CK Hu
2018-07-25 5:10 ` CK Hu
2018-07-25 5:10 ` CK Hu
2018-08-02 11:39 ` Stu Hsieh
2018-08-02 11:39 ` Stu Hsieh
2018-08-02 11:39 ` Stu Hsieh
2018-07-24 8:17 ` [PATCH v1 15/15] drm/mediatek: fixed connection from RDMA2 to DSI1 Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-24 8:17 ` Stu Hsieh
2018-07-25 1:39 ` [PATCH v1 00/15] Add RDMA memory mode support for mediatek SOC MT2712 CK Hu
2018-07-25 1:39 ` CK Hu
2018-07-25 1:39 ` CK Hu
2018-08-02 11:29 ` Stu Hsieh
2018-08-02 11:29 ` Stu Hsieh
2018-08-02 11:29 ` Stu Hsieh
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