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From: Jacopo Mondi <jacopo+renesas@jmondi.org>
To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
	David Airlie <airlied@linux.ie>
Cc: Jacopo Mondi <jacopo+renesas@jmondi.org>,
	ulrich.hecht+renesas@gmail.com, kieran.bingham@ideasonboard.com,
	dri-devel@lists.freedesktop.org (open list:DRM DRIVERS FOR
	RENESAS),
	linux-renesas-soc@vger.kernel.org (open list:DRM DRIVERS FOR
	RENESAS)
Subject: [PATCH 3/4] drm: rcar-du: Fix handling of DORCR for group 1
Date: Thu, 23 Aug 2018 17:12:13 +0200	[thread overview]
Message-ID: <1535037134-373-4-git-send-email-jacopo+renesas@jmondi.org> (raw)
In-Reply-To: <1535037134-373-1-git-send-email-jacopo+renesas@jmondi.org>

According to revision 1.00 of R-Car Gen3 Soc manual, only DU channels of
group 0 (DU0 and DU1) supports output control routing through register DORCR0.

For channels of group 1 (DU2 and DU3) which are only present on H3/M3-W/M3-N
SoCs, no routing options are available between super-imposition processors
and the output pin controller. The updated version of the SoC manual
prescribes thus to hardcode DPRCR2 bits that controls output pin routing for
those channels.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
 drivers/gpu/drm/rcar-du/rcar_du_group.c | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c
index ef2c177..e79d424 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
@@ -127,10 +127,19 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp)
 		rcar_du_group_write(rgrp, DEFR10, DEFR10_CODE | DEFR10_DEFE10);
 
 	/*
-	 * Use DS1PR and DS2PR to configure planes priorities and connects the
-	 * superposition 0 to DU0 pins. DU1 pins will be configured dynamically.
+	 * For group 0 (DU0/DU1) use DS1PR and DS2PR to configure planes
+	 * priorities and connects the superposition 0 to DU0 pins.
+	 * DU1 pins will be configured dynamically.
+	 *
+	 * For group 1 (DU2/DU3), if any, use DS2PR and DS3PT to configure
+	 * planes priorities and hardcode other bits.
 	 */
-	rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS);
+	if (rgrp->index == 0)
+		rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS);
+	else
+		rcar_du_group_write(rgrp, DORCR, DORCR_PG2T | DORCR_DK2S |
+				    DORCR_PG2D_DS2 | DORCR_DPRS);
+
 
 	/* Apply planes to CRTCs association. */
 	mutex_lock(&rgrp->lock);
@@ -247,6 +256,10 @@ int rcar_du_group_set_routing(struct rcar_du_group *rgrp)
 	struct rcar_du_crtc *crtc0 = &rgrp->dev->crtcs[rgrp->index * 2];
 	u32 dorcr = rcar_du_group_read(rgrp, DORCR);
 
+	/* Only group 0 (DU0/DU1) has pin routing options. */
+	if (rgrp->index > 0)
+		return 0;
+
 	dorcr &= ~(DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_MASK);
 
 	/*
-- 
2.7.4

WARNING: multiple messages have this Message-ID
From: Jacopo Mondi <jacopo+renesas@jmondi.org>
To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
	David Airlie <airlied@linux.ie>
Cc: ulrich.hecht+renesas@gmail.com,
	"open list:DRM DRIVERS FOR RENESAS"
	<linux-renesas-soc@vger.kernel.org>,
	Jacopo Mondi <jacopo+renesas@jmondi.org>,
	kieran.bingham@ideasonboard.com,
	"open list:DRM DRIVERS FOR RENESAS"
	<dri-devel@lists.freedesktop.org>
Subject: [PATCH 3/4] drm: rcar-du: Fix handling of DORCR for group 1
Date: Thu, 23 Aug 2018 17:12:13 +0200	[thread overview]
Message-ID: <1535037134-373-4-git-send-email-jacopo+renesas@jmondi.org> (raw)
In-Reply-To: <1535037134-373-1-git-send-email-jacopo+renesas@jmondi.org>

According to revision 1.00 of R-Car Gen3 Soc manual, only DU channels of
group 0 (DU0 and DU1) supports output control routing through register DORCR0.

For channels of group 1 (DU2 and DU3) which are only present on H3/M3-W/M3-N
SoCs, no routing options are available between super-imposition processors
and the output pin controller. The updated version of the SoC manual
prescribes thus to hardcode DPRCR2 bits that controls output pin routing for
those channels.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
 drivers/gpu/drm/rcar-du/rcar_du_group.c | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c
index ef2c177..e79d424 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
@@ -127,10 +127,19 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp)
 		rcar_du_group_write(rgrp, DEFR10, DEFR10_CODE | DEFR10_DEFE10);
 
 	/*
-	 * Use DS1PR and DS2PR to configure planes priorities and connects the
-	 * superposition 0 to DU0 pins. DU1 pins will be configured dynamically.
+	 * For group 0 (DU0/DU1) use DS1PR and DS2PR to configure planes
+	 * priorities and connects the superposition 0 to DU0 pins.
+	 * DU1 pins will be configured dynamically.
+	 *
+	 * For group 1 (DU2/DU3), if any, use DS2PR and DS3PT to configure
+	 * planes priorities and hardcode other bits.
 	 */
-	rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS);
+	if (rgrp->index == 0)
+		rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS);
+	else
+		rcar_du_group_write(rgrp, DORCR, DORCR_PG2T | DORCR_DK2S |
+				    DORCR_PG2D_DS2 | DORCR_DPRS);
+
 
 	/* Apply planes to CRTCs association. */
 	mutex_lock(&rgrp->lock);
@@ -247,6 +256,10 @@ int rcar_du_group_set_routing(struct rcar_du_group *rgrp)
 	struct rcar_du_crtc *crtc0 = &rgrp->dev->crtcs[rgrp->index * 2];
 	u32 dorcr = rcar_du_group_read(rgrp, DORCR);
 
+	/* Only group 0 (DU0/DU1) has pin routing options. */
+	if (rgrp->index > 0)
+		return 0;
+
 	dorcr &= ~(DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_MASK);
 
 	/*
-- 
2.7.4

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  parent reply	other threads:[~2018-08-23 18:42 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-23 15:12 [PATCH 0/4] drm: rcar-du: Update to SoC manual revision 1.00 Jacopo Mondi
2018-08-23 15:12 ` Jacopo Mondi
2018-08-23 15:12 ` [PATCH 1/4] drm: rcar-du: Do not write ESCR for DPLL channels Jacopo Mondi
2018-08-23 15:12   ` Jacopo Mondi
2018-08-23 15:12 ` [PATCH 2/4] drm: rcar-du: Write OTAR for DPAD channels only Jacopo Mondi
2018-08-23 15:12   ` Jacopo Mondi
2018-08-23 15:12 ` Jacopo Mondi [this message]
2018-08-23 15:12   ` [PATCH 3/4] drm: rcar-du: Fix handling of DORCR for group 1 Jacopo Mondi
2018-08-23 15:12 ` [PATCH 4/4] drm: rcar-du: Fix handling of PnMR register Jacopo Mondi
2018-08-23 15:12   ` Jacopo Mondi
2018-09-14 13:58 ` [PATCH 0/4] drm: rcar-du: Update to SoC manual revision 1.00 jacopo mondi
2018-09-14 13:58   ` jacopo mondi

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