[PATCH v2 00/13] drm/mediatek: support hdmi output for mt2701 and mt7623

[PATCH v2 00/13] drm/mediatek: support hdmi output for mt2701 and mt7623

[Bibby Hsieh]

In order to support HDMI on mt2701,
we have to make some modifications.
1) Add the HDMI driver.
2) Add the DPI driver.
3) Add a mechanism that config output component by dts.

Changes since v1:
 - Separate some patches to independent patch.
 - add DISP_REG_CONFIG_DSI_SEL and DISP_REG_CONFIG_DPI_SEL
   configuration in the condition of BLS&DPI0 connection.

Changes since v0:
 - Correct some typos in commit message.
 - Fixup the build warning (tmp variable didn't be initialized)

Bibby Hsieh (3):
  drm/mediatek: implement connection from BLS to DPI0
  drm/mediatek: add a error return value when clock driver has been
    prepared
  drm/mediatek: config component output by device node port

chunhui dai (10):
  drm/mediatek: add refcount for DPI power on/off
  drm/mediatek: move hardware register to node data
  drm/mediatek: adjust EDGE to match clock and data
  drm/mediatek: add clock factor for different IC
  drm/mediatek: dpi use new API for finding bridge
  drm/mediatek: add dpi driver for mt2701 and mt7623
  drm/mediatek: separae hdmi phy to different file
  drm/mediatek: register hdmi codec more earlier
  drm/mediatek: add support for SPDIF audio in HDMI
  drm/mediatek: add hdmi driver for MT2701 and MT7623

 drivers/gpu/drm/mediatek/Makefile              |  16 +-
 drivers/gpu/drm/mediatek/mtk_dpi.c             | 123 +++++++---
 drivers/gpu/drm/mediatek/mtk_dpi_regs.h        |   2 +-
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c         |  19 +-
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c    |   2 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.c         |  39 +++-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h         |   4 +-
 drivers/gpu/drm/mediatek/mtk_hdmi.c            |  51 ++--
 drivers/gpu/drm/mediatek/mtk_hdmi.h            |  27 +++
 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c        | 157 +++++++++++++
 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 307 +++++++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 129 +----------
 12 files changed, 690 insertions(+), 186 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c

-- 
2.12.5.2.gbdf23ab

[PATCH v2 00/13] drm/mediatek: support hdmi output for mt2701 and mt7623

[Bibby Hsieh]

In order to support HDMI on mt2701,
we have to make some modifications.
1) Add the HDMI driver.
2) Add the DPI driver.
3) Add a mechanism that config output component by dts.

Changes since v1:
 - Separate some patches to independent patch.
 - add DISP_REG_CONFIG_DSI_SEL and DISP_REG_CONFIG_DPI_SEL
   configuration in the condition of BLS&DPI0 connection.

Changes since v0:
 - Correct some typos in commit message.
 - Fixup the build warning (tmp variable didn't be initialized)

Bibby Hsieh (3):
  drm/mediatek: implement connection from BLS to DPI0
  drm/mediatek: add a error return value when clock driver has been
    prepared
  drm/mediatek: config component output by device node port

chunhui dai (10):
  drm/mediatek: add refcount for DPI power on/off
  drm/mediatek: move hardware register to node data
  drm/mediatek: adjust EDGE to match clock and data
  drm/mediatek: add clock factor for different IC
  drm/mediatek: dpi use new API for finding bridge
  drm/mediatek: add dpi driver for mt2701 and mt7623
  drm/mediatek: separae hdmi phy to different file
  drm/mediatek: register hdmi codec more earlier
  drm/mediatek: add support for SPDIF audio in HDMI
  drm/mediatek: add hdmi driver for MT2701 and MT7623

 drivers/gpu/drm/mediatek/Makefile              |  16 +-
 drivers/gpu/drm/mediatek/mtk_dpi.c             | 123 +++++++---
 drivers/gpu/drm/mediatek/mtk_dpi_regs.h        |   2 +-
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c         |  19 +-
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c    |   2 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.c         |  39 +++-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h         |   4 +-
 drivers/gpu/drm/mediatek/mtk_hdmi.c            |  51 ++--
 drivers/gpu/drm/mediatek/mtk_hdmi.h            |  27 +++
 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c        | 157 +++++++++++++
 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 307 +++++++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 129 +----------
 12 files changed, 690 insertions(+), 186 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c

-- 
2.12.5.2.gbdf23ab

[PATCH v2 00/13] drm/mediatek: support hdmi output for mt2701 and mt7623

[Bibby Hsieh]

In order to support HDMI on mt2701,
we have to make some modifications.
1) Add the HDMI driver.
2) Add the DPI driver.
3) Add a mechanism that config output component by dts.

Changes since v1:
 - Separate some patches to independent patch.
 - add DISP_REG_CONFIG_DSI_SEL and DISP_REG_CONFIG_DPI_SEL
   configuration in the condition of BLS&DPI0 connection.

Changes since v0:
 - Correct some typos in commit message.
 - Fixup the build warning (tmp variable didn't be initialized)

Bibby Hsieh (3):
  drm/mediatek: implement connection from BLS to DPI0
  drm/mediatek: add a error return value when clock driver has been
    prepared
  drm/mediatek: config component output by device node port

chunhui dai (10):
  drm/mediatek: add refcount for DPI power on/off
  drm/mediatek: move hardware register to node data
  drm/mediatek: adjust EDGE to match clock and data
  drm/mediatek: add clock factor for different IC
  drm/mediatek: dpi use new API for finding bridge
  drm/mediatek: add dpi driver for mt2701 and mt7623
  drm/mediatek: separae hdmi phy to different file
  drm/mediatek: register hdmi codec more earlier
  drm/mediatek: add support for SPDIF audio in HDMI
  drm/mediatek: add hdmi driver for MT2701 and MT7623

 drivers/gpu/drm/mediatek/Makefile              |  16 +-
 drivers/gpu/drm/mediatek/mtk_dpi.c             | 123 +++++++---
 drivers/gpu/drm/mediatek/mtk_dpi_regs.h        |   2 +-
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c         |  19 +-
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c    |   2 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.c         |  39 +++-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h         |   4 +-
 drivers/gpu/drm/mediatek/mtk_hdmi.c            |  51 ++--
 drivers/gpu/drm/mediatek/mtk_hdmi.h            |  27 +++
 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c        | 157 +++++++++++++
 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 307 +++++++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 129 +----------
 12 files changed, 690 insertions(+), 186 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c

-- 
2.12.5.2.gbdf23ab

[PATCH v2 01/13] drm/mediatek: add refcount for DPI power on/off

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

add refcount for DPI power on/off to protect the flow

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 6c0ea39d5739..d9373e67d328 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -77,6 +77,7 @@ struct mtk_dpi {
 	enum mtk_dpi_out_bit_num bit_num;
 	enum mtk_dpi_out_channel_swap channel_swap;
 	bool power_sta;
+	int refcount;
 	u8 power_ctl;
 };
 
@@ -369,6 +370,12 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
 
 static void mtk_dpi_power_off(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl)
 {
+	if (WARN_ON(dpi->refcount == 0))
+		return;
+
+	if (--dpi->refcount != 0)
+		return;
+
 	dpi->power_ctl &= ~pctl;
 
 	if ((dpi->power_ctl & DPI_POWER_START) ||
@@ -388,14 +395,17 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl)
 {
 	int ret;
 
+	if (++dpi->refcount != 1)
+		return 0;
+
 	dpi->power_ctl |= pctl;
 
 	if (!(dpi->power_ctl & DPI_POWER_START) &&
 	    !(dpi->power_ctl & DPI_POWER_ENABLE))
-		return 0;
+		goto err_refcount;
 
 	if (dpi->power_sta)
-		return 0;
+		goto err_refcount;
 
 	ret = clk_prepare_enable(dpi->engine_clk);
 	if (ret) {
@@ -417,6 +427,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl)
 	clk_disable_unprepare(dpi->engine_clk);
 err_eng:
 	dpi->power_ctl &= ~pctl;
+err_refcount:
+	dpi->refcount--;
 	return ret;
 }
 
-- 
2.12.5.2.gbdf23ab

[PATCH v2 01/13] drm/mediatek: add refcount for DPI power on/off

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

add refcount for DPI power on/off to protect the flow

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 6c0ea39d5739..d9373e67d328 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -77,6 +77,7 @@ struct mtk_dpi {
 	enum mtk_dpi_out_bit_num bit_num;
 	enum mtk_dpi_out_channel_swap channel_swap;
 	bool power_sta;
+	int refcount;
 	u8 power_ctl;
 };
 
@@ -369,6 +370,12 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
 
 static void mtk_dpi_power_off(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl)
 {
+	if (WARN_ON(dpi->refcount == 0))
+		return;
+
+	if (--dpi->refcount != 0)
+		return;
+
 	dpi->power_ctl &= ~pctl;
 
 	if ((dpi->power_ctl & DPI_POWER_START) ||
@@ -388,14 +395,17 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl)
 {
 	int ret;
 
+	if (++dpi->refcount != 1)
+		return 0;
+
 	dpi->power_ctl |= pctl;
 
 	if (!(dpi->power_ctl & DPI_POWER_START) &&
 	    !(dpi->power_ctl & DPI_POWER_ENABLE))
-		return 0;
+		goto err_refcount;
 
 	if (dpi->power_sta)
-		return 0;
+		goto err_refcount;
 
 	ret = clk_prepare_enable(dpi->engine_clk);
 	if (ret) {
@@ -417,6 +427,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl)
 	clk_disable_unprepare(dpi->engine_clk);
 err_eng:
 	dpi->power_ctl &= ~pctl;
+err_refcount:
+	dpi->refcount--;
 	return ret;
 }
 
-- 
2.12.5.2.gbdf23ab

[PATCH v2 01/13] drm/mediatek: add refcount for DPI power on/off

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

add refcount for DPI power on/off to protect the flow

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 6c0ea39d5739..d9373e67d328 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -77,6 +77,7 @@ struct mtk_dpi {
 	enum mtk_dpi_out_bit_num bit_num;
 	enum mtk_dpi_out_channel_swap channel_swap;
 	bool power_sta;
+	int refcount;
 	u8 power_ctl;
 };
 
@@ -369,6 +370,12 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
 
 static void mtk_dpi_power_off(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl)
 {
+	if (WARN_ON(dpi->refcount == 0))
+		return;
+
+	if (--dpi->refcount != 0)
+		return;
+
 	dpi->power_ctl &= ~pctl;
 
 	if ((dpi->power_ctl & DPI_POWER_START) ||
@@ -388,14 +395,17 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl)
 {
 	int ret;
 
+	if (++dpi->refcount != 1)
+		return 0;
+
 	dpi->power_ctl |= pctl;
 
 	if (!(dpi->power_ctl & DPI_POWER_START) &&
 	    !(dpi->power_ctl & DPI_POWER_ENABLE))
-		return 0;
+		goto err_refcount;
 
 	if (dpi->power_sta)
-		return 0;
+		goto err_refcount;
 
 	ret = clk_prepare_enable(dpi->engine_clk);
 	if (ret) {
@@ -417,6 +427,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl)
 	clk_disable_unprepare(dpi->engine_clk);
 err_eng:
 	dpi->power_ctl &= ~pctl;
+err_refcount:
+	dpi->refcount--;
 	return ret;
 }
 
-- 
2.12.5.2.gbdf23ab

[PATCH v2 02/13] drm/mediatek: move hardware register to node data

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

The address of register DPI_H_FRE_CON is different in different IC.
Using of_node data to find this address.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c      | 29 +++++++++++++++++++++++------
 drivers/gpu/drm/mediatek/mtk_dpi_regs.h |  1 -
 2 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index d9373e67d328..3db959fed493 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -72,6 +72,7 @@ struct mtk_dpi {
 	struct clk *tvd_clk;
 	int irq;
 	struct drm_display_mode mode;
+	const struct mtk_dpi_conf *conf;
 	enum mtk_dpi_out_color_format color_format;
 	enum mtk_dpi_out_yc_map yc_map;
 	enum mtk_dpi_out_bit_num bit_num;
@@ -117,6 +118,10 @@ struct mtk_dpi_yc_limit {
 	u16 c_bottom;
 };
 
+struct mtk_dpi_conf {
+	const u32 reg_h_fre_con;
+};
+
 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
 {
 	u32 tmp = readl(dpi->regs + offset) & ~mask;
@@ -342,7 +347,7 @@ static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
 
 static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
 {
-	mtk_dpi_mask(dpi, DPI_H_FRE_CON, H_FRE_2N, H_FRE_2N);
+	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
 }
 
 static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
@@ -668,6 +673,18 @@ static const struct component_ops mtk_dpi_component_ops = {
 	.unbind = mtk_dpi_unbind,
 };
 
+static const struct mtk_dpi_conf mt8173_conf = {
+	.reg_h_fre_con = 0xe0,
+};
+
+static const struct of_device_id mtk_dpi_of_ids[] = {
+	{ .compatible = "mediatek,mt8173-dpi",
+	  .data = &mt8173_conf,
+	},
+	{ },
+};
+MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
+
 static int mtk_dpi_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -675,13 +692,18 @@ static int mtk_dpi_probe(struct platform_device *pdev)
 	struct resource *mem;
 	struct device_node *bridge_node;
 	int comp_id;
+	const struct of_device_id *match;
 	int ret;
 
+	match = of_match_node(mtk_dpi_of_ids, dev->of_node);
+	if (!match)
+		return -ENODEV;
 	dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
 	if (!dpi)
 		return -ENOMEM;
 
 	dpi->dev = dev;
+	dpi->conf = (struct mtk_dpi_conf *)match->data;
 
 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	dpi->regs = devm_ioremap_resource(dev, mem);
@@ -760,11 +782,6 @@ static int mtk_dpi_remove(struct platform_device *pdev)
 	return 0;
 }
 
-static const struct of_device_id mtk_dpi_of_ids[] = {
-	{ .compatible = "mediatek,mt8173-dpi", },
-	{}
-};
-
 struct platform_driver mtk_dpi_driver = {
 	.probe = mtk_dpi_probe,
 	.remove = mtk_dpi_remove,
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
index 4b6ad4751a31..040444d7718d 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
@@ -223,6 +223,5 @@
 #define ESAV_CODE2			(0xFFF << 0)
 #define ESAV_CODE3_MSB			BIT(16)
 
-#define DPI_H_FRE_CON		0xE0
 #define H_FRE_2N			BIT(25)
 #endif /* __MTK_DPI_REGS_H */
-- 
2.12.5.2.gbdf23ab

[PATCH v2 02/13] drm/mediatek: move hardware register to node data

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

The address of register DPI_H_FRE_CON is different in different IC.
Using of_node data to find this address.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c      | 29 +++++++++++++++++++++++------
 drivers/gpu/drm/mediatek/mtk_dpi_regs.h |  1 -
 2 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index d9373e67d328..3db959fed493 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -72,6 +72,7 @@ struct mtk_dpi {
 	struct clk *tvd_clk;
 	int irq;
 	struct drm_display_mode mode;
+	const struct mtk_dpi_conf *conf;
 	enum mtk_dpi_out_color_format color_format;
 	enum mtk_dpi_out_yc_map yc_map;
 	enum mtk_dpi_out_bit_num bit_num;
@@ -117,6 +118,10 @@ struct mtk_dpi_yc_limit {
 	u16 c_bottom;
 };
 
+struct mtk_dpi_conf {
+	const u32 reg_h_fre_con;
+};
+
 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
 {
 	u32 tmp = readl(dpi->regs + offset) & ~mask;
@@ -342,7 +347,7 @@ static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
 
 static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
 {
-	mtk_dpi_mask(dpi, DPI_H_FRE_CON, H_FRE_2N, H_FRE_2N);
+	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
 }
 
 static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
@@ -668,6 +673,18 @@ static const struct component_ops mtk_dpi_component_ops = {
 	.unbind = mtk_dpi_unbind,
 };
 
+static const struct mtk_dpi_conf mt8173_conf = {
+	.reg_h_fre_con = 0xe0,
+};
+
+static const struct of_device_id mtk_dpi_of_ids[] = {
+	{ .compatible = "mediatek,mt8173-dpi",
+	  .data = &mt8173_conf,
+	},
+	{ },
+};
+MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
+
 static int mtk_dpi_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -675,13 +692,18 @@ static int mtk_dpi_probe(struct platform_device *pdev)
 	struct resource *mem;
 	struct device_node *bridge_node;
 	int comp_id;
+	const struct of_device_id *match;
 	int ret;
 
+	match = of_match_node(mtk_dpi_of_ids, dev->of_node);
+	if (!match)
+		return -ENODEV;
 	dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
 	if (!dpi)
 		return -ENOMEM;
 
 	dpi->dev = dev;
+	dpi->conf = (struct mtk_dpi_conf *)match->data;
 
 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	dpi->regs = devm_ioremap_resource(dev, mem);
@@ -760,11 +782,6 @@ static int mtk_dpi_remove(struct platform_device *pdev)
 	return 0;
 }
 
-static const struct of_device_id mtk_dpi_of_ids[] = {
-	{ .compatible = "mediatek,mt8173-dpi", },
-	{}
-};
-
 struct platform_driver mtk_dpi_driver = {
 	.probe = mtk_dpi_probe,
 	.remove = mtk_dpi_remove,
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
index 4b6ad4751a31..040444d7718d 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
@@ -223,6 +223,5 @@
 #define ESAV_CODE2			(0xFFF << 0)
 #define ESAV_CODE3_MSB			BIT(16)
 
-#define DPI_H_FRE_CON		0xE0
 #define H_FRE_2N			BIT(25)
 #endif /* __MTK_DPI_REGS_H */
-- 
2.12.5.2.gbdf23ab

[PATCH v2 02/13] drm/mediatek: move hardware register to node data

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

The address of register DPI_H_FRE_CON is different in different IC.
Using of_node data to find this address.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c      | 29 +++++++++++++++++++++++------
 drivers/gpu/drm/mediatek/mtk_dpi_regs.h |  1 -
 2 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index d9373e67d328..3db959fed493 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -72,6 +72,7 @@ struct mtk_dpi {
 	struct clk *tvd_clk;
 	int irq;
 	struct drm_display_mode mode;
+	const struct mtk_dpi_conf *conf;
 	enum mtk_dpi_out_color_format color_format;
 	enum mtk_dpi_out_yc_map yc_map;
 	enum mtk_dpi_out_bit_num bit_num;
@@ -117,6 +118,10 @@ struct mtk_dpi_yc_limit {
 	u16 c_bottom;
 };
 
+struct mtk_dpi_conf {
+	const u32 reg_h_fre_con;
+};
+
 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
 {
 	u32 tmp = readl(dpi->regs + offset) & ~mask;
@@ -342,7 +347,7 @@ static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
 
 static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
 {
-	mtk_dpi_mask(dpi, DPI_H_FRE_CON, H_FRE_2N, H_FRE_2N);
+	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
 }
 
 static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
@@ -668,6 +673,18 @@ static const struct component_ops mtk_dpi_component_ops = {
 	.unbind = mtk_dpi_unbind,
 };
 
+static const struct mtk_dpi_conf mt8173_conf = {
+	.reg_h_fre_con = 0xe0,
+};
+
+static const struct of_device_id mtk_dpi_of_ids[] = {
+	{ .compatible = "mediatek,mt8173-dpi",
+	  .data = &mt8173_conf,
+	},
+	{ },
+};
+MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
+
 static int mtk_dpi_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -675,13 +692,18 @@ static int mtk_dpi_probe(struct platform_device *pdev)
 	struct resource *mem;
 	struct device_node *bridge_node;
 	int comp_id;
+	const struct of_device_id *match;
 	int ret;
 
+	match = of_match_node(mtk_dpi_of_ids, dev->of_node);
+	if (!match)
+		return -ENODEV;
 	dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
 	if (!dpi)
 		return -ENOMEM;
 
 	dpi->dev = dev;
+	dpi->conf = (struct mtk_dpi_conf *)match->data;
 
 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	dpi->regs = devm_ioremap_resource(dev, mem);
@@ -760,11 +782,6 @@ static int mtk_dpi_remove(struct platform_device *pdev)
 	return 0;
 }
 
-static const struct of_device_id mtk_dpi_of_ids[] = {
-	{ .compatible = "mediatek,mt8173-dpi", },
-	{}
-};
-
 struct platform_driver mtk_dpi_driver = {
 	.probe = mtk_dpi_probe,
 	.remove = mtk_dpi_remove,
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
index 4b6ad4751a31..040444d7718d 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
@@ -223,6 +223,5 @@
 #define ESAV_CODE2			(0xFFF << 0)
 #define ESAV_CODE3_MSB			BIT(16)
 
-#define DPI_H_FRE_CON		0xE0
 #define H_FRE_2N			BIT(25)
 #endif /* __MTK_DPI_REGS_H */
-- 
2.12.5.2.gbdf23ab

[PATCH v2 03/13] drm/mediatek: adjust EDGE to match clock and data

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

The default timing of DPI data and clock is not match.
We could adjust this bit to make them match.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c      | 8 ++++++++
 drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 1 +
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 3db959fed493..df27107b1f0b 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -120,6 +120,7 @@ struct mtk_dpi_yc_limit {
 
 struct mtk_dpi_conf {
 	const u32 reg_h_fre_con;
+	bool edge_sel_en;
 };
 
 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -350,6 +351,12 @@ static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
 	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
 }
 
+static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
+{
+	if (dpi->conf->edge_sel_en)
+		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
+}
+
 static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
 					enum mtk_dpi_out_color_format format)
 {
@@ -535,6 +542,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 	mtk_dpi_config_yc_map(dpi, dpi->yc_map);
 	mtk_dpi_config_color_format(dpi, dpi->color_format);
 	mtk_dpi_config_2n_h_fre(dpi);
+	mtk_dpi_config_disable_edge(dpi);
 	mtk_dpi_sw_reset(dpi, false);
 
 	return 0;
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
index 040444d7718d..d9db8c4cacd7 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
@@ -223,5 +223,6 @@
 #define ESAV_CODE2			(0xFFF << 0)
 #define ESAV_CODE3_MSB			BIT(16)
 
+#define EDGE_SEL_EN			BIT(5)
 #define H_FRE_2N			BIT(25)
 #endif /* __MTK_DPI_REGS_H */
-- 
2.12.5.2.gbdf23ab

[PATCH v2 03/13] drm/mediatek: adjust EDGE to match clock and data

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

The default timing of DPI data and clock is not match.
We could adjust this bit to make them match.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c      | 8 ++++++++
 drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 1 +
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 3db959fed493..df27107b1f0b 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -120,6 +120,7 @@ struct mtk_dpi_yc_limit {
 
 struct mtk_dpi_conf {
 	const u32 reg_h_fre_con;
+	bool edge_sel_en;
 };
 
 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -350,6 +351,12 @@ static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
 	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
 }
 
+static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
+{
+	if (dpi->conf->edge_sel_en)
+		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
+}
+
 static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
 					enum mtk_dpi_out_color_format format)
 {
@@ -535,6 +542,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 	mtk_dpi_config_yc_map(dpi, dpi->yc_map);
 	mtk_dpi_config_color_format(dpi, dpi->color_format);
 	mtk_dpi_config_2n_h_fre(dpi);
+	mtk_dpi_config_disable_edge(dpi);
 	mtk_dpi_sw_reset(dpi, false);
 
 	return 0;
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
index 040444d7718d..d9db8c4cacd7 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
@@ -223,5 +223,6 @@
 #define ESAV_CODE2			(0xFFF << 0)
 #define ESAV_CODE3_MSB			BIT(16)
 
+#define EDGE_SEL_EN			BIT(5)
 #define H_FRE_2N			BIT(25)
 #endif /* __MTK_DPI_REGS_H */
-- 
2.12.5.2.gbdf23ab

[PATCH v2 03/13] drm/mediatek: adjust EDGE to match clock and data

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

The default timing of DPI data and clock is not match.
We could adjust this bit to make them match.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c      | 8 ++++++++
 drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 1 +
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 3db959fed493..df27107b1f0b 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -120,6 +120,7 @@ struct mtk_dpi_yc_limit {
 
 struct mtk_dpi_conf {
 	const u32 reg_h_fre_con;
+	bool edge_sel_en;
 };
 
 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -350,6 +351,12 @@ static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
 	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
 }
 
+static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
+{
+	if (dpi->conf->edge_sel_en)
+		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
+}
+
 static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
 					enum mtk_dpi_out_color_format format)
 {
@@ -535,6 +542,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 	mtk_dpi_config_yc_map(dpi, dpi->yc_map);
 	mtk_dpi_config_color_format(dpi, dpi->color_format);
 	mtk_dpi_config_2n_h_fre(dpi);
+	mtk_dpi_config_disable_edge(dpi);
 	mtk_dpi_sw_reset(dpi, false);
 
 	return 0;
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
index 040444d7718d..d9db8c4cacd7 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
@@ -223,5 +223,6 @@
 #define ESAV_CODE2			(0xFFF << 0)
 #define ESAV_CODE3_MSB			BIT(16)
 
+#define EDGE_SEL_EN			BIT(5)
 #define H_FRE_2N			BIT(25)
 #endif /* __MTK_DPI_REGS_H */
-- 
2.12.5.2.gbdf23ab

[PATCH v2 04/13] drm/mediatek: add clock factor for different IC

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

different IC has different clock designed in HDMI, the factor for
calculate clock should be different. Usinng the data in of_node
to find this factor.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 28 +++++++++++++++++++---------
 1 file changed, 19 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index df27107b1f0b..3758cfeb586b 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -119,6 +119,7 @@ struct mtk_dpi_yc_limit {
 };
 
 struct mtk_dpi_conf {
+	unsigned int (*cal_factor)(int clock);
 	const u32 reg_h_fre_con;
 	bool edge_sel_en;
 };
@@ -458,16 +459,12 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 	unsigned long pll_rate;
 	unsigned int factor;
 
+	if (!dpi) {
+		dev_err(dpi->dev, "invalid argument\n");
+		return -EINVAL;
+	}
 	/* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
-
-	if (mode->clock <= 27000)
-		factor = 3 << 4;
-	else if (mode->clock <= 84000)
-		factor = 3 << 3;
-	else if (mode->clock <= 167000)
-		factor = 3 << 2;
-	else
-		factor = 3 << 1;
+	factor = dpi->conf->cal_factor(mode->clock);
 	drm_display_mode_to_videomode(mode, &vm);
 	pll_rate = vm.pixelclock * factor;
 
@@ -681,7 +678,20 @@ static const struct component_ops mtk_dpi_component_ops = {
 	.unbind = mtk_dpi_unbind,
 };
 
+static unsigned int mt8173_calculate_factor(int clock)
+{
+	if (clock <= 27000)
+		return 3 << 4;
+	else if (clock <= 84000)
+		return 3 << 3;
+	else if (clock <= 167000)
+		return 3 << 2;
+	else
+		return 3 << 1;
+}
+
 static const struct mtk_dpi_conf mt8173_conf = {
+	.cal_factor = mt8173_calculate_factor,
 	.reg_h_fre_con = 0xe0,
 };
 
-- 
2.12.5.2.gbdf23ab

[PATCH v2 04/13] drm/mediatek: add clock factor for different IC

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

different IC has different clock designed in HDMI, the factor for
calculate clock should be different. Usinng the data in of_node
to find this factor.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 28 +++++++++++++++++++---------
 1 file changed, 19 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index df27107b1f0b..3758cfeb586b 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -119,6 +119,7 @@ struct mtk_dpi_yc_limit {
 };
 
 struct mtk_dpi_conf {
+	unsigned int (*cal_factor)(int clock);
 	const u32 reg_h_fre_con;
 	bool edge_sel_en;
 };
@@ -458,16 +459,12 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 	unsigned long pll_rate;
 	unsigned int factor;
 
+	if (!dpi) {
+		dev_err(dpi->dev, "invalid argument\n");
+		return -EINVAL;
+	}
 	/* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
-
-	if (mode->clock <= 27000)
-		factor = 3 << 4;
-	else if (mode->clock <= 84000)
-		factor = 3 << 3;
-	else if (mode->clock <= 167000)
-		factor = 3 << 2;
-	else
-		factor = 3 << 1;
+	factor = dpi->conf->cal_factor(mode->clock);
 	drm_display_mode_to_videomode(mode, &vm);
 	pll_rate = vm.pixelclock * factor;
 
@@ -681,7 +678,20 @@ static const struct component_ops mtk_dpi_component_ops = {
 	.unbind = mtk_dpi_unbind,
 };
 
+static unsigned int mt8173_calculate_factor(int clock)
+{
+	if (clock <= 27000)
+		return 3 << 4;
+	else if (clock <= 84000)
+		return 3 << 3;
+	else if (clock <= 167000)
+		return 3 << 2;
+	else
+		return 3 << 1;
+}
+
 static const struct mtk_dpi_conf mt8173_conf = {
+	.cal_factor = mt8173_calculate_factor,
 	.reg_h_fre_con = 0xe0,
 };
 
-- 
2.12.5.2.gbdf23ab

[PATCH v2 04/13] drm/mediatek: add clock factor for different IC

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

different IC has different clock designed in HDMI, the factor for
calculate clock should be different. Usinng the data in of_node
to find this factor.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 28 +++++++++++++++++++---------
 1 file changed, 19 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index df27107b1f0b..3758cfeb586b 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -119,6 +119,7 @@ struct mtk_dpi_yc_limit {
 };
 
 struct mtk_dpi_conf {
+	unsigned int (*cal_factor)(int clock);
 	const u32 reg_h_fre_con;
 	bool edge_sel_en;
 };
@@ -458,16 +459,12 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 	unsigned long pll_rate;
 	unsigned int factor;
 
+	if (!dpi) {
+		dev_err(dpi->dev, "invalid argument\n");
+		return -EINVAL;
+	}
 	/* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
-
-	if (mode->clock <= 27000)
-		factor = 3 << 4;
-	else if (mode->clock <= 84000)
-		factor = 3 << 3;
-	else if (mode->clock <= 167000)
-		factor = 3 << 2;
-	else
-		factor = 3 << 1;
+	factor = dpi->conf->cal_factor(mode->clock);
 	drm_display_mode_to_videomode(mode, &vm);
 	pll_rate = vm.pixelclock * factor;
 
@@ -681,7 +678,20 @@ static const struct component_ops mtk_dpi_component_ops = {
 	.unbind = mtk_dpi_unbind,
 };
 
+static unsigned int mt8173_calculate_factor(int clock)
+{
+	if (clock <= 27000)
+		return 3 << 4;
+	else if (clock <= 84000)
+		return 3 << 3;
+	else if (clock <= 167000)
+		return 3 << 2;
+	else
+		return 3 << 1;
+}
+
 static const struct mtk_dpi_conf mt8173_conf = {
+	.cal_factor = mt8173_calculate_factor,
 	.reg_h_fre_con = 0xe0,
 };
 
-- 
2.12.5.2.gbdf23ab

[PATCH v2 05/13] drm/mediatek: dpi use new API for finding bridge

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

Using new API for finding bridge.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 3758cfeb586b..ed2c153c70a2 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -14,6 +14,7 @@
 #include <drm/drmP.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
+#include <drm/drm_of.h>
 #include <linux/kernel.h>
 #include <linux/component.h>
 #include <linux/platform_device.h>
@@ -708,7 +709,6 @@ static int mtk_dpi_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct mtk_dpi *dpi;
 	struct resource *mem;
-	struct device_node *bridge_node;
 	int comp_id;
 	const struct of_device_id *match;
 	int ret;
@@ -758,16 +758,13 @@ static int mtk_dpi_probe(struct platform_device *pdev)
 		return -EINVAL;
 	}
 
-	bridge_node = of_graph_get_remote_node(dev->of_node, 0, 0);
-	if (!bridge_node)
-		return -ENODEV;
-
-	dev_info(dev, "Found bridge node: %pOF\n", bridge_node);
-
-	dpi->bridge = of_drm_find_bridge(bridge_node);
-	of_node_put(bridge_node);
-	if (!dpi->bridge)
+	ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
+					  NULL, &dpi->bridge);
+	if (ret) {
+		dev_err(dev, "Failed to find panel or bridge: %d\n", ret);
 		return -EPROBE_DEFER;
+	}
+	dev_info(dev, "Found bridge node: %pOF\n", dpi->bridge);
 
 	comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DPI);
 	if (comp_id < 0) {
-- 
2.12.5.2.gbdf23ab

[PATCH v2 05/13] drm/mediatek: dpi use new API for finding bridge

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

Using new API for finding bridge.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 3758cfeb586b..ed2c153c70a2 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -14,6 +14,7 @@
 #include <drm/drmP.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
+#include <drm/drm_of.h>
 #include <linux/kernel.h>
 #include <linux/component.h>
 #include <linux/platform_device.h>
@@ -708,7 +709,6 @@ static int mtk_dpi_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct mtk_dpi *dpi;
 	struct resource *mem;
-	struct device_node *bridge_node;
 	int comp_id;
 	const struct of_device_id *match;
 	int ret;
@@ -758,16 +758,13 @@ static int mtk_dpi_probe(struct platform_device *pdev)
 		return -EINVAL;
 	}
 
-	bridge_node = of_graph_get_remote_node(dev->of_node, 0, 0);
-	if (!bridge_node)
-		return -ENODEV;
-
-	dev_info(dev, "Found bridge node: %pOF\n", bridge_node);
-
-	dpi->bridge = of_drm_find_bridge(bridge_node);
-	of_node_put(bridge_node);
-	if (!dpi->bridge)
+	ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
+					  NULL, &dpi->bridge);
+	if (ret) {
+		dev_err(dev, "Failed to find panel or bridge: %d\n", ret);
 		return -EPROBE_DEFER;
+	}
+	dev_info(dev, "Found bridge node: %pOF\n", dpi->bridge);
 
 	comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DPI);
 	if (comp_id < 0) {
-- 
2.12.5.2.gbdf23ab

[PATCH v2 05/13] drm/mediatek: dpi use new API for finding bridge

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

Using new API for finding bridge.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 3758cfeb586b..ed2c153c70a2 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -14,6 +14,7 @@
 #include <drm/drmP.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
+#include <drm/drm_of.h>
 #include <linux/kernel.h>
 #include <linux/component.h>
 #include <linux/platform_device.h>
@@ -708,7 +709,6 @@ static int mtk_dpi_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct mtk_dpi *dpi;
 	struct resource *mem;
-	struct device_node *bridge_node;
 	int comp_id;
 	const struct of_device_id *match;
 	int ret;
@@ -758,16 +758,13 @@ static int mtk_dpi_probe(struct platform_device *pdev)
 		return -EINVAL;
 	}
 
-	bridge_node = of_graph_get_remote_node(dev->of_node, 0, 0);
-	if (!bridge_node)
-		return -ENODEV;
-
-	dev_info(dev, "Found bridge node: %pOF\n", bridge_node);
-
-	dpi->bridge = of_drm_find_bridge(bridge_node);
-	of_node_put(bridge_node);
-	if (!dpi->bridge)
+	ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
+					  NULL, &dpi->bridge);
+	if (ret) {
+		dev_err(dev, "Failed to find panel or bridge: %d\n", ret);
 		return -EPROBE_DEFER;
+	}
+	dev_info(dev, "Found bridge node: %pOF\n", dpi->bridge);
 
 	comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DPI);
 	if (comp_id < 0) {
-- 
2.12.5.2.gbdf23ab

[PATCH v2 06/13] drm/mediatek: add dpi driver for mt2701 and mt7623

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

This patch adds dpi dirver suppot for both mt2701 and mt7623.
And also support other (existing or future) chips that use
the same binding and driver.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c     | 25 ++++++++++++++++++++++---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c |  2 ++
 2 files changed, 24 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index ed2c153c70a2..1af25765ab5f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -641,9 +641,7 @@ static int mtk_dpi_bind(struct device *dev, struct device *master, void *data)
 	}
 	drm_encoder_helper_add(&dpi->encoder, &mtk_dpi_encoder_helper_funcs);
 
-	/* Currently DPI0 is fixed to be driven by OVL1 */
-	dpi->encoder.possible_crtcs = BIT(1);
-
+	dpi->encoder.possible_crtcs = BIT(0) | BIT(1);
 	ret = drm_bridge_attach(&dpi->encoder, dpi->bridge, NULL);
 	if (ret) {
 		dev_err(dev, "Failed to attach bridge: %d\n", ret);
@@ -691,12 +689,33 @@ static unsigned int mt8173_calculate_factor(int clock)
 		return 3 << 1;
 }
 
+static unsigned int mt2701_calculate_factor(int clock)
+{
+	if (clock <= 64000)
+		return 16;
+	else if (clock <= 128000)
+		return 8;
+	else if (clock <= 256000)
+		return 4;
+	else
+		return 2;
+}
+
 static const struct mtk_dpi_conf mt8173_conf = {
 	.cal_factor = mt8173_calculate_factor,
 	.reg_h_fre_con = 0xe0,
 };
 
+static const struct mtk_dpi_conf mt2701_conf = {
+	.cal_factor = mt2701_calculate_factor,
+	.reg_h_fre_con = 0xb0,
+	.edge_sel_en = true,
+};
+
 static const struct of_device_id mtk_dpi_of_ids[] = {
+	{ .compatible = "mediatek,mt2701-dpi",
+	  .data = &mt2701_conf,
+	},
 	{ .compatible = "mediatek,mt8173-dpi",
 	  .data = &mt8173_conf,
 	},
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 39721119713b..d961112fa2f5 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -424,6 +424,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DSI },
 	{ .compatible = "mediatek,mt8173-dsi",
 	  .data = (void *)MTK_DSI },
+	{ .compatible = "mediatek,mt2701-dpi",
+	  .data = (void *)MTK_DPI },
 	{ .compatible = "mediatek,mt8173-dpi",
 	  .data = (void *)MTK_DPI },
 	{ .compatible = "mediatek,mt2701-disp-mutex",
-- 
2.12.5.2.gbdf23ab

[PATCH v2 06/13] drm/mediatek: add dpi driver for mt2701 and mt7623

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

This patch adds dpi dirver suppot for both mt2701 and mt7623.
And also support other (existing or future) chips that use
the same binding and driver.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c     | 25 ++++++++++++++++++++++---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c |  2 ++
 2 files changed, 24 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index ed2c153c70a2..1af25765ab5f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -641,9 +641,7 @@ static int mtk_dpi_bind(struct device *dev, struct device *master, void *data)
 	}
 	drm_encoder_helper_add(&dpi->encoder, &mtk_dpi_encoder_helper_funcs);
 
-	/* Currently DPI0 is fixed to be driven by OVL1 */
-	dpi->encoder.possible_crtcs = BIT(1);
-
+	dpi->encoder.possible_crtcs = BIT(0) | BIT(1);
 	ret = drm_bridge_attach(&dpi->encoder, dpi->bridge, NULL);
 	if (ret) {
 		dev_err(dev, "Failed to attach bridge: %d\n", ret);
@@ -691,12 +689,33 @@ static unsigned int mt8173_calculate_factor(int clock)
 		return 3 << 1;
 }
 
+static unsigned int mt2701_calculate_factor(int clock)
+{
+	if (clock <= 64000)
+		return 16;
+	else if (clock <= 128000)
+		return 8;
+	else if (clock <= 256000)
+		return 4;
+	else
+		return 2;
+}
+
 static const struct mtk_dpi_conf mt8173_conf = {
 	.cal_factor = mt8173_calculate_factor,
 	.reg_h_fre_con = 0xe0,
 };
 
+static const struct mtk_dpi_conf mt2701_conf = {
+	.cal_factor = mt2701_calculate_factor,
+	.reg_h_fre_con = 0xb0,
+	.edge_sel_en = true,
+};
+
 static const struct of_device_id mtk_dpi_of_ids[] = {
+	{ .compatible = "mediatek,mt2701-dpi",
+	  .data = &mt2701_conf,
+	},
 	{ .compatible = "mediatek,mt8173-dpi",
 	  .data = &mt8173_conf,
 	},
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 39721119713b..d961112fa2f5 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -424,6 +424,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DSI },
 	{ .compatible = "mediatek,mt8173-dsi",
 	  .data = (void *)MTK_DSI },
+	{ .compatible = "mediatek,mt2701-dpi",
+	  .data = (void *)MTK_DPI },
 	{ .compatible = "mediatek,mt8173-dpi",
 	  .data = (void *)MTK_DPI },
 	{ .compatible = "mediatek,mt2701-disp-mutex",
-- 
2.12.5.2.gbdf23ab

[PATCH v2 06/13] drm/mediatek: add dpi driver for mt2701 and mt7623

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

This patch adds dpi dirver suppot for both mt2701 and mt7623.
And also support other (existing or future) chips that use
the same binding and driver.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c     | 25 ++++++++++++++++++++++---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c |  2 ++
 2 files changed, 24 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index ed2c153c70a2..1af25765ab5f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -641,9 +641,7 @@ static int mtk_dpi_bind(struct device *dev, struct device *master, void *data)
 	}
 	drm_encoder_helper_add(&dpi->encoder, &mtk_dpi_encoder_helper_funcs);
 
-	/* Currently DPI0 is fixed to be driven by OVL1 */
-	dpi->encoder.possible_crtcs = BIT(1);
-
+	dpi->encoder.possible_crtcs = BIT(0) | BIT(1);
 	ret = drm_bridge_attach(&dpi->encoder, dpi->bridge, NULL);
 	if (ret) {
 		dev_err(dev, "Failed to attach bridge: %d\n", ret);
@@ -691,12 +689,33 @@ static unsigned int mt8173_calculate_factor(int clock)
 		return 3 << 1;
 }
 
+static unsigned int mt2701_calculate_factor(int clock)
+{
+	if (clock <= 64000)
+		return 16;
+	else if (clock <= 128000)
+		return 8;
+	else if (clock <= 256000)
+		return 4;
+	else
+		return 2;
+}
+
 static const struct mtk_dpi_conf mt8173_conf = {
 	.cal_factor = mt8173_calculate_factor,
 	.reg_h_fre_con = 0xe0,
 };
 
+static const struct mtk_dpi_conf mt2701_conf = {
+	.cal_factor = mt2701_calculate_factor,
+	.reg_h_fre_con = 0xb0,
+	.edge_sel_en = true,
+};
+
 static const struct of_device_id mtk_dpi_of_ids[] = {
+	{ .compatible = "mediatek,mt2701-dpi",
+	  .data = &mt2701_conf,
+	},
 	{ .compatible = "mediatek,mt8173-dpi",
 	  .data = &mt8173_conf,
 	},
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 39721119713b..d961112fa2f5 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -424,6 +424,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DSI },
 	{ .compatible = "mediatek,mt8173-dsi",
 	  .data = (void *)MTK_DSI },
+	{ .compatible = "mediatek,mt2701-dpi",
+	  .data = (void *)MTK_DPI },
 	{ .compatible = "mediatek,mt8173-dpi",
 	  .data = (void *)MTK_DPI },
 	{ .compatible = "mediatek,mt2701-disp-mutex",
-- 
2.12.5.2.gbdf23ab

[PATCH v2 07/13] drm/mediatek: separae hdmi phy to different file

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

Different IC has different phy setting of HDMI.
This patch separaes the phy hardware relate part for mt8173.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/Makefile              |  15 +--
 drivers/gpu/drm/mediatek/mtk_hdmi.c            |  30 +++--
 drivers/gpu/drm/mediatek/mtk_hdmi.h            |  26 +++++
 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c        | 154 +++++++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 129 ++-------------------
 5 files changed, 216 insertions(+), 138 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index ce83c396a742..7f947979d68f 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -1,4 +1,12 @@
 # SPDX-License-Identifier: GPL-2.0
+mediatek-drm-hdmi-objs := mtk_cec.o \
+			  mtk_hdmi.o \
+			  mtk_hdmi_ddc.o \
+			  mtk_mt8173_hdmi_phy.o \
+			  mtk_hdmi_phy.o
+
+obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
+
 mediatek-drm-y := mtk_disp_color.o \
 		  mtk_disp_ovl.o \
 		  mtk_disp_rdma.o \
@@ -14,10 +22,3 @@ mediatek-drm-y := mtk_disp_color.o \
 		  mtk_dpi.o
 
 obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
-
-mediatek-drm-hdmi-objs := mtk_cec.o \
-			  mtk_hdmi.o \
-			  mtk_hdmi_ddc.o \
-			  mtk_mt8173_hdmi_phy.o
-
-obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 2d45d1dd9554..7c022f3f53ec 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -233,6 +233,7 @@ static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
 static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
 {
 	struct arm_smccc_res res;
+	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(hdmi->phy);
 
 	/*
 	 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI
@@ -240,8 +241,13 @@ static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
 	 * The ARM trusted firmware provides an API for the HDMI driver to set
 	 * this control bit to enable HDMI output in supervisor mode.
 	 */
-	arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, 0x80000000,
-		      0, 0, 0, 0, 0, &res);
+	if (hdmi_phy->conf && hdmi_phy->conf->tz_enabled)
+		arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904,
+			      0x80000000, 0, 0, 0, 0, 0, &res);
+	else
+		regmap_update_bits(hdmi->sys_regmap,
+				   hdmi->sys_offset + HDMI_SYS_CFG20,
+				   0x80008005, enable ? 0x80000005 : 0x8000);
 
 	regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 			   HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
@@ -1437,6 +1443,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
 	struct platform_device *cec_pdev;
 	struct regmap *regmap;
 	struct resource *mem;
+	const char *phy_name;
 	int ret;
 
 	ret = mtk_hdmi_get_all_clk(hdmi, np);
@@ -1445,6 +1452,18 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
 		return ret;
 	}
 
+	ret = of_property_read_string(np, "phy-names", &phy_name);
+	if (ret < 0) {
+		dev_err(dev, "Failed to read phy-names: %d\n", ret);
+		return ret;
+	}
+	hdmi->phy = devm_phy_get(dev, phy_name);
+	if (IS_ERR(hdmi->phy)) {
+		ret = PTR_ERR(hdmi->phy);
+		dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
+		return ret;
+	}
+
 	/* The CEC module handles HDMI hotplug detection */
 	cec_np = of_find_compatible_node(np->parent, NULL,
 					 "mediatek,mt8173-cec");
@@ -1677,13 +1696,6 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
-	hdmi->phy = devm_phy_get(dev, "hdmi");
-	if (IS_ERR(hdmi->phy)) {
-		ret = PTR_ERR(hdmi->phy);
-		dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
-		return ret;
-	}
-
 	platform_set_drvdata(pdev, hdmi);
 
 	ret = mtk_hdmi_output_init(hdmi);
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.h b/drivers/gpu/drm/mediatek/mtk_hdmi.h
index 6371b3de1ff6..a350a6c9271f 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.h
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.h
@@ -13,11 +13,37 @@
  */
 #ifndef _MTK_HDMI_CTRL_H
 #define _MTK_HDMI_CTRL_H
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+
+struct mtk_hdmi_phy_conf {
+	bool tz_enabled;
+	const struct clk_ops *hdmi_phy_clk_ops;
+	const struct phy_ops *hdmi_phy_dev_ops;
+};
+
+struct mtk_hdmi_phy {
+	void __iomem *regs;
+	struct device *dev;
+	struct mtk_hdmi_phy_conf *conf;
+	struct clk *pll;
+	struct clk_hw pll_hw;
+	unsigned long pll_rate;
+	unsigned char drv_imp_clk;
+	unsigned char drv_imp_d2;
+	unsigned char drv_imp_d1;
+	unsigned char drv_imp_d0;
+	unsigned int ibias;
+	unsigned int ibias_up;
+};
 
 struct platform_driver;
 
 extern struct platform_driver mtk_cec_driver;
 extern struct platform_driver mtk_hdmi_ddc_driver;
 extern struct platform_driver mtk_hdmi_phy_driver;
+extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
 
 #endif /* _MTK_HDMI_CTRL_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
new file mode 100644
index 000000000000..82ed73575e04
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Jie Qiu <jie.qiu@mediatek.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include "mtk_hdmi.h"
+
+static void mtk_hdmi_phy_clk_get_ops(struct mtk_hdmi_phy *hdmi_phy,
+				     const struct clk_ops **ops)
+{
+	if (hdmi_phy && hdmi_phy->conf && hdmi_phy->conf->hdmi_phy_clk_ops)
+		*ops = hdmi_phy->conf->hdmi_phy_clk_ops;
+	else
+		dev_err(hdmi_phy->dev, "Failed to get clk ops of phy\n");
+}
+
+static const struct phy_ops *
+mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy)
+{
+	if (hdmi_phy && hdmi_phy->conf && hdmi_phy->conf->hdmi_phy_dev_ops)
+		return hdmi_phy->conf->hdmi_phy_dev_ops;
+	dev_err(hdmi_phy->dev, "Failed to get dev ops of phy\n");
+		return NULL;
+}
+
+static int mtk_hdmi_phy_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct mtk_hdmi_phy *hdmi_phy;
+	struct resource *mem;
+	struct clk *ref_clk;
+	const char *ref_clk_name;
+	struct clk_init_data clk_init = {
+		.num_parents = 1,
+		.parent_names = (const char * const *)&ref_clk_name,
+		.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+	};
+
+	struct phy *phy;
+	struct phy_provider *phy_provider;
+	int ret;
+
+	hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
+	if (!hdmi_phy)
+		return -ENOMEM;
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	hdmi_phy->regs = devm_ioremap_resource(dev, mem);
+	if (IS_ERR(hdmi_phy->regs)) {
+		ret = PTR_ERR(hdmi_phy->regs);
+		dev_err(dev, "Failed to get memory resource: %d\n", ret);
+		return ret;
+	}
+
+	ref_clk = devm_clk_get(dev, "pll_ref");
+	if (IS_ERR(ref_clk)) {
+		ret = PTR_ERR(ref_clk);
+		dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
+			ret);
+		return ret;
+	}
+	ref_clk_name = __clk_get_name(ref_clk);
+
+	ret = of_property_read_string(dev->of_node, "clock-output-names",
+				      &clk_init.name);
+	if (ret < 0) {
+		dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
+		return ret;
+	}
+
+	hdmi_phy->dev = dev;
+	hdmi_phy->conf =
+		(struct mtk_hdmi_phy_conf *)of_device_get_match_data(dev);
+	mtk_hdmi_phy_clk_get_ops(hdmi_phy, &clk_init.ops);
+	hdmi_phy->pll_hw.init = &clk_init;
+	hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
+	if (IS_ERR(hdmi_phy->pll)) {
+		ret = PTR_ERR(hdmi_phy->pll);
+		dev_err(dev, "Failed to register PLL: %d\n", ret);
+		return ret;
+	}
+
+	ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
+				   &hdmi_phy->ibias);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
+		return ret;
+	}
+
+	ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
+				   &hdmi_phy->ibias_up);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
+		return ret;
+	}
+
+	dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
+	hdmi_phy->drv_imp_clk = 0x30;
+	hdmi_phy->drv_imp_d2 = 0x30;
+	hdmi_phy->drv_imp_d1 = 0x30;
+	hdmi_phy->drv_imp_d0 = 0x30;
+
+	phy = devm_phy_create(dev, NULL, mtk_hdmi_phy_dev_get_ops(hdmi_phy));
+	if (IS_ERR(phy)) {
+		dev_err(dev, "Failed to create HDMI PHY\n");
+		return PTR_ERR(phy);
+	}
+	phy_set_drvdata(phy, hdmi_phy);
+
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+	if (IS_ERR(phy_provider)) {
+		dev_err(dev, "Failed to register HDMI PHY\n");
+		return PTR_ERR(phy_provider);
+	}
+
+	return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
+				   hdmi_phy->pll);
+}
+
+static int mtk_hdmi_phy_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static const struct of_device_id mtk_hdmi_phy_match[] = {
+	{ .compatible = "mediatek,mt8173-hdmi-phy",
+	  .data = &mtk_hdmi_phy_8173_conf,
+	},
+	{},
+};
+
+struct platform_driver mtk_hdmi_phy_driver = {
+	.probe = mtk_hdmi_phy_probe,
+	.remove = mtk_hdmi_phy_remove,
+	.driver = {
+		.name = "mediatek-hdmi-phy",
+		.of_match_table = mtk_hdmi_phy_match,
+	},
+};
+
+MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
index 51cb9cfb6646..1a35fdd405d8 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
@@ -21,6 +21,7 @@
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
 #include <linux/types.h>
+#include "mtk_hdmi.h"
 
 #define HDMI_CON0		0x00
 #define RG_HDMITX_PLL_EN		BIT(31)
@@ -123,20 +124,6 @@
 #define RGS_HDMITX_5T1_EDG		(0xf << 4)
 #define RGS_HDMITX_PLUG_TST		BIT(0)
 
-struct mtk_hdmi_phy {
-	void __iomem *regs;
-	struct device *dev;
-	struct clk *pll;
-	struct clk_hw pll_hw;
-	unsigned long pll_rate;
-	u8 drv_imp_clk;
-	u8 drv_imp_d2;
-	u8 drv_imp_d1;
-	u8 drv_imp_d0;
-	u32 ibias;
-	u32 ibias_up;
-};
-
 static const u8 PREDIV[3][4] = {
 	{0x0, 0x0, 0x0, 0x0},	/* 27Mhz */
 	{0x1, 0x1, 0x1, 0x1},	/* 74Mhz */
@@ -367,7 +354,7 @@ static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
 	return hdmi_phy->pll_rate;
 }
 
-static const struct clk_ops mtk_hdmi_pll_ops = {
+static const struct clk_ops mtk_hdmi_phy_pll_ops = {
 	.prepare = mtk_hdmi_pll_prepare,
 	.unprepare = mtk_hdmi_pll_unprepare,
 	.set_rate = mtk_hdmi_pll_set_rate,
@@ -414,118 +401,16 @@ static int mtk_hdmi_phy_power_off(struct phy *phy)
 	return 0;
 }
 
-static const struct phy_ops mtk_hdmi_phy_ops = {
+static const struct phy_ops mtk_hdmi_phy_dev_ops = {
 	.power_on = mtk_hdmi_phy_power_on,
 	.power_off = mtk_hdmi_phy_power_off,
 	.owner = THIS_MODULE,
 };
 
-static int mtk_hdmi_phy_probe(struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-	struct mtk_hdmi_phy *hdmi_phy;
-	struct resource *mem;
-	struct clk *ref_clk;
-	const char *ref_clk_name;
-	struct clk_init_data clk_init = {
-		.ops = &mtk_hdmi_pll_ops,
-		.num_parents = 1,
-		.parent_names = (const char * const *)&ref_clk_name,
-		.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
-	};
-	struct phy *phy;
-	struct phy_provider *phy_provider;
-	int ret;
-
-	hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
-	if (!hdmi_phy)
-		return -ENOMEM;
-
-	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	hdmi_phy->regs = devm_ioremap_resource(dev, mem);
-	if (IS_ERR(hdmi_phy->regs)) {
-		ret = PTR_ERR(hdmi_phy->regs);
-		dev_err(dev, "Failed to get memory resource: %d\n", ret);
-		return ret;
-	}
-
-	ref_clk = devm_clk_get(dev, "pll_ref");
-	if (IS_ERR(ref_clk)) {
-		ret = PTR_ERR(ref_clk);
-		dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
-			ret);
-		return ret;
-	}
-	ref_clk_name = __clk_get_name(ref_clk);
-
-	ret = of_property_read_string(dev->of_node, "clock-output-names",
-				      &clk_init.name);
-	if (ret < 0) {
-		dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
-		return ret;
-	}
-
-	hdmi_phy->pll_hw.init = &clk_init;
-	hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
-	if (IS_ERR(hdmi_phy->pll)) {
-		ret = PTR_ERR(hdmi_phy->pll);
-		dev_err(dev, "Failed to register PLL: %d\n", ret);
-		return ret;
-	}
-
-	ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
-				   &hdmi_phy->ibias);
-	if (ret < 0) {
-		dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
-		return ret;
-	}
-
-	ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
-				   &hdmi_phy->ibias_up);
-	if (ret < 0) {
-		dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
-		return ret;
-	}
-
-	dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
-	hdmi_phy->drv_imp_clk = 0x30;
-	hdmi_phy->drv_imp_d2 = 0x30;
-	hdmi_phy->drv_imp_d1 = 0x30;
-	hdmi_phy->drv_imp_d0 = 0x30;
-
-	phy = devm_phy_create(dev, NULL, &mtk_hdmi_phy_ops);
-	if (IS_ERR(phy)) {
-		dev_err(dev, "Failed to create HDMI PHY\n");
-		return PTR_ERR(phy);
-	}
-	phy_set_drvdata(phy, hdmi_phy);
-
-	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-	if (IS_ERR(phy_provider))
-		return PTR_ERR(phy_provider);
-
-	hdmi_phy->dev = dev;
-	return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
-				   hdmi_phy->pll);
-}
-
-static int mtk_hdmi_phy_remove(struct platform_device *pdev)
-{
-	return 0;
-}
-
-static const struct of_device_id mtk_hdmi_phy_match[] = {
-	{ .compatible = "mediatek,mt8173-hdmi-phy", },
-	{},
-};
-
-struct platform_driver mtk_hdmi_phy_driver = {
-	.probe = mtk_hdmi_phy_probe,
-	.remove = mtk_hdmi_phy_remove,
-	.driver = {
-		.name = "mediatek-hdmi-phy",
-		.of_match_table = mtk_hdmi_phy_match,
-	},
+struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = {
+	.tz_enabled = true,
+	.hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
+	.hdmi_phy_dev_ops = &mtk_hdmi_phy_dev_ops,
 };
 
 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
-- 
2.12.5.2.gbdf23ab

[PATCH v2 07/13] drm/mediatek: separae hdmi phy to different file

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

Different IC has different phy setting of HDMI.
This patch separaes the phy hardware relate part for mt8173.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/Makefile              |  15 +--
 drivers/gpu/drm/mediatek/mtk_hdmi.c            |  30 +++--
 drivers/gpu/drm/mediatek/mtk_hdmi.h            |  26 +++++
 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c        | 154 +++++++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 129 ++-------------------
 5 files changed, 216 insertions(+), 138 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index ce83c396a742..7f947979d68f 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -1,4 +1,12 @@
 # SPDX-License-Identifier: GPL-2.0
+mediatek-drm-hdmi-objs := mtk_cec.o \
+			  mtk_hdmi.o \
+			  mtk_hdmi_ddc.o \
+			  mtk_mt8173_hdmi_phy.o \
+			  mtk_hdmi_phy.o
+
+obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
+
 mediatek-drm-y := mtk_disp_color.o \
 		  mtk_disp_ovl.o \
 		  mtk_disp_rdma.o \
@@ -14,10 +22,3 @@ mediatek-drm-y := mtk_disp_color.o \
 		  mtk_dpi.o
 
 obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
-
-mediatek-drm-hdmi-objs := mtk_cec.o \
-			  mtk_hdmi.o \
-			  mtk_hdmi_ddc.o \
-			  mtk_mt8173_hdmi_phy.o
-
-obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 2d45d1dd9554..7c022f3f53ec 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -233,6 +233,7 @@ static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
 static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
 {
 	struct arm_smccc_res res;
+	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(hdmi->phy);
 
 	/*
 	 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI
@@ -240,8 +241,13 @@ static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
 	 * The ARM trusted firmware provides an API for the HDMI driver to set
 	 * this control bit to enable HDMI output in supervisor mode.
 	 */
-	arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, 0x80000000,
-		      0, 0, 0, 0, 0, &res);
+	if (hdmi_phy->conf && hdmi_phy->conf->tz_enabled)
+		arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904,
+			      0x80000000, 0, 0, 0, 0, 0, &res);
+	else
+		regmap_update_bits(hdmi->sys_regmap,
+				   hdmi->sys_offset + HDMI_SYS_CFG20,
+				   0x80008005, enable ? 0x80000005 : 0x8000);
 
 	regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 			   HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
@@ -1437,6 +1443,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
 	struct platform_device *cec_pdev;
 	struct regmap *regmap;
 	struct resource *mem;
+	const char *phy_name;
 	int ret;
 
 	ret = mtk_hdmi_get_all_clk(hdmi, np);
@@ -1445,6 +1452,18 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
 		return ret;
 	}
 
+	ret = of_property_read_string(np, "phy-names", &phy_name);
+	if (ret < 0) {
+		dev_err(dev, "Failed to read phy-names: %d\n", ret);
+		return ret;
+	}
+	hdmi->phy = devm_phy_get(dev, phy_name);
+	if (IS_ERR(hdmi->phy)) {
+		ret = PTR_ERR(hdmi->phy);
+		dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
+		return ret;
+	}
+
 	/* The CEC module handles HDMI hotplug detection */
 	cec_np = of_find_compatible_node(np->parent, NULL,
 					 "mediatek,mt8173-cec");
@@ -1677,13 +1696,6 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
-	hdmi->phy = devm_phy_get(dev, "hdmi");
-	if (IS_ERR(hdmi->phy)) {
-		ret = PTR_ERR(hdmi->phy);
-		dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
-		return ret;
-	}
-
 	platform_set_drvdata(pdev, hdmi);
 
 	ret = mtk_hdmi_output_init(hdmi);
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.h b/drivers/gpu/drm/mediatek/mtk_hdmi.h
index 6371b3de1ff6..a350a6c9271f 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.h
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.h
@@ -13,11 +13,37 @@
  */
 #ifndef _MTK_HDMI_CTRL_H
 #define _MTK_HDMI_CTRL_H
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+
+struct mtk_hdmi_phy_conf {
+	bool tz_enabled;
+	const struct clk_ops *hdmi_phy_clk_ops;
+	const struct phy_ops *hdmi_phy_dev_ops;
+};
+
+struct mtk_hdmi_phy {
+	void __iomem *regs;
+	struct device *dev;
+	struct mtk_hdmi_phy_conf *conf;
+	struct clk *pll;
+	struct clk_hw pll_hw;
+	unsigned long pll_rate;
+	unsigned char drv_imp_clk;
+	unsigned char drv_imp_d2;
+	unsigned char drv_imp_d1;
+	unsigned char drv_imp_d0;
+	unsigned int ibias;
+	unsigned int ibias_up;
+};
 
 struct platform_driver;
 
 extern struct platform_driver mtk_cec_driver;
 extern struct platform_driver mtk_hdmi_ddc_driver;
 extern struct platform_driver mtk_hdmi_phy_driver;
+extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
 
 #endif /* _MTK_HDMI_CTRL_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
new file mode 100644
index 000000000000..82ed73575e04
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Jie Qiu <jie.qiu@mediatek.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include "mtk_hdmi.h"
+
+static void mtk_hdmi_phy_clk_get_ops(struct mtk_hdmi_phy *hdmi_phy,
+				     const struct clk_ops **ops)
+{
+	if (hdmi_phy && hdmi_phy->conf && hdmi_phy->conf->hdmi_phy_clk_ops)
+		*ops = hdmi_phy->conf->hdmi_phy_clk_ops;
+	else
+		dev_err(hdmi_phy->dev, "Failed to get clk ops of phy\n");
+}
+
+static const struct phy_ops *
+mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy)
+{
+	if (hdmi_phy && hdmi_phy->conf && hdmi_phy->conf->hdmi_phy_dev_ops)
+		return hdmi_phy->conf->hdmi_phy_dev_ops;
+	dev_err(hdmi_phy->dev, "Failed to get dev ops of phy\n");
+		return NULL;
+}
+
+static int mtk_hdmi_phy_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct mtk_hdmi_phy *hdmi_phy;
+	struct resource *mem;
+	struct clk *ref_clk;
+	const char *ref_clk_name;
+	struct clk_init_data clk_init = {
+		.num_parents = 1,
+		.parent_names = (const char * const *)&ref_clk_name,
+		.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+	};
+
+	struct phy *phy;
+	struct phy_provider *phy_provider;
+	int ret;
+
+	hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
+	if (!hdmi_phy)
+		return -ENOMEM;
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	hdmi_phy->regs = devm_ioremap_resource(dev, mem);
+	if (IS_ERR(hdmi_phy->regs)) {
+		ret = PTR_ERR(hdmi_phy->regs);
+		dev_err(dev, "Failed to get memory resource: %d\n", ret);
+		return ret;
+	}
+
+	ref_clk = devm_clk_get(dev, "pll_ref");
+	if (IS_ERR(ref_clk)) {
+		ret = PTR_ERR(ref_clk);
+		dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
+			ret);
+		return ret;
+	}
+	ref_clk_name = __clk_get_name(ref_clk);
+
+	ret = of_property_read_string(dev->of_node, "clock-output-names",
+				      &clk_init.name);
+	if (ret < 0) {
+		dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
+		return ret;
+	}
+
+	hdmi_phy->dev = dev;
+	hdmi_phy->conf =
+		(struct mtk_hdmi_phy_conf *)of_device_get_match_data(dev);
+	mtk_hdmi_phy_clk_get_ops(hdmi_phy, &clk_init.ops);
+	hdmi_phy->pll_hw.init = &clk_init;
+	hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
+	if (IS_ERR(hdmi_phy->pll)) {
+		ret = PTR_ERR(hdmi_phy->pll);
+		dev_err(dev, "Failed to register PLL: %d\n", ret);
+		return ret;
+	}
+
+	ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
+				   &hdmi_phy->ibias);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
+		return ret;
+	}
+
+	ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
+				   &hdmi_phy->ibias_up);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
+		return ret;
+	}
+
+	dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
+	hdmi_phy->drv_imp_clk = 0x30;
+	hdmi_phy->drv_imp_d2 = 0x30;
+	hdmi_phy->drv_imp_d1 = 0x30;
+	hdmi_phy->drv_imp_d0 = 0x30;
+
+	phy = devm_phy_create(dev, NULL, mtk_hdmi_phy_dev_get_ops(hdmi_phy));
+	if (IS_ERR(phy)) {
+		dev_err(dev, "Failed to create HDMI PHY\n");
+		return PTR_ERR(phy);
+	}
+	phy_set_drvdata(phy, hdmi_phy);
+
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+	if (IS_ERR(phy_provider)) {
+		dev_err(dev, "Failed to register HDMI PHY\n");
+		return PTR_ERR(phy_provider);
+	}
+
+	return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
+				   hdmi_phy->pll);
+}
+
+static int mtk_hdmi_phy_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static const struct of_device_id mtk_hdmi_phy_match[] = {
+	{ .compatible = "mediatek,mt8173-hdmi-phy",
+	  .data = &mtk_hdmi_phy_8173_conf,
+	},
+	{},
+};
+
+struct platform_driver mtk_hdmi_phy_driver = {
+	.probe = mtk_hdmi_phy_probe,
+	.remove = mtk_hdmi_phy_remove,
+	.driver = {
+		.name = "mediatek-hdmi-phy",
+		.of_match_table = mtk_hdmi_phy_match,
+	},
+};
+
+MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
index 51cb9cfb6646..1a35fdd405d8 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
@@ -21,6 +21,7 @@
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
 #include <linux/types.h>
+#include "mtk_hdmi.h"
 
 #define HDMI_CON0		0x00
 #define RG_HDMITX_PLL_EN		BIT(31)
@@ -123,20 +124,6 @@
 #define RGS_HDMITX_5T1_EDG		(0xf << 4)
 #define RGS_HDMITX_PLUG_TST		BIT(0)
 
-struct mtk_hdmi_phy {
-	void __iomem *regs;
-	struct device *dev;
-	struct clk *pll;
-	struct clk_hw pll_hw;
-	unsigned long pll_rate;
-	u8 drv_imp_clk;
-	u8 drv_imp_d2;
-	u8 drv_imp_d1;
-	u8 drv_imp_d0;
-	u32 ibias;
-	u32 ibias_up;
-};
-
 static const u8 PREDIV[3][4] = {
 	{0x0, 0x0, 0x0, 0x0},	/* 27Mhz */
 	{0x1, 0x1, 0x1, 0x1},	/* 74Mhz */
@@ -367,7 +354,7 @@ static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
 	return hdmi_phy->pll_rate;
 }
 
-static const struct clk_ops mtk_hdmi_pll_ops = {
+static const struct clk_ops mtk_hdmi_phy_pll_ops = {
 	.prepare = mtk_hdmi_pll_prepare,
 	.unprepare = mtk_hdmi_pll_unprepare,
 	.set_rate = mtk_hdmi_pll_set_rate,
@@ -414,118 +401,16 @@ static int mtk_hdmi_phy_power_off(struct phy *phy)
 	return 0;
 }
 
-static const struct phy_ops mtk_hdmi_phy_ops = {
+static const struct phy_ops mtk_hdmi_phy_dev_ops = {
 	.power_on = mtk_hdmi_phy_power_on,
 	.power_off = mtk_hdmi_phy_power_off,
 	.owner = THIS_MODULE,
 };
 
-static int mtk_hdmi_phy_probe(struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-	struct mtk_hdmi_phy *hdmi_phy;
-	struct resource *mem;
-	struct clk *ref_clk;
-	const char *ref_clk_name;
-	struct clk_init_data clk_init = {
-		.ops = &mtk_hdmi_pll_ops,
-		.num_parents = 1,
-		.parent_names = (const char * const *)&ref_clk_name,
-		.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
-	};
-	struct phy *phy;
-	struct phy_provider *phy_provider;
-	int ret;
-
-	hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
-	if (!hdmi_phy)
-		return -ENOMEM;
-
-	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	hdmi_phy->regs = devm_ioremap_resource(dev, mem);
-	if (IS_ERR(hdmi_phy->regs)) {
-		ret = PTR_ERR(hdmi_phy->regs);
-		dev_err(dev, "Failed to get memory resource: %d\n", ret);
-		return ret;
-	}
-
-	ref_clk = devm_clk_get(dev, "pll_ref");
-	if (IS_ERR(ref_clk)) {
-		ret = PTR_ERR(ref_clk);
-		dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
-			ret);
-		return ret;
-	}
-	ref_clk_name = __clk_get_name(ref_clk);
-
-	ret = of_property_read_string(dev->of_node, "clock-output-names",
-				      &clk_init.name);
-	if (ret < 0) {
-		dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
-		return ret;
-	}
-
-	hdmi_phy->pll_hw.init = &clk_init;
-	hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
-	if (IS_ERR(hdmi_phy->pll)) {
-		ret = PTR_ERR(hdmi_phy->pll);
-		dev_err(dev, "Failed to register PLL: %d\n", ret);
-		return ret;
-	}
-
-	ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
-				   &hdmi_phy->ibias);
-	if (ret < 0) {
-		dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
-		return ret;
-	}
-
-	ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
-				   &hdmi_phy->ibias_up);
-	if (ret < 0) {
-		dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
-		return ret;
-	}
-
-	dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
-	hdmi_phy->drv_imp_clk = 0x30;
-	hdmi_phy->drv_imp_d2 = 0x30;
-	hdmi_phy->drv_imp_d1 = 0x30;
-	hdmi_phy->drv_imp_d0 = 0x30;
-
-	phy = devm_phy_create(dev, NULL, &mtk_hdmi_phy_ops);
-	if (IS_ERR(phy)) {
-		dev_err(dev, "Failed to create HDMI PHY\n");
-		return PTR_ERR(phy);
-	}
-	phy_set_drvdata(phy, hdmi_phy);
-
-	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-	if (IS_ERR(phy_provider))
-		return PTR_ERR(phy_provider);
-
-	hdmi_phy->dev = dev;
-	return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
-				   hdmi_phy->pll);
-}
-
-static int mtk_hdmi_phy_remove(struct platform_device *pdev)
-{
-	return 0;
-}
-
-static const struct of_device_id mtk_hdmi_phy_match[] = {
-	{ .compatible = "mediatek,mt8173-hdmi-phy", },
-	{},
-};
-
-struct platform_driver mtk_hdmi_phy_driver = {
-	.probe = mtk_hdmi_phy_probe,
-	.remove = mtk_hdmi_phy_remove,
-	.driver = {
-		.name = "mediatek-hdmi-phy",
-		.of_match_table = mtk_hdmi_phy_match,
-	},
+struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = {
+	.tz_enabled = true,
+	.hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
+	.hdmi_phy_dev_ops = &mtk_hdmi_phy_dev_ops,
 };
 
 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
-- 
2.12.5.2.gbdf23ab

[PATCH v2 07/13] drm/mediatek: separae hdmi phy to different file

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

Different IC has different phy setting of HDMI.
This patch separaes the phy hardware relate part for mt8173.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/Makefile              |  15 +--
 drivers/gpu/drm/mediatek/mtk_hdmi.c            |  30 +++--
 drivers/gpu/drm/mediatek/mtk_hdmi.h            |  26 +++++
 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c        | 154 +++++++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 129 ++-------------------
 5 files changed, 216 insertions(+), 138 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index ce83c396a742..7f947979d68f 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -1,4 +1,12 @@
 # SPDX-License-Identifier: GPL-2.0
+mediatek-drm-hdmi-objs := mtk_cec.o \
+			  mtk_hdmi.o \
+			  mtk_hdmi_ddc.o \
+			  mtk_mt8173_hdmi_phy.o \
+			  mtk_hdmi_phy.o
+
+obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
+
 mediatek-drm-y := mtk_disp_color.o \
 		  mtk_disp_ovl.o \
 		  mtk_disp_rdma.o \
@@ -14,10 +22,3 @@ mediatek-drm-y := mtk_disp_color.o \
 		  mtk_dpi.o
 
 obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
-
-mediatek-drm-hdmi-objs := mtk_cec.o \
-			  mtk_hdmi.o \
-			  mtk_hdmi_ddc.o \
-			  mtk_mt8173_hdmi_phy.o
-
-obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 2d45d1dd9554..7c022f3f53ec 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -233,6 +233,7 @@ static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
 static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
 {
 	struct arm_smccc_res res;
+	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(hdmi->phy);
 
 	/*
 	 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI
@@ -240,8 +241,13 @@ static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
 	 * The ARM trusted firmware provides an API for the HDMI driver to set
 	 * this control bit to enable HDMI output in supervisor mode.
 	 */
-	arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, 0x80000000,
-		      0, 0, 0, 0, 0, &res);
+	if (hdmi_phy->conf && hdmi_phy->conf->tz_enabled)
+		arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904,
+			      0x80000000, 0, 0, 0, 0, 0, &res);
+	else
+		regmap_update_bits(hdmi->sys_regmap,
+				   hdmi->sys_offset + HDMI_SYS_CFG20,
+				   0x80008005, enable ? 0x80000005 : 0x8000);
 
 	regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 			   HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
@@ -1437,6 +1443,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
 	struct platform_device *cec_pdev;
 	struct regmap *regmap;
 	struct resource *mem;
+	const char *phy_name;
 	int ret;
 
 	ret = mtk_hdmi_get_all_clk(hdmi, np);
@@ -1445,6 +1452,18 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
 		return ret;
 	}
 
+	ret = of_property_read_string(np, "phy-names", &phy_name);
+	if (ret < 0) {
+		dev_err(dev, "Failed to read phy-names: %d\n", ret);
+		return ret;
+	}
+	hdmi->phy = devm_phy_get(dev, phy_name);
+	if (IS_ERR(hdmi->phy)) {
+		ret = PTR_ERR(hdmi->phy);
+		dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
+		return ret;
+	}
+
 	/* The CEC module handles HDMI hotplug detection */
 	cec_np = of_find_compatible_node(np->parent, NULL,
 					 "mediatek,mt8173-cec");
@@ -1677,13 +1696,6 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
-	hdmi->phy = devm_phy_get(dev, "hdmi");
-	if (IS_ERR(hdmi->phy)) {
-		ret = PTR_ERR(hdmi->phy);
-		dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
-		return ret;
-	}
-
 	platform_set_drvdata(pdev, hdmi);
 
 	ret = mtk_hdmi_output_init(hdmi);
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.h b/drivers/gpu/drm/mediatek/mtk_hdmi.h
index 6371b3de1ff6..a350a6c9271f 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.h
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.h
@@ -13,11 +13,37 @@
  */
 #ifndef _MTK_HDMI_CTRL_H
 #define _MTK_HDMI_CTRL_H
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+
+struct mtk_hdmi_phy_conf {
+	bool tz_enabled;
+	const struct clk_ops *hdmi_phy_clk_ops;
+	const struct phy_ops *hdmi_phy_dev_ops;
+};
+
+struct mtk_hdmi_phy {
+	void __iomem *regs;
+	struct device *dev;
+	struct mtk_hdmi_phy_conf *conf;
+	struct clk *pll;
+	struct clk_hw pll_hw;
+	unsigned long pll_rate;
+	unsigned char drv_imp_clk;
+	unsigned char drv_imp_d2;
+	unsigned char drv_imp_d1;
+	unsigned char drv_imp_d0;
+	unsigned int ibias;
+	unsigned int ibias_up;
+};
 
 struct platform_driver;
 
 extern struct platform_driver mtk_cec_driver;
 extern struct platform_driver mtk_hdmi_ddc_driver;
 extern struct platform_driver mtk_hdmi_phy_driver;
+extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
 
 #endif /* _MTK_HDMI_CTRL_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
new file mode 100644
index 000000000000..82ed73575e04
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Jie Qiu <jie.qiu@mediatek.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include "mtk_hdmi.h"
+
+static void mtk_hdmi_phy_clk_get_ops(struct mtk_hdmi_phy *hdmi_phy,
+				     const struct clk_ops **ops)
+{
+	if (hdmi_phy && hdmi_phy->conf && hdmi_phy->conf->hdmi_phy_clk_ops)
+		*ops = hdmi_phy->conf->hdmi_phy_clk_ops;
+	else
+		dev_err(hdmi_phy->dev, "Failed to get clk ops of phy\n");
+}
+
+static const struct phy_ops *
+mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy)
+{
+	if (hdmi_phy && hdmi_phy->conf && hdmi_phy->conf->hdmi_phy_dev_ops)
+		return hdmi_phy->conf->hdmi_phy_dev_ops;
+	dev_err(hdmi_phy->dev, "Failed to get dev ops of phy\n");
+		return NULL;
+}
+
+static int mtk_hdmi_phy_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct mtk_hdmi_phy *hdmi_phy;
+	struct resource *mem;
+	struct clk *ref_clk;
+	const char *ref_clk_name;
+	struct clk_init_data clk_init = {
+		.num_parents = 1,
+		.parent_names = (const char * const *)&ref_clk_name,
+		.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+	};
+
+	struct phy *phy;
+	struct phy_provider *phy_provider;
+	int ret;
+
+	hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
+	if (!hdmi_phy)
+		return -ENOMEM;
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	hdmi_phy->regs = devm_ioremap_resource(dev, mem);
+	if (IS_ERR(hdmi_phy->regs)) {
+		ret = PTR_ERR(hdmi_phy->regs);
+		dev_err(dev, "Failed to get memory resource: %d\n", ret);
+		return ret;
+	}
+
+	ref_clk = devm_clk_get(dev, "pll_ref");
+	if (IS_ERR(ref_clk)) {
+		ret = PTR_ERR(ref_clk);
+		dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
+			ret);
+		return ret;
+	}
+	ref_clk_name = __clk_get_name(ref_clk);
+
+	ret = of_property_read_string(dev->of_node, "clock-output-names",
+				      &clk_init.name);
+	if (ret < 0) {
+		dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
+		return ret;
+	}
+
+	hdmi_phy->dev = dev;
+	hdmi_phy->conf =
+		(struct mtk_hdmi_phy_conf *)of_device_get_match_data(dev);
+	mtk_hdmi_phy_clk_get_ops(hdmi_phy, &clk_init.ops);
+	hdmi_phy->pll_hw.init = &clk_init;
+	hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
+	if (IS_ERR(hdmi_phy->pll)) {
+		ret = PTR_ERR(hdmi_phy->pll);
+		dev_err(dev, "Failed to register PLL: %d\n", ret);
+		return ret;
+	}
+
+	ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
+				   &hdmi_phy->ibias);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
+		return ret;
+	}
+
+	ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
+				   &hdmi_phy->ibias_up);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
+		return ret;
+	}
+
+	dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
+	hdmi_phy->drv_imp_clk = 0x30;
+	hdmi_phy->drv_imp_d2 = 0x30;
+	hdmi_phy->drv_imp_d1 = 0x30;
+	hdmi_phy->drv_imp_d0 = 0x30;
+
+	phy = devm_phy_create(dev, NULL, mtk_hdmi_phy_dev_get_ops(hdmi_phy));
+	if (IS_ERR(phy)) {
+		dev_err(dev, "Failed to create HDMI PHY\n");
+		return PTR_ERR(phy);
+	}
+	phy_set_drvdata(phy, hdmi_phy);
+
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+	if (IS_ERR(phy_provider)) {
+		dev_err(dev, "Failed to register HDMI PHY\n");
+		return PTR_ERR(phy_provider);
+	}
+
+	return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
+				   hdmi_phy->pll);
+}
+
+static int mtk_hdmi_phy_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static const struct of_device_id mtk_hdmi_phy_match[] = {
+	{ .compatible = "mediatek,mt8173-hdmi-phy",
+	  .data = &mtk_hdmi_phy_8173_conf,
+	},
+	{},
+};
+
+struct platform_driver mtk_hdmi_phy_driver = {
+	.probe = mtk_hdmi_phy_probe,
+	.remove = mtk_hdmi_phy_remove,
+	.driver = {
+		.name = "mediatek-hdmi-phy",
+		.of_match_table = mtk_hdmi_phy_match,
+	},
+};
+
+MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
index 51cb9cfb6646..1a35fdd405d8 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
@@ -21,6 +21,7 @@
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
 #include <linux/types.h>
+#include "mtk_hdmi.h"
 
 #define HDMI_CON0		0x00
 #define RG_HDMITX_PLL_EN		BIT(31)
@@ -123,20 +124,6 @@
 #define RGS_HDMITX_5T1_EDG		(0xf << 4)
 #define RGS_HDMITX_PLUG_TST		BIT(0)
 
-struct mtk_hdmi_phy {
-	void __iomem *regs;
-	struct device *dev;
-	struct clk *pll;
-	struct clk_hw pll_hw;
-	unsigned long pll_rate;
-	u8 drv_imp_clk;
-	u8 drv_imp_d2;
-	u8 drv_imp_d1;
-	u8 drv_imp_d0;
-	u32 ibias;
-	u32 ibias_up;
-};
-
 static const u8 PREDIV[3][4] = {
 	{0x0, 0x0, 0x0, 0x0},	/* 27Mhz */
 	{0x1, 0x1, 0x1, 0x1},	/* 74Mhz */
@@ -367,7 +354,7 @@ static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
 	return hdmi_phy->pll_rate;
 }
 
-static const struct clk_ops mtk_hdmi_pll_ops = {
+static const struct clk_ops mtk_hdmi_phy_pll_ops = {
 	.prepare = mtk_hdmi_pll_prepare,
 	.unprepare = mtk_hdmi_pll_unprepare,
 	.set_rate = mtk_hdmi_pll_set_rate,
@@ -414,118 +401,16 @@ static int mtk_hdmi_phy_power_off(struct phy *phy)
 	return 0;
 }
 
-static const struct phy_ops mtk_hdmi_phy_ops = {
+static const struct phy_ops mtk_hdmi_phy_dev_ops = {
 	.power_on = mtk_hdmi_phy_power_on,
 	.power_off = mtk_hdmi_phy_power_off,
 	.owner = THIS_MODULE,
 };
 
-static int mtk_hdmi_phy_probe(struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-	struct mtk_hdmi_phy *hdmi_phy;
-	struct resource *mem;
-	struct clk *ref_clk;
-	const char *ref_clk_name;
-	struct clk_init_data clk_init = {
-		.ops = &mtk_hdmi_pll_ops,
-		.num_parents = 1,
-		.parent_names = (const char * const *)&ref_clk_name,
-		.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
-	};
-	struct phy *phy;
-	struct phy_provider *phy_provider;
-	int ret;
-
-	hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
-	if (!hdmi_phy)
-		return -ENOMEM;
-
-	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	hdmi_phy->regs = devm_ioremap_resource(dev, mem);
-	if (IS_ERR(hdmi_phy->regs)) {
-		ret = PTR_ERR(hdmi_phy->regs);
-		dev_err(dev, "Failed to get memory resource: %d\n", ret);
-		return ret;
-	}
-
-	ref_clk = devm_clk_get(dev, "pll_ref");
-	if (IS_ERR(ref_clk)) {
-		ret = PTR_ERR(ref_clk);
-		dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
-			ret);
-		return ret;
-	}
-	ref_clk_name = __clk_get_name(ref_clk);
-
-	ret = of_property_read_string(dev->of_node, "clock-output-names",
-				      &clk_init.name);
-	if (ret < 0) {
-		dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
-		return ret;
-	}
-
-	hdmi_phy->pll_hw.init = &clk_init;
-	hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
-	if (IS_ERR(hdmi_phy->pll)) {
-		ret = PTR_ERR(hdmi_phy->pll);
-		dev_err(dev, "Failed to register PLL: %d\n", ret);
-		return ret;
-	}
-
-	ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
-				   &hdmi_phy->ibias);
-	if (ret < 0) {
-		dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
-		return ret;
-	}
-
-	ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
-				   &hdmi_phy->ibias_up);
-	if (ret < 0) {
-		dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
-		return ret;
-	}
-
-	dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
-	hdmi_phy->drv_imp_clk = 0x30;
-	hdmi_phy->drv_imp_d2 = 0x30;
-	hdmi_phy->drv_imp_d1 = 0x30;
-	hdmi_phy->drv_imp_d0 = 0x30;
-
-	phy = devm_phy_create(dev, NULL, &mtk_hdmi_phy_ops);
-	if (IS_ERR(phy)) {
-		dev_err(dev, "Failed to create HDMI PHY\n");
-		return PTR_ERR(phy);
-	}
-	phy_set_drvdata(phy, hdmi_phy);
-
-	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-	if (IS_ERR(phy_provider))
-		return PTR_ERR(phy_provider);
-
-	hdmi_phy->dev = dev;
-	return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
-				   hdmi_phy->pll);
-}
-
-static int mtk_hdmi_phy_remove(struct platform_device *pdev)
-{
-	return 0;
-}
-
-static const struct of_device_id mtk_hdmi_phy_match[] = {
-	{ .compatible = "mediatek,mt8173-hdmi-phy", },
-	{},
-};
-
-struct platform_driver mtk_hdmi_phy_driver = {
-	.probe = mtk_hdmi_phy_probe,
-	.remove = mtk_hdmi_phy_remove,
-	.driver = {
-		.name = "mediatek-hdmi-phy",
-		.of_match_table = mtk_hdmi_phy_match,
-	},
+struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = {
+	.tz_enabled = true,
+	.hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
+	.hdmi_phy_dev_ops = &mtk_hdmi_phy_dev_ops,
 };
 
 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
-- 
2.12.5.2.gbdf23ab

[PATCH v2 08/13] drm/mediatek: register hdmi codec more earlier

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

sometimes hdmi reprobe due to encoder probe late,
but audio dai probe earlier than hdmi. it would make
audio dai cannot find the hdmi codec. we need to
register hdmi codec earlier, and the base name which
used in the register should be PLATFORM_DEVID_NONE,
otherwise some audio dai dirver could not match it.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_hdmi.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 7c022f3f53ec..2cb33098ec1a 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1669,15 +1669,14 @@ static void mtk_hdmi_register_audio_driver(struct device *dev)
 		.max_i2s_channels = 2,
 		.i2s = 1,
 	};
-	struct platform_device *pdev;
+	static struct platform_device *pdev;
 
-	pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
-					     PLATFORM_DEVID_AUTO, &codec_data,
-					     sizeof(codec_data));
-	if (IS_ERR(pdev))
+	if (!pdev) {
+		pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
+						     PLATFORM_DEVID_NONE,
+						     &codec_data,
+						     sizeof(codec_data));
+		DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
+	}
 		return;
-
-	DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
 }
 
 static int mtk_drm_hdmi_probe(struct platform_device *pdev)
@@ -1691,6 +1690,7 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	hdmi->dev = dev;
+	mtk_hdmi_register_audio_driver(dev);
 
 	ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
 	if (ret)
@@ -1704,8 +1704,6 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	mtk_hdmi_register_audio_driver(dev);
-
 	hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
 	hdmi->bridge.of_node = pdev->dev.of_node;
 	drm_bridge_add(&hdmi->bridge);
-- 
2.12.5.2.gbdf23ab

[PATCH v2 08/13] drm/mediatek: register hdmi codec more earlier

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

sometimes hdmi reprobe due to encoder probe late,
but audio dai probe earlier than hdmi. it would make
audio dai cannot find the hdmi codec. we need to
register hdmi codec earlier, and the base name which
used in the register should be PLATFORM_DEVID_NONE,
otherwise some audio dai dirver could not match it.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_hdmi.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 7c022f3f53ec..2cb33098ec1a 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1669,15 +1669,14 @@ static void mtk_hdmi_register_audio_driver(struct device *dev)
 		.max_i2s_channels = 2,
 		.i2s = 1,
 	};
-	struct platform_device *pdev;
+	static struct platform_device *pdev;
 
-	pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
-					     PLATFORM_DEVID_AUTO, &codec_data,
-					     sizeof(codec_data));
-	if (IS_ERR(pdev))
+	if (!pdev) {
+		pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
+						     PLATFORM_DEVID_NONE,
+						     &codec_data,
+						     sizeof(codec_data));
+		DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
+	}
 		return;
-
-	DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
 }
 
 static int mtk_drm_hdmi_probe(struct platform_device *pdev)
@@ -1691,6 +1690,7 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	hdmi->dev = dev;
+	mtk_hdmi_register_audio_driver(dev);
 
 	ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
 	if (ret)
@@ -1704,8 +1704,6 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	mtk_hdmi_register_audio_driver(dev);
-
 	hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
 	hdmi->bridge.of_node = pdev->dev.of_node;
 	drm_bridge_add(&hdmi->bridge);
-- 
2.12.5.2.gbdf23ab

[PATCH v2 08/13] drm/mediatek: register hdmi codec more earlier

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

sometimes hdmi reprobe due to encoder probe late,
but audio dai probe earlier than hdmi. it would make
audio dai cannot find the hdmi codec. we need to
register hdmi codec earlier, and the base name which
used in the register should be PLATFORM_DEVID_NONE,
otherwise some audio dai dirver could not match it.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_hdmi.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 7c022f3f53ec..2cb33098ec1a 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1669,15 +1669,14 @@ static void mtk_hdmi_register_audio_driver(struct device *dev)
 		.max_i2s_channels = 2,
 		.i2s = 1,
 	};
-	struct platform_device *pdev;
+	static struct platform_device *pdev;
 
-	pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
-					     PLATFORM_DEVID_AUTO, &codec_data,
-					     sizeof(codec_data));
-	if (IS_ERR(pdev))
+	if (!pdev) {
+		pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
+						     PLATFORM_DEVID_NONE,
+						     &codec_data,
+						     sizeof(codec_data));
+		DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
+	}
 		return;
-
-	DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
 }
 
 static int mtk_drm_hdmi_probe(struct platform_device *pdev)
@@ -1691,6 +1690,7 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	hdmi->dev = dev;
+	mtk_hdmi_register_audio_driver(dev);
 
 	ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
 	if (ret)
@@ -1704,8 +1704,6 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	mtk_hdmi_register_audio_driver(dev);
-
 	hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
 	hdmi->bridge.of_node = pdev->dev.of_node;
 	drm_bridge_add(&hdmi->bridge);
-- 
2.12.5.2.gbdf23ab

[PATCH v2 09/13] drm/mediatek: add support for SPDIF audio in HDMI

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

add support for SPDIF audio  in HDMI

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_hdmi.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 2cb33098ec1a..cd8aaeebb436 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1594,6 +1594,11 @@ static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
 		hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
 		hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
 		break;
+	case HDMI_SPDIF:
+		hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
+		hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
+		hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
+		break;
 	default:
 		dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
 			daifmt->fmt);
-- 
2.12.5.2.gbdf23ab

[PATCH v2 09/13] drm/mediatek: add support for SPDIF audio in HDMI

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

add support for SPDIF audio  in HDMI

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_hdmi.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 2cb33098ec1a..cd8aaeebb436 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1594,6 +1594,11 @@ static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
 		hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
 		hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
 		break;
+	case HDMI_SPDIF:
+		hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
+		hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
+		hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
+		break;
 	default:
 		dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
 			daifmt->fmt);
-- 
2.12.5.2.gbdf23ab

[PATCH v2 09/13] drm/mediatek: add support for SPDIF audio in HDMI

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

add support for SPDIF audio  in HDMI

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_hdmi.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 2cb33098ec1a..cd8aaeebb436 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1594,6 +1594,11 @@ static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
 		hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
 		hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
 		break;
+	case HDMI_SPDIF:
+		hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
+		hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
+		hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
+		break;
 	default:
 		dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
 			daifmt->fmt);
-- 
2.12.5.2.gbdf23ab

[PATCH v2 10/13] drm/mediatek: add hdmi driver for MT2701 and MT7623

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

This patch adds hdmi dirver suppot for both MT2701 and MT7623.
And also support other (existing or future) chips that use
the same binding and driver.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/Makefile              |   1 +
 drivers/gpu/drm/mediatek/mtk_hdmi.h            |   1 +
 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c        |   3 +
 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 307 +++++++++++++++++++++++++
 4 files changed, 312 insertions(+)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 7f947979d68f..bf0067b5ee6f 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -2,6 +2,7 @@
 mediatek-drm-hdmi-objs := mtk_cec.o \
 			  mtk_hdmi.o \
 			  mtk_hdmi_ddc.o \
+                          mtk_mt2701_hdmi_phy.o \
 			  mtk_mt8173_hdmi_phy.o \
 			  mtk_hdmi_phy.o
 
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.h b/drivers/gpu/drm/mediatek/mtk_hdmi.h
index a350a6c9271f..fa12eb6288f3 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.h
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.h
@@ -45,5 +45,6 @@ extern struct platform_driver mtk_cec_driver;
 extern struct platform_driver mtk_hdmi_ddc_driver;
 extern struct platform_driver mtk_hdmi_phy_driver;
 extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
+extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf;
 
 #endif /* _MTK_HDMI_CTRL_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
index 82ed73575e04..606fc7a0c13b 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
@@ -135,6 +135,9 @@ static int mtk_hdmi_phy_remove(struct platform_device *pdev)
 }
 
 static const struct of_device_id mtk_hdmi_phy_match[] = {
+	{ .compatible = "mediatek,mt2701-hdmi-phy",
+	  .data = &mtk_hdmi_phy_2701_conf,
+	},
 	{ .compatible = "mediatek,mt8173-hdmi-phy",
 	  .data = &mtk_hdmi_phy_8173_conf,
 	},
diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
new file mode 100644
index 000000000000..428ef1557a14
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
@@ -0,0 +1,307 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Chunhui Dai <chunhui.dai@mediatek.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
+#include <linux/slab.h>
+#include "mtk_hdmi.h"
+
+#define HDMI_CON0	0x00
+#define RG_HDMITX_DRV_IBIAS		(0)
+#define RG_HDMITX_DRV_IBIAS_MASK	(0x3F << 0)
+#define RG_HDMITX_EN_SER		(12)
+#define RG_HDMITX_EN_SER_MASK		(0x0F << 12)
+#define RG_HDMITX_EN_SLDO		(16)
+#define RG_HDMITX_EN_SLDO_MASK		(0x0F << 16)
+#define RG_HDMITX_EN_PRED		(20)
+#define RG_HDMITX_EN_PRED_MASK		(0x0F << 20)
+#define RG_HDMITX_EN_IMP		(24)
+#define RG_HDMITX_EN_IMP_MASK		(0x0F << 24)
+#define RG_HDMITX_EN_DRV		(28)
+#define RG_HDMITX_EN_DRV_MASK		(0x0F << 28)
+
+#define HDMI_CON1	0x04
+#define RG_HDMITX_PRED_IBIAS		(18)
+#define RG_HDMITX_PRED_IBIAS_MASK	(0x0F << 18)
+#define RG_HDMITX_PRED_IMP		(0x01 << 22)
+#define RG_HDMITX_DRV_IMP		(26)
+#define RG_HDMITX_DRV_IMP_MASK		(0x3F << 26)
+
+#define HDMI_CON2	0x08
+#define RG_HDMITX_EN_TX_CKLDO		(0x01 << 0)
+#define RG_HDMITX_EN_TX_POSDIV		(0x01 << 1)
+#define RG_HDMITX_TX_POSDIV		(3)
+#define RG_HDMITX_TX_POSDIV_MASK	(0x03 << 3)
+#define RG_HDMITX_EN_MBIAS		(0x01 << 6)
+#define RG_HDMITX_MBIAS_LPF_EN		(0x01 << 7)
+
+#define HDMI_CON4	0x10
+#define RG_HDMITX_RESERVE_MASK		(0xFFFFFFFF << 0)
+
+#define HDMI_CON6	0x18
+#define RG_HTPLL_BR			(0)
+#define RG_HTPLL_BR_MASK		(0x03 << 0)
+#define RG_HTPLL_BC			(2)
+#define RG_HTPLL_BC_MASK		(0x03 << 2)
+#define RG_HTPLL_BP			(4)
+#define RG_HTPLL_BP_MASK		(0x0F << 4)
+#define RG_HTPLL_IR			(8)
+#define RG_HTPLL_IR_MASK		(0x0F << 8)
+#define RG_HTPLL_IC			(12)
+#define RG_HTPLL_IC_MASK		(0x0F << 12)
+#define RG_HTPLL_POSDIV			(16)
+#define RG_HTPLL_POSDIV_MASK		(0x03 << 16)
+#define RG_HTPLL_PREDIV			(18)
+#define RG_HTPLL_PREDIV_MASK		(0x03 << 18)
+#define RG_HTPLL_FBKSEL			(20)
+#define RG_HTPLL_FBKSEL_MASK		(0x03 << 20)
+#define RG_HTPLL_RLH_EN			(0x01 << 22)
+#define RG_HTPLL_FBKDIV			(24)
+#define RG_HTPLL_FBKDIV_MASK		(0x7F << 24)
+#define RG_HTPLL_EN			(0x01 << 31)
+
+#define HDMI_CON7	0x1c
+#define RG_HTPLL_AUTOK_EN		(0x01 << 23)
+#define RG_HTPLL_DIVEN			(28)
+#define RG_HTPLL_DIVEN_MASK		(0x07 << 28)
+
+static inline struct mtk_hdmi_phy *to_mtk_hdmi_pll(struct clk_hw *hw)
+{
+	return container_of(hw, struct mtk_hdmi_phy, pll_hw);
+}
+
+static inline void mtk_hdmi_pll_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
+				     u32 val, u32 mask)
+{
+	u32 tmp = readl(hdmi_phy->regs  + offset) & ~mask;
+
+	tmp |= (val & mask);
+	writel(tmp, hdmi_phy->regs + offset);
+}
+
+static int mtk_hdmi_pll_enable(struct clk_hw *hw)
+{
+	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
+
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN,
+			  RG_HTPLL_AUTOK_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_RLH_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x3 << RG_HTPLL_POSDIV),
+			  RG_HTPLL_POSDIV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS,
+			  RG_HDMITX_EN_MBIAS);
+	usleep_range(80, 100);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, RG_HTPLL_EN, RG_HTPLL_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO,
+			  RG_HDMITX_EN_TX_CKLDO);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_SLDO),
+			  RG_HDMITX_EN_SLDO_MASK);
+	usleep_range(80, 100);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN,
+			  RG_HDMITX_MBIAS_LPF_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV,
+			  RG_HDMITX_EN_TX_POSDIV);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_SER),
+			  RG_HDMITX_EN_SER_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_PRED),
+			  RG_HDMITX_EN_PRED_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_DRV),
+			  RG_HDMITX_EN_DRV_MASK);
+	usleep_range(80, 100);
+	return 0;
+}
+
+static void mtk_hdmi_pll_disable(struct clk_hw *hw)
+{
+	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
+
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_DRV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_PRED_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_SER_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_TX_POSDIV);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_MBIAS_LPF_EN);
+	usleep_range(80, 100);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_SLDO_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_TX_CKLDO);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_EN);
+	usleep_range(80, 100);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_MBIAS);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_POSDIV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_RLH_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, 0, RG_HTPLL_AUTOK_EN);
+	usleep_range(80, 100);
+}
+
+static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+				 unsigned long parent_rate)
+{
+	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
+	u32 pos_div;
+
+	if (rate <= 64000000)
+		pos_div = 3;
+	else if (rate <= 12800000)
+		pos_div = 1;
+	else
+		pos_div = 1;
+
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x3 << RG_HTPLL_PREDIV),
+			  RG_HTPLL_PREDIV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x3 << RG_HTPLL_POSDIV),
+			  RG_HTPLL_POSDIV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IC),
+			  RG_HTPLL_IC_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IR),
+			  RG_HTPLL_IR_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, (pos_div << RG_HDMITX_TX_POSDIV),
+			  RG_HDMITX_TX_POSDIV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (1 << RG_HTPLL_FBKSEL),
+			  RG_HTPLL_FBKSEL_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (19 << RG_HTPLL_FBKDIV),
+			  RG_HTPLL_FBKDIV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, (0x2 << RG_HTPLL_DIVEN),
+			  RG_HTPLL_DIVEN_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0xc << RG_HTPLL_BP),
+			  RG_HTPLL_BP_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x2 << RG_HTPLL_BC),
+			  RG_HTPLL_BC_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_BR),
+			  RG_HTPLL_BR_MASK);
+
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON1, 0, RG_HDMITX_PRED_IMP);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON1, (0x3 << RG_HDMITX_PRED_IBIAS),
+			  RG_HDMITX_PRED_IBIAS_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0x0 << RG_HDMITX_EN_IMP),
+			  RG_HDMITX_EN_IMP_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON1, (0x28 << RG_HDMITX_DRV_IMP),
+			  RG_HDMITX_DRV_IMP_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON4, 0x28, RG_HDMITX_RESERVE_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xa << RG_HDMITX_DRV_IBIAS),
+			  RG_HDMITX_DRV_IBIAS_MASK);
+	return 0;
+}
+
+static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+				    unsigned long *parent_rate)
+{
+	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
+
+	hdmi_phy->pll_rate = rate;
+	return rate;
+}
+
+static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
+					      unsigned long parent_rate)
+{
+	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
+
+	return hdmi_phy->pll_rate;
+}
+
+static const struct clk_ops mtk_hdmi_phy_pll_ops = {
+	.enable = mtk_hdmi_pll_enable,
+	.disable = mtk_hdmi_pll_disable,
+	.set_rate = mtk_hdmi_pll_set_rate,
+	.round_rate = mtk_hdmi_pll_round_rate,
+	.recalc_rate = mtk_hdmi_pll_recalc_rate,
+};
+
+static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
+{
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN,
+			  RG_HTPLL_AUTOK_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_RLH_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x3 << RG_HTPLL_POSDIV),
+			  RG_HTPLL_POSDIV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS,
+			  RG_HDMITX_EN_MBIAS);
+	usleep_range(80, 100);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, RG_HTPLL_EN, RG_HTPLL_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO,
+			  RG_HDMITX_EN_TX_CKLDO);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_SLDO),
+			  RG_HDMITX_EN_SLDO_MASK);
+	usleep_range(80, 100);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN,
+			  RG_HDMITX_MBIAS_LPF_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV,
+			  RG_HDMITX_EN_TX_POSDIV);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_SER),
+			  RG_HDMITX_EN_SER_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_PRED),
+			  RG_HDMITX_EN_PRED_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_DRV),
+			  RG_HDMITX_EN_DRV_MASK);
+	usleep_range(80, 100);
+}
+
+static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
+{
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_DRV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_PRED_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_SER_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_TX_POSDIV);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_MBIAS_LPF_EN);
+	usleep_range(80, 100);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_SLDO_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_TX_CKLDO);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_EN);
+	usleep_range(80, 100);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_MBIAS);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_POSDIV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_RLH_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, 0, RG_HTPLL_AUTOK_EN);
+	usleep_range(80, 100);
+}
+
+static int mtk_hdmi_phy_power_on(struct phy *phy)
+{
+	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
+	int ret;
+
+	ret = clk_prepare_enable(hdmi_phy->pll);
+	if (ret < 0)
+		return ret;
+
+	mtk_hdmi_phy_enable_tmds(hdmi_phy);
+
+	return 0;
+}
+
+static int mtk_hdmi_phy_power_off(struct phy *phy)
+{
+	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
+
+	mtk_hdmi_phy_disable_tmds(hdmi_phy);
+	clk_disable_unprepare(hdmi_phy->pll);
+
+	return 0;
+}
+
+static const struct phy_ops mtk_hdmi_phy_dev_ops = {
+	.power_on = mtk_hdmi_phy_power_on,
+	.power_off = mtk_hdmi_phy_power_off,
+	.owner = THIS_MODULE,
+};
+
+struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf = {
+	.tz_enabled = false,
+	.hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
+	.hdmi_phy_dev_ops = &mtk_hdmi_phy_dev_ops,
+};
+
+MODULE_AUTHOR("Chunhui Dai <chunhui.dai@mediatek.com>");
+MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
+MODULE_LICENSE("GPL v2");
-- 
2.12.5.2.gbdf23ab

[PATCH v2 10/13] drm/mediatek: add hdmi driver for MT2701 and MT7623

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

This patch adds hdmi dirver suppot for both MT2701 and MT7623.
And also support other (existing or future) chips that use
the same binding and driver.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/Makefile              |   1 +
 drivers/gpu/drm/mediatek/mtk_hdmi.h            |   1 +
 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c        |   3 +
 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 307 +++++++++++++++++++++++++
 4 files changed, 312 insertions(+)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 7f947979d68f..bf0067b5ee6f 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -2,6 +2,7 @@
 mediatek-drm-hdmi-objs := mtk_cec.o \
 			  mtk_hdmi.o \
 			  mtk_hdmi_ddc.o \
+                          mtk_mt2701_hdmi_phy.o \
 			  mtk_mt8173_hdmi_phy.o \
 			  mtk_hdmi_phy.o
 
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.h b/drivers/gpu/drm/mediatek/mtk_hdmi.h
index a350a6c9271f..fa12eb6288f3 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.h
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.h
@@ -45,5 +45,6 @@ extern struct platform_driver mtk_cec_driver;
 extern struct platform_driver mtk_hdmi_ddc_driver;
 extern struct platform_driver mtk_hdmi_phy_driver;
 extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
+extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf;
 
 #endif /* _MTK_HDMI_CTRL_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
index 82ed73575e04..606fc7a0c13b 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
@@ -135,6 +135,9 @@ static int mtk_hdmi_phy_remove(struct platform_device *pdev)
 }
 
 static const struct of_device_id mtk_hdmi_phy_match[] = {
+	{ .compatible = "mediatek,mt2701-hdmi-phy",
+	  .data = &mtk_hdmi_phy_2701_conf,
+	},
 	{ .compatible = "mediatek,mt8173-hdmi-phy",
 	  .data = &mtk_hdmi_phy_8173_conf,
 	},
diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
new file mode 100644
index 000000000000..428ef1557a14
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
@@ -0,0 +1,307 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Chunhui Dai <chunhui.dai@mediatek.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
+#include <linux/slab.h>
+#include "mtk_hdmi.h"
+
+#define HDMI_CON0	0x00
+#define RG_HDMITX_DRV_IBIAS		(0)
+#define RG_HDMITX_DRV_IBIAS_MASK	(0x3F << 0)
+#define RG_HDMITX_EN_SER		(12)
+#define RG_HDMITX_EN_SER_MASK		(0x0F << 12)
+#define RG_HDMITX_EN_SLDO		(16)
+#define RG_HDMITX_EN_SLDO_MASK		(0x0F << 16)
+#define RG_HDMITX_EN_PRED		(20)
+#define RG_HDMITX_EN_PRED_MASK		(0x0F << 20)
+#define RG_HDMITX_EN_IMP		(24)
+#define RG_HDMITX_EN_IMP_MASK		(0x0F << 24)
+#define RG_HDMITX_EN_DRV		(28)
+#define RG_HDMITX_EN_DRV_MASK		(0x0F << 28)
+
+#define HDMI_CON1	0x04
+#define RG_HDMITX_PRED_IBIAS		(18)
+#define RG_HDMITX_PRED_IBIAS_MASK	(0x0F << 18)
+#define RG_HDMITX_PRED_IMP		(0x01 << 22)
+#define RG_HDMITX_DRV_IMP		(26)
+#define RG_HDMITX_DRV_IMP_MASK		(0x3F << 26)
+
+#define HDMI_CON2	0x08
+#define RG_HDMITX_EN_TX_CKLDO		(0x01 << 0)
+#define RG_HDMITX_EN_TX_POSDIV		(0x01 << 1)
+#define RG_HDMITX_TX_POSDIV		(3)
+#define RG_HDMITX_TX_POSDIV_MASK	(0x03 << 3)
+#define RG_HDMITX_EN_MBIAS		(0x01 << 6)
+#define RG_HDMITX_MBIAS_LPF_EN		(0x01 << 7)
+
+#define HDMI_CON4	0x10
+#define RG_HDMITX_RESERVE_MASK		(0xFFFFFFFF << 0)
+
+#define HDMI_CON6	0x18
+#define RG_HTPLL_BR			(0)
+#define RG_HTPLL_BR_MASK		(0x03 << 0)
+#define RG_HTPLL_BC			(2)
+#define RG_HTPLL_BC_MASK		(0x03 << 2)
+#define RG_HTPLL_BP			(4)
+#define RG_HTPLL_BP_MASK		(0x0F << 4)
+#define RG_HTPLL_IR			(8)
+#define RG_HTPLL_IR_MASK		(0x0F << 8)
+#define RG_HTPLL_IC			(12)
+#define RG_HTPLL_IC_MASK		(0x0F << 12)
+#define RG_HTPLL_POSDIV			(16)
+#define RG_HTPLL_POSDIV_MASK		(0x03 << 16)
+#define RG_HTPLL_PREDIV			(18)
+#define RG_HTPLL_PREDIV_MASK		(0x03 << 18)
+#define RG_HTPLL_FBKSEL			(20)
+#define RG_HTPLL_FBKSEL_MASK		(0x03 << 20)
+#define RG_HTPLL_RLH_EN			(0x01 << 22)
+#define RG_HTPLL_FBKDIV			(24)
+#define RG_HTPLL_FBKDIV_MASK		(0x7F << 24)
+#define RG_HTPLL_EN			(0x01 << 31)
+
+#define HDMI_CON7	0x1c
+#define RG_HTPLL_AUTOK_EN		(0x01 << 23)
+#define RG_HTPLL_DIVEN			(28)
+#define RG_HTPLL_DIVEN_MASK		(0x07 << 28)
+
+static inline struct mtk_hdmi_phy *to_mtk_hdmi_pll(struct clk_hw *hw)
+{
+	return container_of(hw, struct mtk_hdmi_phy, pll_hw);
+}
+
+static inline void mtk_hdmi_pll_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
+				     u32 val, u32 mask)
+{
+	u32 tmp = readl(hdmi_phy->regs  + offset) & ~mask;
+
+	tmp |= (val & mask);
+	writel(tmp, hdmi_phy->regs + offset);
+}
+
+static int mtk_hdmi_pll_enable(struct clk_hw *hw)
+{
+	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
+
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN,
+			  RG_HTPLL_AUTOK_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_RLH_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x3 << RG_HTPLL_POSDIV),
+			  RG_HTPLL_POSDIV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS,
+			  RG_HDMITX_EN_MBIAS);
+	usleep_range(80, 100);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, RG_HTPLL_EN, RG_HTPLL_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO,
+			  RG_HDMITX_EN_TX_CKLDO);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_SLDO),
+			  RG_HDMITX_EN_SLDO_MASK);
+	usleep_range(80, 100);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN,
+			  RG_HDMITX_MBIAS_LPF_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV,
+			  RG_HDMITX_EN_TX_POSDIV);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_SER),
+			  RG_HDMITX_EN_SER_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_PRED),
+			  RG_HDMITX_EN_PRED_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_DRV),
+			  RG_HDMITX_EN_DRV_MASK);
+	usleep_range(80, 100);
+	return 0;
+}
+
+static void mtk_hdmi_pll_disable(struct clk_hw *hw)
+{
+	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
+
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_DRV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_PRED_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_SER_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_TX_POSDIV);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_MBIAS_LPF_EN);
+	usleep_range(80, 100);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_SLDO_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_TX_CKLDO);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_EN);
+	usleep_range(80, 100);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_MBIAS);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_POSDIV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_RLH_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, 0, RG_HTPLL_AUTOK_EN);
+	usleep_range(80, 100);
+}
+
+static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+				 unsigned long parent_rate)
+{
+	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
+	u32 pos_div;
+
+	if (rate <= 64000000)
+		pos_div = 3;
+	else if (rate <= 12800000)
+		pos_div = 1;
+	else
+		pos_div = 1;
+
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x3 << RG_HTPLL_PREDIV),
+			  RG_HTPLL_PREDIV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x3 << RG_HTPLL_POSDIV),
+			  RG_HTPLL_POSDIV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IC),
+			  RG_HTPLL_IC_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IR),
+			  RG_HTPLL_IR_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, (pos_div << RG_HDMITX_TX_POSDIV),
+			  RG_HDMITX_TX_POSDIV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (1 << RG_HTPLL_FBKSEL),
+			  RG_HTPLL_FBKSEL_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (19 << RG_HTPLL_FBKDIV),
+			  RG_HTPLL_FBKDIV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, (0x2 << RG_HTPLL_DIVEN),
+			  RG_HTPLL_DIVEN_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0xc << RG_HTPLL_BP),
+			  RG_HTPLL_BP_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x2 << RG_HTPLL_BC),
+			  RG_HTPLL_BC_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_BR),
+			  RG_HTPLL_BR_MASK);
+
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON1, 0, RG_HDMITX_PRED_IMP);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON1, (0x3 << RG_HDMITX_PRED_IBIAS),
+			  RG_HDMITX_PRED_IBIAS_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0x0 << RG_HDMITX_EN_IMP),
+			  RG_HDMITX_EN_IMP_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON1, (0x28 << RG_HDMITX_DRV_IMP),
+			  RG_HDMITX_DRV_IMP_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON4, 0x28, RG_HDMITX_RESERVE_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xa << RG_HDMITX_DRV_IBIAS),
+			  RG_HDMITX_DRV_IBIAS_MASK);
+	return 0;
+}
+
+static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+				    unsigned long *parent_rate)
+{
+	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
+
+	hdmi_phy->pll_rate = rate;
+	return rate;
+}
+
+static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
+					      unsigned long parent_rate)
+{
+	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
+
+	return hdmi_phy->pll_rate;
+}
+
+static const struct clk_ops mtk_hdmi_phy_pll_ops = {
+	.enable = mtk_hdmi_pll_enable,
+	.disable = mtk_hdmi_pll_disable,
+	.set_rate = mtk_hdmi_pll_set_rate,
+	.round_rate = mtk_hdmi_pll_round_rate,
+	.recalc_rate = mtk_hdmi_pll_recalc_rate,
+};
+
+static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
+{
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN,
+			  RG_HTPLL_AUTOK_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_RLH_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x3 << RG_HTPLL_POSDIV),
+			  RG_HTPLL_POSDIV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS,
+			  RG_HDMITX_EN_MBIAS);
+	usleep_range(80, 100);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, RG_HTPLL_EN, RG_HTPLL_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO,
+			  RG_HDMITX_EN_TX_CKLDO);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_SLDO),
+			  RG_HDMITX_EN_SLDO_MASK);
+	usleep_range(80, 100);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN,
+			  RG_HDMITX_MBIAS_LPF_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV,
+			  RG_HDMITX_EN_TX_POSDIV);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_SER),
+			  RG_HDMITX_EN_SER_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_PRED),
+			  RG_HDMITX_EN_PRED_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_DRV),
+			  RG_HDMITX_EN_DRV_MASK);
+	usleep_range(80, 100);
+}
+
+static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
+{
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_DRV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_PRED_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_SER_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_TX_POSDIV);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_MBIAS_LPF_EN);
+	usleep_range(80, 100);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_SLDO_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_TX_CKLDO);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_EN);
+	usleep_range(80, 100);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_MBIAS);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_POSDIV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_RLH_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, 0, RG_HTPLL_AUTOK_EN);
+	usleep_range(80, 100);
+}
+
+static int mtk_hdmi_phy_power_on(struct phy *phy)
+{
+	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
+	int ret;
+
+	ret = clk_prepare_enable(hdmi_phy->pll);
+	if (ret < 0)
+		return ret;
+
+	mtk_hdmi_phy_enable_tmds(hdmi_phy);
+
+	return 0;
+}
+
+static int mtk_hdmi_phy_power_off(struct phy *phy)
+{
+	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
+
+	mtk_hdmi_phy_disable_tmds(hdmi_phy);
+	clk_disable_unprepare(hdmi_phy->pll);
+
+	return 0;
+}
+
+static const struct phy_ops mtk_hdmi_phy_dev_ops = {
+	.power_on = mtk_hdmi_phy_power_on,
+	.power_off = mtk_hdmi_phy_power_off,
+	.owner = THIS_MODULE,
+};
+
+struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf = {
+	.tz_enabled = false,
+	.hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
+	.hdmi_phy_dev_ops = &mtk_hdmi_phy_dev_ops,
+};
+
+MODULE_AUTHOR("Chunhui Dai <chunhui.dai@mediatek.com>");
+MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
+MODULE_LICENSE("GPL v2");
-- 
2.12.5.2.gbdf23ab

[PATCH v2 10/13] drm/mediatek: add hdmi driver for MT2701 and MT7623

[Bibby Hsieh]

From: chunhui dai <chunhui.dai@mediatek.com>

This patch adds hdmi dirver suppot for both MT2701 and MT7623.
And also support other (existing or future) chips that use
the same binding and driver.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
---
 drivers/gpu/drm/mediatek/Makefile              |   1 +
 drivers/gpu/drm/mediatek/mtk_hdmi.h            |   1 +
 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c        |   3 +
 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 307 +++++++++++++++++++++++++
 4 files changed, 312 insertions(+)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 7f947979d68f..bf0067b5ee6f 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -2,6 +2,7 @@
 mediatek-drm-hdmi-objs := mtk_cec.o \
 			  mtk_hdmi.o \
 			  mtk_hdmi_ddc.o \
+                          mtk_mt2701_hdmi_phy.o \
 			  mtk_mt8173_hdmi_phy.o \
 			  mtk_hdmi_phy.o
 
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.h b/drivers/gpu/drm/mediatek/mtk_hdmi.h
index a350a6c9271f..fa12eb6288f3 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.h
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.h
@@ -45,5 +45,6 @@ extern struct platform_driver mtk_cec_driver;
 extern struct platform_driver mtk_hdmi_ddc_driver;
 extern struct platform_driver mtk_hdmi_phy_driver;
 extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
+extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf;
 
 #endif /* _MTK_HDMI_CTRL_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
index 82ed73575e04..606fc7a0c13b 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
@@ -135,6 +135,9 @@ static int mtk_hdmi_phy_remove(struct platform_device *pdev)
 }
 
 static const struct of_device_id mtk_hdmi_phy_match[] = {
+	{ .compatible = "mediatek,mt2701-hdmi-phy",
+	  .data = &mtk_hdmi_phy_2701_conf,
+	},
 	{ .compatible = "mediatek,mt8173-hdmi-phy",
 	  .data = &mtk_hdmi_phy_8173_conf,
 	},
diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
new file mode 100644
index 000000000000..428ef1557a14
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
@@ -0,0 +1,307 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Chunhui Dai <chunhui.dai@mediatek.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
+#include <linux/slab.h>
+#include "mtk_hdmi.h"
+
+#define HDMI_CON0	0x00
+#define RG_HDMITX_DRV_IBIAS		(0)
+#define RG_HDMITX_DRV_IBIAS_MASK	(0x3F << 0)
+#define RG_HDMITX_EN_SER		(12)
+#define RG_HDMITX_EN_SER_MASK		(0x0F << 12)
+#define RG_HDMITX_EN_SLDO		(16)
+#define RG_HDMITX_EN_SLDO_MASK		(0x0F << 16)
+#define RG_HDMITX_EN_PRED		(20)
+#define RG_HDMITX_EN_PRED_MASK		(0x0F << 20)
+#define RG_HDMITX_EN_IMP		(24)
+#define RG_HDMITX_EN_IMP_MASK		(0x0F << 24)
+#define RG_HDMITX_EN_DRV		(28)
+#define RG_HDMITX_EN_DRV_MASK		(0x0F << 28)
+
+#define HDMI_CON1	0x04
+#define RG_HDMITX_PRED_IBIAS		(18)
+#define RG_HDMITX_PRED_IBIAS_MASK	(0x0F << 18)
+#define RG_HDMITX_PRED_IMP		(0x01 << 22)
+#define RG_HDMITX_DRV_IMP		(26)
+#define RG_HDMITX_DRV_IMP_MASK		(0x3F << 26)
+
+#define HDMI_CON2	0x08
+#define RG_HDMITX_EN_TX_CKLDO		(0x01 << 0)
+#define RG_HDMITX_EN_TX_POSDIV		(0x01 << 1)
+#define RG_HDMITX_TX_POSDIV		(3)
+#define RG_HDMITX_TX_POSDIV_MASK	(0x03 << 3)
+#define RG_HDMITX_EN_MBIAS		(0x01 << 6)
+#define RG_HDMITX_MBIAS_LPF_EN		(0x01 << 7)
+
+#define HDMI_CON4	0x10
+#define RG_HDMITX_RESERVE_MASK		(0xFFFFFFFF << 0)
+
+#define HDMI_CON6	0x18
+#define RG_HTPLL_BR			(0)
+#define RG_HTPLL_BR_MASK		(0x03 << 0)
+#define RG_HTPLL_BC			(2)
+#define RG_HTPLL_BC_MASK		(0x03 << 2)
+#define RG_HTPLL_BP			(4)
+#define RG_HTPLL_BP_MASK		(0x0F << 4)
+#define RG_HTPLL_IR			(8)
+#define RG_HTPLL_IR_MASK		(0x0F << 8)
+#define RG_HTPLL_IC			(12)
+#define RG_HTPLL_IC_MASK		(0x0F << 12)
+#define RG_HTPLL_POSDIV			(16)
+#define RG_HTPLL_POSDIV_MASK		(0x03 << 16)
+#define RG_HTPLL_PREDIV			(18)
+#define RG_HTPLL_PREDIV_MASK		(0x03 << 18)
+#define RG_HTPLL_FBKSEL			(20)
+#define RG_HTPLL_FBKSEL_MASK		(0x03 << 20)
+#define RG_HTPLL_RLH_EN			(0x01 << 22)
+#define RG_HTPLL_FBKDIV			(24)
+#define RG_HTPLL_FBKDIV_MASK		(0x7F << 24)
+#define RG_HTPLL_EN			(0x01 << 31)
+
+#define HDMI_CON7	0x1c
+#define RG_HTPLL_AUTOK_EN		(0x01 << 23)
+#define RG_HTPLL_DIVEN			(28)
+#define RG_HTPLL_DIVEN_MASK		(0x07 << 28)
+
+static inline struct mtk_hdmi_phy *to_mtk_hdmi_pll(struct clk_hw *hw)
+{
+	return container_of(hw, struct mtk_hdmi_phy, pll_hw);
+}
+
+static inline void mtk_hdmi_pll_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
+				     u32 val, u32 mask)
+{
+	u32 tmp = readl(hdmi_phy->regs  + offset) & ~mask;
+
+	tmp |= (val & mask);
+	writel(tmp, hdmi_phy->regs + offset);
+}
+
+static int mtk_hdmi_pll_enable(struct clk_hw *hw)
+{
+	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
+
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN,
+			  RG_HTPLL_AUTOK_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_RLH_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x3 << RG_HTPLL_POSDIV),
+			  RG_HTPLL_POSDIV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS,
+			  RG_HDMITX_EN_MBIAS);
+	usleep_range(80, 100);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, RG_HTPLL_EN, RG_HTPLL_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO,
+			  RG_HDMITX_EN_TX_CKLDO);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_SLDO),
+			  RG_HDMITX_EN_SLDO_MASK);
+	usleep_range(80, 100);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN,
+			  RG_HDMITX_MBIAS_LPF_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV,
+			  RG_HDMITX_EN_TX_POSDIV);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_SER),
+			  RG_HDMITX_EN_SER_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_PRED),
+			  RG_HDMITX_EN_PRED_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_DRV),
+			  RG_HDMITX_EN_DRV_MASK);
+	usleep_range(80, 100);
+	return 0;
+}
+
+static void mtk_hdmi_pll_disable(struct clk_hw *hw)
+{
+	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
+
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_DRV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_PRED_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_SER_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_TX_POSDIV);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_MBIAS_LPF_EN);
+	usleep_range(80, 100);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_SLDO_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_TX_CKLDO);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_EN);
+	usleep_range(80, 100);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_MBIAS);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_POSDIV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_RLH_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, 0, RG_HTPLL_AUTOK_EN);
+	usleep_range(80, 100);
+}
+
+static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+				 unsigned long parent_rate)
+{
+	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
+	u32 pos_div;
+
+	if (rate <= 64000000)
+		pos_div = 3;
+	else if (rate <= 12800000)
+		pos_div = 1;
+	else
+		pos_div = 1;
+
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x3 << RG_HTPLL_PREDIV),
+			  RG_HTPLL_PREDIV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x3 << RG_HTPLL_POSDIV),
+			  RG_HTPLL_POSDIV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IC),
+			  RG_HTPLL_IC_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IR),
+			  RG_HTPLL_IR_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, (pos_div << RG_HDMITX_TX_POSDIV),
+			  RG_HDMITX_TX_POSDIV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (1 << RG_HTPLL_FBKSEL),
+			  RG_HTPLL_FBKSEL_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (19 << RG_HTPLL_FBKDIV),
+			  RG_HTPLL_FBKDIV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, (0x2 << RG_HTPLL_DIVEN),
+			  RG_HTPLL_DIVEN_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0xc << RG_HTPLL_BP),
+			  RG_HTPLL_BP_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x2 << RG_HTPLL_BC),
+			  RG_HTPLL_BC_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_BR),
+			  RG_HTPLL_BR_MASK);
+
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON1, 0, RG_HDMITX_PRED_IMP);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON1, (0x3 << RG_HDMITX_PRED_IBIAS),
+			  RG_HDMITX_PRED_IBIAS_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0x0 << RG_HDMITX_EN_IMP),
+			  RG_HDMITX_EN_IMP_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON1, (0x28 << RG_HDMITX_DRV_IMP),
+			  RG_HDMITX_DRV_IMP_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON4, 0x28, RG_HDMITX_RESERVE_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xa << RG_HDMITX_DRV_IBIAS),
+			  RG_HDMITX_DRV_IBIAS_MASK);
+	return 0;
+}
+
+static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+				    unsigned long *parent_rate)
+{
+	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
+
+	hdmi_phy->pll_rate = rate;
+	return rate;
+}
+
+static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
+					      unsigned long parent_rate)
+{
+	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
+
+	return hdmi_phy->pll_rate;
+}
+
+static const struct clk_ops mtk_hdmi_phy_pll_ops = {
+	.enable = mtk_hdmi_pll_enable,
+	.disable = mtk_hdmi_pll_disable,
+	.set_rate = mtk_hdmi_pll_set_rate,
+	.round_rate = mtk_hdmi_pll_round_rate,
+	.recalc_rate = mtk_hdmi_pll_recalc_rate,
+};
+
+static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
+{
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN,
+			  RG_HTPLL_AUTOK_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_RLH_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x3 << RG_HTPLL_POSDIV),
+			  RG_HTPLL_POSDIV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS,
+			  RG_HDMITX_EN_MBIAS);
+	usleep_range(80, 100);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, RG_HTPLL_EN, RG_HTPLL_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO,
+			  RG_HDMITX_EN_TX_CKLDO);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_SLDO),
+			  RG_HDMITX_EN_SLDO_MASK);
+	usleep_range(80, 100);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN,
+			  RG_HDMITX_MBIAS_LPF_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV,
+			  RG_HDMITX_EN_TX_POSDIV);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_SER),
+			  RG_HDMITX_EN_SER_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_PRED),
+			  RG_HDMITX_EN_PRED_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_DRV),
+			  RG_HDMITX_EN_DRV_MASK);
+	usleep_range(80, 100);
+}
+
+static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
+{
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_DRV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_PRED_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_SER_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_TX_POSDIV);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_MBIAS_LPF_EN);
+	usleep_range(80, 100);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_SLDO_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_TX_CKLDO);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_EN);
+	usleep_range(80, 100);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_MBIAS);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_POSDIV_MASK);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_RLH_EN);
+	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, 0, RG_HTPLL_AUTOK_EN);
+	usleep_range(80, 100);
+}
+
+static int mtk_hdmi_phy_power_on(struct phy *phy)
+{
+	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
+	int ret;
+
+	ret = clk_prepare_enable(hdmi_phy->pll);
+	if (ret < 0)
+		return ret;
+
+	mtk_hdmi_phy_enable_tmds(hdmi_phy);
+
+	return 0;
+}
+
+static int mtk_hdmi_phy_power_off(struct phy *phy)
+{
+	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
+
+	mtk_hdmi_phy_disable_tmds(hdmi_phy);
+	clk_disable_unprepare(hdmi_phy->pll);
+
+	return 0;
+}
+
+static const struct phy_ops mtk_hdmi_phy_dev_ops = {
+	.power_on = mtk_hdmi_phy_power_on,
+	.power_off = mtk_hdmi_phy_power_off,
+	.owner = THIS_MODULE,
+};
+
+struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf = {
+	.tz_enabled = false,
+	.hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
+	.hdmi_phy_dev_ops = &mtk_hdmi_phy_dev_ops,
+};
+
+MODULE_AUTHOR("Chunhui Dai <chunhui.dai@mediatek.com>");
+MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
+MODULE_LICENSE("GPL v2");
-- 
2.12.5.2.gbdf23ab

[PATCH v2 11/13] drm/mediatek: implement connection from BLS to DPI0

[Bibby Hsieh]

Modify display driver to support connection from BLS to DPI.

Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 87e4191c250e..cc8d49e60c7e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -39,6 +39,7 @@
 #define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
 #define DISP_REG_CONFIG_OUT_SEL			0x04c
 #define DISP_REG_CONFIG_DSI_SEL			0x050
+#define DISP_REG_CONFIG_DPI_SEL			0x064
 
 #define DISP_REG_MUTEX_EN(n)	(0x20 + 0x20 * (n))
 #define DISP_REG_MUTEX(n)	(0x24 + 0x20 * (n))
@@ -132,7 +133,11 @@
 
 #define OVL_MOUT_EN_RDMA		0x1
 #define BLS_TO_DSI_RDMA1_TO_DPI1	0x8
+#define BLS_TO_DPI_RDMA1_TO_DSI		0x2
 #define DSI_SEL_IN_BLS			0x0
+#define DPI_SEL_IN_BLS			0x0
+#define DSI_SEL_IN_RDMA			0x1
+#define DPI_SEL_IN_RDMA			0x1
 
 struct mtk_disp_mutex {
 	int id;
@@ -323,9 +328,21 @@ static void mtk_ddp_sout_sel(void __iomem *config_regs,
 			     enum mtk_ddp_comp_id cur,
 			     enum mtk_ddp_comp_id next)
 {
-	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0)
+	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
 		writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
 			       config_regs + DISP_REG_CONFIG_OUT_SEL);
+		writel_relaxed(DSI_SEL_IN_BLS,
+			       config_regs + DISP_REG_CONFIG_DSI_SEL);
+		writel_relaxed(DPI_SEL_IN_RDMA,
+			       config_regs + DISP_REG_CONFIG_DPI_SEL);
+	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
+		writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
+			       config_regs + DISP_REG_CONFIG_OUT_SEL);
+		writel_relaxed(DSI_SEL_IN_RDMA,
+			       config_regs + DISP_REG_CONFIG_DSI_SEL);
+		writel_relaxed(DPI_SEL_IN_BLS,
+			       config_regs + DISP_REG_CONFIG_DPI_SEL);
+	}
 }
 
 void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
-- 
2.12.5.2.gbdf23ab

[PATCH v2 11/13] drm/mediatek: implement connection from BLS to DPI0

[Bibby Hsieh]

Modify display driver to support connection from BLS to DPI.

Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 87e4191c250e..cc8d49e60c7e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -39,6 +39,7 @@
 #define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
 #define DISP_REG_CONFIG_OUT_SEL			0x04c
 #define DISP_REG_CONFIG_DSI_SEL			0x050
+#define DISP_REG_CONFIG_DPI_SEL			0x064
 
 #define DISP_REG_MUTEX_EN(n)	(0x20 + 0x20 * (n))
 #define DISP_REG_MUTEX(n)	(0x24 + 0x20 * (n))
@@ -132,7 +133,11 @@
 
 #define OVL_MOUT_EN_RDMA		0x1
 #define BLS_TO_DSI_RDMA1_TO_DPI1	0x8
+#define BLS_TO_DPI_RDMA1_TO_DSI		0x2
 #define DSI_SEL_IN_BLS			0x0
+#define DPI_SEL_IN_BLS			0x0
+#define DSI_SEL_IN_RDMA			0x1
+#define DPI_SEL_IN_RDMA			0x1
 
 struct mtk_disp_mutex {
 	int id;
@@ -323,9 +328,21 @@ static void mtk_ddp_sout_sel(void __iomem *config_regs,
 			     enum mtk_ddp_comp_id cur,
 			     enum mtk_ddp_comp_id next)
 {
-	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0)
+	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
 		writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
 			       config_regs + DISP_REG_CONFIG_OUT_SEL);
+		writel_relaxed(DSI_SEL_IN_BLS,
+			       config_regs + DISP_REG_CONFIG_DSI_SEL);
+		writel_relaxed(DPI_SEL_IN_RDMA,
+			       config_regs + DISP_REG_CONFIG_DPI_SEL);
+	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
+		writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
+			       config_regs + DISP_REG_CONFIG_OUT_SEL);
+		writel_relaxed(DSI_SEL_IN_RDMA,
+			       config_regs + DISP_REG_CONFIG_DSI_SEL);
+		writel_relaxed(DPI_SEL_IN_BLS,
+			       config_regs + DISP_REG_CONFIG_DPI_SEL);
+	}
 }
 
 void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
-- 
2.12.5.2.gbdf23ab

[PATCH v2 11/13] drm/mediatek: implement connection from BLS to DPI0

[Bibby Hsieh]

Modify display driver to support connection from BLS to DPI.

Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 87e4191c250e..cc8d49e60c7e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -39,6 +39,7 @@
 #define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
 #define DISP_REG_CONFIG_OUT_SEL			0x04c
 #define DISP_REG_CONFIG_DSI_SEL			0x050
+#define DISP_REG_CONFIG_DPI_SEL			0x064
 
 #define DISP_REG_MUTEX_EN(n)	(0x20 + 0x20 * (n))
 #define DISP_REG_MUTEX(n)	(0x24 + 0x20 * (n))
@@ -132,7 +133,11 @@
 
 #define OVL_MOUT_EN_RDMA		0x1
 #define BLS_TO_DSI_RDMA1_TO_DPI1	0x8
+#define BLS_TO_DPI_RDMA1_TO_DSI		0x2
 #define DSI_SEL_IN_BLS			0x0
+#define DPI_SEL_IN_BLS			0x0
+#define DSI_SEL_IN_RDMA			0x1
+#define DPI_SEL_IN_RDMA			0x1
 
 struct mtk_disp_mutex {
 	int id;
@@ -323,9 +328,21 @@ static void mtk_ddp_sout_sel(void __iomem *config_regs,
 			     enum mtk_ddp_comp_id cur,
 			     enum mtk_ddp_comp_id next)
 {
-	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0)
+	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
 		writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
 			       config_regs + DISP_REG_CONFIG_OUT_SEL);
+		writel_relaxed(DSI_SEL_IN_BLS,
+			       config_regs + DISP_REG_CONFIG_DSI_SEL);
+		writel_relaxed(DPI_SEL_IN_RDMA,
+			       config_regs + DISP_REG_CONFIG_DPI_SEL);
+	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
+		writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
+			       config_regs + DISP_REG_CONFIG_OUT_SEL);
+		writel_relaxed(DSI_SEL_IN_RDMA,
+			       config_regs + DISP_REG_CONFIG_DSI_SEL);
+		writel_relaxed(DPI_SEL_IN_BLS,
+			       config_regs + DISP_REG_CONFIG_DPI_SEL);
+	}
 }
 
 void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
-- 
2.12.5.2.gbdf23ab

[PATCH v2 12/13] drm/mediatek: add a error return value when clock driver has been prepared

[Bibby Hsieh]

DRM driver get the comp->clk by of_clk_get(), we only
assign NULL to comp->clk when error happened, but do
not return the error number.

Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index ff974d82a4a6..54ca794db3e9 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -294,7 +294,7 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
 	comp->irq = of_irq_get(node, 0);
 	comp->clk = of_clk_get(node, 0);
 	if (IS_ERR(comp->clk))
-		comp->clk = NULL;
+		return PTR_ERR(comp->clk);
 
 	/* Only DMA capable components need the LARB property */
 	comp->larb_dev = NULL;
-- 
2.12.5.2.gbdf23ab

[PATCH v2 12/13] drm/mediatek: add a error return value when clock driver has been prepared

[Bibby Hsieh]

DRM driver get the comp->clk by of_clk_get(), we only
assign NULL to comp->clk when error happened, but do
not return the error number.

Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index ff974d82a4a6..54ca794db3e9 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -294,7 +294,7 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
 	comp->irq = of_irq_get(node, 0);
 	comp->clk = of_clk_get(node, 0);
 	if (IS_ERR(comp->clk))
-		comp->clk = NULL;
+		return PTR_ERR(comp->clk);
 
 	/* Only DMA capable components need the LARB property */
 	comp->larb_dev = NULL;
-- 
2.12.5.2.gbdf23ab

[PATCH v2 12/13] drm/mediatek: add a error return value when clock driver has been prepared

[Bibby Hsieh]

DRM driver get the comp->clk by of_clk_get(), we only
assign NULL to comp->clk when error happened, but do
not return the error number.

Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index ff974d82a4a6..54ca794db3e9 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -294,7 +294,7 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
 	comp->irq = of_irq_get(node, 0);
 	comp->clk = of_clk_get(node, 0);
 	if (IS_ERR(comp->clk))
-		comp->clk = NULL;
+		return PTR_ERR(comp->clk);
 
 	/* Only DMA capable components need the LARB property */
 	comp->larb_dev = NULL;
-- 
2.12.5.2.gbdf23ab

[PATCH v2 13/13] drm/mediatek: config component output by device node port

[Bibby Hsieh]

We can select output component by decive node port.
Main path default output component is DSI.
External path default output component is DPI.

Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 37 ++++++++++++++++++++++++++++++----
 drivers/gpu/drm/mediatek/mtk_drm_drv.h |  4 ++--
 2 files changed, 35 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index d961112fa2f5..a477fb878c06 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -21,7 +21,9 @@
 #include <drm/drm_of.h>
 #include <linux/component.h>
 #include <linux/iommu.h>
+#include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/of_graph.h>
 #include <linux/of_platform.h>
 #include <linux/pm_runtime.h>
 
@@ -133,7 +135,7 @@ static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
 	.atomic_commit = mtk_atomic_commit,
 };
 
-static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
+static enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
 	DDP_COMPONENT_OVL0,
 	DDP_COMPONENT_RDMA0,
 	DDP_COMPONENT_COLOR0,
@@ -141,7 +143,7 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
 	DDP_COMPONENT_DSI0,
 };
 
-static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
+static enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
 	DDP_COMPONENT_RDMA1,
 	DDP_COMPONENT_DPI0,
 };
@@ -172,7 +174,7 @@ static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = {
 	DDP_COMPONENT_PWM2,
 };
 
-static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
+static enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
 	DDP_COMPONENT_OVL0,
 	DDP_COMPONENT_COLOR0,
 	DDP_COMPONENT_AAL0,
@@ -183,7 +185,7 @@ static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
 	DDP_COMPONENT_PWM0,
 };
 
-static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
+static enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
 	DDP_COMPONENT_OVL1,
 	DDP_COMPONENT_COLOR1,
 	DDP_COMPONENT_GAMMA,
@@ -472,6 +474,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
 
 	/* Iterate over sibling DISP function blocks */
 	for_each_child_of_node(dev->of_node->parent, node) {
+		struct device_node *port, *ep, *remote;
 		const struct of_device_id *of_id;
 		enum mtk_ddp_comp_type comp_type;
 		int comp_id;
@@ -531,6 +534,32 @@ static int mtk_drm_probe(struct platform_device *pdev)
 
 			private->ddp_comp[comp_id] = comp;
 		}
+
+		if (comp_type != MTK_DSI && comp_type != MTK_DPI) {
+			port = of_graph_get_port_by_id(node, 0);
+			if (!port)
+				continue;
+			ep = of_get_child_by_name(port, "endpoint");
+			of_node_put(port);
+			if (!ep)
+				continue;
+			remote = of_graph_get_remote_port_parent(ep);
+			of_node_put(ep);
+			if (!remote)
+				continue;
+			of_id = of_match_node(mtk_ddp_comp_dt_ids, remote);
+			if (!of_id)
+				continue;
+			comp_type = (enum mtk_ddp_comp_type)of_id->data;
+			for (i = 0; i < private->data->main_len - 1; i++)
+				if (private->data->main_path[i] == comp_id)
+					private->data->main_path[i + 1] =
+					mtk_ddp_comp_get_id(node, comp_type);
+			for (i = 0; i < private->data->ext_len - 1; i++)
+				if (private->data->ext_path[i] == comp_id)
+					private->data->ext_path[i + 1] =
+					mtk_ddp_comp_get_id(node, comp_type);
+		}
 	}
 
 	if (!private->mutex_node) {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index ecc00ca3221d..256a3ff2e66e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -29,9 +29,9 @@ struct drm_property;
 struct regmap;
 
 struct mtk_mmsys_driver_data {
-	const enum mtk_ddp_comp_id *main_path;
+	enum mtk_ddp_comp_id *main_path;
 	unsigned int main_len;
-	const enum mtk_ddp_comp_id *ext_path;
+	enum mtk_ddp_comp_id *ext_path;
 	unsigned int ext_len;
 	const enum mtk_ddp_comp_id *third_path;
 	unsigned int third_len;
-- 
2.12.5.2.gbdf23ab

[PATCH v2 13/13] drm/mediatek: config component output by device node port

[Bibby Hsieh]

We can select output component by decive node port.
Main path default output component is DSI.
External path default output component is DPI.

Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 37 ++++++++++++++++++++++++++++++----
 drivers/gpu/drm/mediatek/mtk_drm_drv.h |  4 ++--
 2 files changed, 35 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index d961112fa2f5..a477fb878c06 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -21,7 +21,9 @@
 #include <drm/drm_of.h>
 #include <linux/component.h>
 #include <linux/iommu.h>
+#include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/of_graph.h>
 #include <linux/of_platform.h>
 #include <linux/pm_runtime.h>
 
@@ -133,7 +135,7 @@ static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
 	.atomic_commit = mtk_atomic_commit,
 };
 
-static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
+static enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
 	DDP_COMPONENT_OVL0,
 	DDP_COMPONENT_RDMA0,
 	DDP_COMPONENT_COLOR0,
@@ -141,7 +143,7 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
 	DDP_COMPONENT_DSI0,
 };
 
-static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
+static enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
 	DDP_COMPONENT_RDMA1,
 	DDP_COMPONENT_DPI0,
 };
@@ -172,7 +174,7 @@ static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = {
 	DDP_COMPONENT_PWM2,
 };
 
-static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
+static enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
 	DDP_COMPONENT_OVL0,
 	DDP_COMPONENT_COLOR0,
 	DDP_COMPONENT_AAL0,
@@ -183,7 +185,7 @@ static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
 	DDP_COMPONENT_PWM0,
 };
 
-static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
+static enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
 	DDP_COMPONENT_OVL1,
 	DDP_COMPONENT_COLOR1,
 	DDP_COMPONENT_GAMMA,
@@ -472,6 +474,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
 
 	/* Iterate over sibling DISP function blocks */
 	for_each_child_of_node(dev->of_node->parent, node) {
+		struct device_node *port, *ep, *remote;
 		const struct of_device_id *of_id;
 		enum mtk_ddp_comp_type comp_type;
 		int comp_id;
@@ -531,6 +534,32 @@ static int mtk_drm_probe(struct platform_device *pdev)
 
 			private->ddp_comp[comp_id] = comp;
 		}
+
+		if (comp_type != MTK_DSI && comp_type != MTK_DPI) {
+			port = of_graph_get_port_by_id(node, 0);
+			if (!port)
+				continue;
+			ep = of_get_child_by_name(port, "endpoint");
+			of_node_put(port);
+			if (!ep)
+				continue;
+			remote = of_graph_get_remote_port_parent(ep);
+			of_node_put(ep);
+			if (!remote)
+				continue;
+			of_id = of_match_node(mtk_ddp_comp_dt_ids, remote);
+			if (!of_id)
+				continue;
+			comp_type = (enum mtk_ddp_comp_type)of_id->data;
+			for (i = 0; i < private->data->main_len - 1; i++)
+				if (private->data->main_path[i] == comp_id)
+					private->data->main_path[i + 1] =
+					mtk_ddp_comp_get_id(node, comp_type);
+			for (i = 0; i < private->data->ext_len - 1; i++)
+				if (private->data->ext_path[i] == comp_id)
+					private->data->ext_path[i + 1] =
+					mtk_ddp_comp_get_id(node, comp_type);
+		}
 	}
 
 	if (!private->mutex_node) {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index ecc00ca3221d..256a3ff2e66e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -29,9 +29,9 @@ struct drm_property;
 struct regmap;
 
 struct mtk_mmsys_driver_data {
-	const enum mtk_ddp_comp_id *main_path;
+	enum mtk_ddp_comp_id *main_path;
 	unsigned int main_len;
-	const enum mtk_ddp_comp_id *ext_path;
+	enum mtk_ddp_comp_id *ext_path;
 	unsigned int ext_len;
 	const enum mtk_ddp_comp_id *third_path;
 	unsigned int third_len;
-- 
2.12.5.2.gbdf23ab

[PATCH v2 13/13] drm/mediatek: config component output by device node port

[Bibby Hsieh]

We can select output component by decive node port.
Main path default output component is DSI.
External path default output component is DPI.

Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 37 ++++++++++++++++++++++++++++++----
 drivers/gpu/drm/mediatek/mtk_drm_drv.h |  4 ++--
 2 files changed, 35 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index d961112fa2f5..a477fb878c06 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -21,7 +21,9 @@
 #include <drm/drm_of.h>
 #include <linux/component.h>
 #include <linux/iommu.h>
+#include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/of_graph.h>
 #include <linux/of_platform.h>
 #include <linux/pm_runtime.h>
 
@@ -133,7 +135,7 @@ static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
 	.atomic_commit = mtk_atomic_commit,
 };
 
-static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
+static enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
 	DDP_COMPONENT_OVL0,
 	DDP_COMPONENT_RDMA0,
 	DDP_COMPONENT_COLOR0,
@@ -141,7 +143,7 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
 	DDP_COMPONENT_DSI0,
 };
 
-static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
+static enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
 	DDP_COMPONENT_RDMA1,
 	DDP_COMPONENT_DPI0,
 };
@@ -172,7 +174,7 @@ static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = {
 	DDP_COMPONENT_PWM2,
 };
 
-static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
+static enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
 	DDP_COMPONENT_OVL0,
 	DDP_COMPONENT_COLOR0,
 	DDP_COMPONENT_AAL0,
@@ -183,7 +185,7 @@ static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
 	DDP_COMPONENT_PWM0,
 };
 
-static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
+static enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
 	DDP_COMPONENT_OVL1,
 	DDP_COMPONENT_COLOR1,
 	DDP_COMPONENT_GAMMA,
@@ -472,6 +474,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
 
 	/* Iterate over sibling DISP function blocks */
 	for_each_child_of_node(dev->of_node->parent, node) {
+		struct device_node *port, *ep, *remote;
 		const struct of_device_id *of_id;
 		enum mtk_ddp_comp_type comp_type;
 		int comp_id;
@@ -531,6 +534,32 @@ static int mtk_drm_probe(struct platform_device *pdev)
 
 			private->ddp_comp[comp_id] = comp;
 		}
+
+		if (comp_type != MTK_DSI && comp_type != MTK_DPI) {
+			port = of_graph_get_port_by_id(node, 0);
+			if (!port)
+				continue;
+			ep = of_get_child_by_name(port, "endpoint");
+			of_node_put(port);
+			if (!ep)
+				continue;
+			remote = of_graph_get_remote_port_parent(ep);
+			of_node_put(ep);
+			if (!remote)
+				continue;
+			of_id = of_match_node(mtk_ddp_comp_dt_ids, remote);
+			if (!of_id)
+				continue;
+			comp_type = (enum mtk_ddp_comp_type)of_id->data;
+			for (i = 0; i < private->data->main_len - 1; i++)
+				if (private->data->main_path[i] == comp_id)
+					private->data->main_path[i + 1] =
+					mtk_ddp_comp_get_id(node, comp_type);
+			for (i = 0; i < private->data->ext_len - 1; i++)
+				if (private->data->ext_path[i] == comp_id)
+					private->data->ext_path[i + 1] =
+					mtk_ddp_comp_get_id(node, comp_type);
+		}
 	}
 
 	if (!private->mutex_node) {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index ecc00ca3221d..256a3ff2e66e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -29,9 +29,9 @@ struct drm_property;
 struct regmap;
 
 struct mtk_mmsys_driver_data {
-	const enum mtk_ddp_comp_id *main_path;
+	enum mtk_ddp_comp_id *main_path;
 	unsigned int main_len;
-	const enum mtk_ddp_comp_id *ext_path;
+	enum mtk_ddp_comp_id *ext_path;
 	unsigned int ext_len;
 	const enum mtk_ddp_comp_id *third_path;
 	unsigned int third_len;
-- 
2.12.5.2.gbdf23ab

Re: [PATCH v2 01/13] drm/mediatek: add refcount for DPI power on/off

[CK Hu]

Hi, Bibby:

This looks reasonable, but why MT8173 doesn't need this patch? So
describe more about why MT7623 need this patch. If this is caused by
latest DRM core flow change, I think we should treat this patch
independent with MT7623.

Regards,
CK

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> add refcount for DPI power on/off to protect the flow
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dpi.c | 16 ++++++++++++++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 6c0ea39d5739..d9373e67d328 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -77,6 +77,7 @@ struct mtk_dpi {
>  	enum mtk_dpi_out_bit_num bit_num;
>  	enum mtk_dpi_out_channel_swap channel_swap;
>  	bool power_sta;
> +	int refcount;
>  	u8 power_ctl;
>  };
>  
> @@ -369,6 +370,12 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
>  
>  static void mtk_dpi_power_off(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl)
>  {
> +	if (WARN_ON(dpi->refcount == 0))
> +		return;
> +
> +	if (--dpi->refcount != 0)
> +		return;
> +
>  	dpi->power_ctl &= ~pctl;
>  
>  	if ((dpi->power_ctl & DPI_POWER_START) ||
> @@ -388,14 +395,17 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl)
>  {
>  	int ret;
>  
> +	if (++dpi->refcount != 1)
> +		return 0;
> +
>  	dpi->power_ctl |= pctl;
>  
>  	if (!(dpi->power_ctl & DPI_POWER_START) &&
>  	    !(dpi->power_ctl & DPI_POWER_ENABLE))
> -		return 0;
> +		goto err_refcount;
>  
>  	if (dpi->power_sta)
> -		return 0;
> +		goto err_refcount;
>  
>  	ret = clk_prepare_enable(dpi->engine_clk);
>  	if (ret) {
> @@ -417,6 +427,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl)
>  	clk_disable_unprepare(dpi->engine_clk);
>  err_eng:
>  	dpi->power_ctl &= ~pctl;
> +err_refcount:
> +	dpi->refcount--;
>  	return ret;
>  }
>  

Re: [PATCH v2 01/13] drm/mediatek: add refcount for DPI power on/off

[CK Hu]

Hi, Bibby:

This looks reasonable, but why MT8173 doesn't need this patch? So
describe more about why MT7623 need this patch. If this is caused by
latest DRM core flow change, I think we should treat this patch
independent with MT7623.

Regards,
CK

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> add refcount for DPI power on/off to protect the flow
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dpi.c | 16 ++++++++++++++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 6c0ea39d5739..d9373e67d328 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -77,6 +77,7 @@ struct mtk_dpi {
>  	enum mtk_dpi_out_bit_num bit_num;
>  	enum mtk_dpi_out_channel_swap channel_swap;
>  	bool power_sta;
> +	int refcount;
>  	u8 power_ctl;
>  };
>  
> @@ -369,6 +370,12 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
>  
>  static void mtk_dpi_power_off(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl)
>  {
> +	if (WARN_ON(dpi->refcount == 0))
> +		return;
> +
> +	if (--dpi->refcount != 0)
> +		return;
> +
>  	dpi->power_ctl &= ~pctl;
>  
>  	if ((dpi->power_ctl & DPI_POWER_START) ||
> @@ -388,14 +395,17 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl)
>  {
>  	int ret;
>  
> +	if (++dpi->refcount != 1)
> +		return 0;
> +
>  	dpi->power_ctl |= pctl;
>  
>  	if (!(dpi->power_ctl & DPI_POWER_START) &&
>  	    !(dpi->power_ctl & DPI_POWER_ENABLE))
> -		return 0;
> +		goto err_refcount;
>  
>  	if (dpi->power_sta)
> -		return 0;
> +		goto err_refcount;
>  
>  	ret = clk_prepare_enable(dpi->engine_clk);
>  	if (ret) {
> @@ -417,6 +427,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl)
>  	clk_disable_unprepare(dpi->engine_clk);
>  err_eng:
>  	dpi->power_ctl &= ~pctl;
> +err_refcount:
> +	dpi->refcount--;
>  	return ret;
>  }
>  


_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v2 01/13] drm/mediatek: add refcount for DPI power on/off

[CK Hu]

Hi, Bibby:

This looks reasonable, but why MT8173 doesn't need this patch? So
describe more about why MT7623 need this patch. If this is caused by
latest DRM core flow change, I think we should treat this patch
independent with MT7623.

Regards,
CK

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> add refcount for DPI power on/off to protect the flow
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dpi.c | 16 ++++++++++++++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 6c0ea39d5739..d9373e67d328 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -77,6 +77,7 @@ struct mtk_dpi {
>  	enum mtk_dpi_out_bit_num bit_num;
>  	enum mtk_dpi_out_channel_swap channel_swap;
>  	bool power_sta;
> +	int refcount;
>  	u8 power_ctl;
>  };
>  
> @@ -369,6 +370,12 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
>  
>  static void mtk_dpi_power_off(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl)
>  {
> +	if (WARN_ON(dpi->refcount == 0))
> +		return;
> +
> +	if (--dpi->refcount != 0)
> +		return;
> +
>  	dpi->power_ctl &= ~pctl;
>  
>  	if ((dpi->power_ctl & DPI_POWER_START) ||
> @@ -388,14 +395,17 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl)
>  {
>  	int ret;
>  
> +	if (++dpi->refcount != 1)
> +		return 0;
> +
>  	dpi->power_ctl |= pctl;
>  
>  	if (!(dpi->power_ctl & DPI_POWER_START) &&
>  	    !(dpi->power_ctl & DPI_POWER_ENABLE))
> -		return 0;
> +		goto err_refcount;
>  
>  	if (dpi->power_sta)
> -		return 0;
> +		goto err_refcount;
>  
>  	ret = clk_prepare_enable(dpi->engine_clk);
>  	if (ret) {
> @@ -417,6 +427,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl)
>  	clk_disable_unprepare(dpi->engine_clk);
>  err_eng:
>  	dpi->power_ctl &= ~pctl;
> +err_refcount:
> +	dpi->refcount--;
>  	return ret;
>  }
>  

Re: [PATCH v2 02/13] drm/mediatek: move hardware register to node data

[CK Hu]

Hi, Bibby:

One inline comment.

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> The address of register DPI_H_FRE_CON is different in different IC.
> Using of_node data to find this address.
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dpi.c      | 29 +++++++++++++++++++++++------
>  drivers/gpu/drm/mediatek/mtk_dpi_regs.h |  1 -
>  2 files changed, 23 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index d9373e67d328..3db959fed493 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -72,6 +72,7 @@ struct mtk_dpi {
>  	struct clk *tvd_clk;
>  	int irq;
>  	struct drm_display_mode mode;
> +	const struct mtk_dpi_conf *conf;
>  	enum mtk_dpi_out_color_format color_format;
>  	enum mtk_dpi_out_yc_map yc_map;
>  	enum mtk_dpi_out_bit_num bit_num;
> @@ -117,6 +118,10 @@ struct mtk_dpi_yc_limit {
>  	u16 c_bottom;
>  };
>  
> +struct mtk_dpi_conf {
> +	const u32 reg_h_fre_con;
> +};
> +
>  static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
>  {
>  	u32 tmp = readl(dpi->regs + offset) & ~mask;
> @@ -342,7 +347,7 @@ static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
>  
>  static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
>  {
> -	mtk_dpi_mask(dpi, DPI_H_FRE_CON, H_FRE_2N, H_FRE_2N);
> +	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
>  }
>  
>  static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
> @@ -668,6 +673,18 @@ static const struct component_ops mtk_dpi_component_ops = {
>  	.unbind = mtk_dpi_unbind,
>  };
>  
> +static const struct mtk_dpi_conf mt8173_conf = {
> +	.reg_h_fre_con = 0xe0,
> +};
> +
> +static const struct of_device_id mtk_dpi_of_ids[] = {
> +	{ .compatible = "mediatek,mt8173-dpi",
> +	  .data = &mt8173_conf,
> +	},
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
> +
>  static int mtk_dpi_probe(struct platform_device *pdev)
>  {
>  	struct device *dev = &pdev->dev;
> @@ -675,13 +692,18 @@ static int mtk_dpi_probe(struct platform_device *pdev)
>  	struct resource *mem;
>  	struct device_node *bridge_node;
>  	int comp_id;
> +	const struct of_device_id *match;
>  	int ret;
>  
> +	match = of_match_node(mtk_dpi_of_ids, dev->of_node);
> +	if (!match)
> +		return -ENODEV;

One more blank line.

Regards,
CK

>  	dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
>  	if (!dpi)
>  		return -ENOMEM;
>  
>  	dpi->dev = dev;
> +	dpi->conf = (struct mtk_dpi_conf *)match->data;
>  
>  	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	dpi->regs = devm_ioremap_resource(dev, mem);
> @@ -760,11 +782,6 @@ static int mtk_dpi_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> -static const struct of_device_id mtk_dpi_of_ids[] = {
> -	{ .compatible = "mediatek,mt8173-dpi", },
> -	{}
> -};
> -
>  struct platform_driver mtk_dpi_driver = {
>  	.probe = mtk_dpi_probe,
>  	.remove = mtk_dpi_remove,
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> index 4b6ad4751a31..040444d7718d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> @@ -223,6 +223,5 @@
>  #define ESAV_CODE2			(0xFFF << 0)
>  #define ESAV_CODE3_MSB			BIT(16)
>  
> -#define DPI_H_FRE_CON		0xE0
>  #define H_FRE_2N			BIT(25)
>  #endif /* __MTK_DPI_REGS_H */

Re: [PATCH v2 02/13] drm/mediatek: move hardware register to node data

[CK Hu]

Hi, Bibby:

One inline comment.

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> The address of register DPI_H_FRE_CON is different in different IC.
> Using of_node data to find this address.
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dpi.c      | 29 +++++++++++++++++++++++------
>  drivers/gpu/drm/mediatek/mtk_dpi_regs.h |  1 -
>  2 files changed, 23 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index d9373e67d328..3db959fed493 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -72,6 +72,7 @@ struct mtk_dpi {
>  	struct clk *tvd_clk;
>  	int irq;
>  	struct drm_display_mode mode;
> +	const struct mtk_dpi_conf *conf;
>  	enum mtk_dpi_out_color_format color_format;
>  	enum mtk_dpi_out_yc_map yc_map;
>  	enum mtk_dpi_out_bit_num bit_num;
> @@ -117,6 +118,10 @@ struct mtk_dpi_yc_limit {
>  	u16 c_bottom;
>  };
>  
> +struct mtk_dpi_conf {
> +	const u32 reg_h_fre_con;
> +};
> +
>  static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
>  {
>  	u32 tmp = readl(dpi->regs + offset) & ~mask;
> @@ -342,7 +347,7 @@ static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
>  
>  static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
>  {
> -	mtk_dpi_mask(dpi, DPI_H_FRE_CON, H_FRE_2N, H_FRE_2N);
> +	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
>  }
>  
>  static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
> @@ -668,6 +673,18 @@ static const struct component_ops mtk_dpi_component_ops = {
>  	.unbind = mtk_dpi_unbind,
>  };
>  
> +static const struct mtk_dpi_conf mt8173_conf = {
> +	.reg_h_fre_con = 0xe0,
> +};
> +
> +static const struct of_device_id mtk_dpi_of_ids[] = {
> +	{ .compatible = "mediatek,mt8173-dpi",
> +	  .data = &mt8173_conf,
> +	},
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
> +
>  static int mtk_dpi_probe(struct platform_device *pdev)
>  {
>  	struct device *dev = &pdev->dev;
> @@ -675,13 +692,18 @@ static int mtk_dpi_probe(struct platform_device *pdev)
>  	struct resource *mem;
>  	struct device_node *bridge_node;
>  	int comp_id;
> +	const struct of_device_id *match;
>  	int ret;
>  
> +	match = of_match_node(mtk_dpi_of_ids, dev->of_node);
> +	if (!match)
> +		return -ENODEV;

One more blank line.

Regards,
CK

>  	dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
>  	if (!dpi)
>  		return -ENOMEM;
>  
>  	dpi->dev = dev;
> +	dpi->conf = (struct mtk_dpi_conf *)match->data;
>  
>  	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	dpi->regs = devm_ioremap_resource(dev, mem);
> @@ -760,11 +782,6 @@ static int mtk_dpi_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> -static const struct of_device_id mtk_dpi_of_ids[] = {
> -	{ .compatible = "mediatek,mt8173-dpi", },
> -	{}
> -};
> -
>  struct platform_driver mtk_dpi_driver = {
>  	.probe = mtk_dpi_probe,
>  	.remove = mtk_dpi_remove,
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> index 4b6ad4751a31..040444d7718d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> @@ -223,6 +223,5 @@
>  #define ESAV_CODE2			(0xFFF << 0)
>  #define ESAV_CODE3_MSB			BIT(16)
>  
> -#define DPI_H_FRE_CON		0xE0
>  #define H_FRE_2N			BIT(25)
>  #endif /* __MTK_DPI_REGS_H */


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[PATCH v2 02/13] drm/mediatek: move hardware register to node data

[CK Hu]

Hi, Bibby:

One inline comment.

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> The address of register DPI_H_FRE_CON is different in different IC.
> Using of_node data to find this address.
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dpi.c      | 29 +++++++++++++++++++++++------
>  drivers/gpu/drm/mediatek/mtk_dpi_regs.h |  1 -
>  2 files changed, 23 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index d9373e67d328..3db959fed493 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -72,6 +72,7 @@ struct mtk_dpi {
>  	struct clk *tvd_clk;
>  	int irq;
>  	struct drm_display_mode mode;
> +	const struct mtk_dpi_conf *conf;
>  	enum mtk_dpi_out_color_format color_format;
>  	enum mtk_dpi_out_yc_map yc_map;
>  	enum mtk_dpi_out_bit_num bit_num;
> @@ -117,6 +118,10 @@ struct mtk_dpi_yc_limit {
>  	u16 c_bottom;
>  };
>  
> +struct mtk_dpi_conf {
> +	const u32 reg_h_fre_con;
> +};
> +
>  static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
>  {
>  	u32 tmp = readl(dpi->regs + offset) & ~mask;
> @@ -342,7 +347,7 @@ static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
>  
>  static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
>  {
> -	mtk_dpi_mask(dpi, DPI_H_FRE_CON, H_FRE_2N, H_FRE_2N);
> +	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
>  }
>  
>  static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
> @@ -668,6 +673,18 @@ static const struct component_ops mtk_dpi_component_ops = {
>  	.unbind = mtk_dpi_unbind,
>  };
>  
> +static const struct mtk_dpi_conf mt8173_conf = {
> +	.reg_h_fre_con = 0xe0,
> +};
> +
> +static const struct of_device_id mtk_dpi_of_ids[] = {
> +	{ .compatible = "mediatek,mt8173-dpi",
> +	  .data = &mt8173_conf,
> +	},
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
> +
>  static int mtk_dpi_probe(struct platform_device *pdev)
>  {
>  	struct device *dev = &pdev->dev;
> @@ -675,13 +692,18 @@ static int mtk_dpi_probe(struct platform_device *pdev)
>  	struct resource *mem;
>  	struct device_node *bridge_node;
>  	int comp_id;
> +	const struct of_device_id *match;
>  	int ret;
>  
> +	match = of_match_node(mtk_dpi_of_ids, dev->of_node);
> +	if (!match)
> +		return -ENODEV;

One more blank line.

Regards,
CK

>  	dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
>  	if (!dpi)
>  		return -ENOMEM;
>  
>  	dpi->dev = dev;
> +	dpi->conf = (struct mtk_dpi_conf *)match->data;
>  
>  	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	dpi->regs = devm_ioremap_resource(dev, mem);
> @@ -760,11 +782,6 @@ static int mtk_dpi_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> -static const struct of_device_id mtk_dpi_of_ids[] = {
> -	{ .compatible = "mediatek,mt8173-dpi", },
> -	{}
> -};
> -
>  struct platform_driver mtk_dpi_driver = {
>  	.probe = mtk_dpi_probe,
>  	.remove = mtk_dpi_remove,
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> index 4b6ad4751a31..040444d7718d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> @@ -223,6 +223,5 @@
>  #define ESAV_CODE2			(0xFFF << 0)
>  #define ESAV_CODE3_MSB			BIT(16)
>  
> -#define DPI_H_FRE_CON		0xE0
>  #define H_FRE_2N			BIT(25)
>  #endif /* __MTK_DPI_REGS_H */

Re: [PATCH v2 02/13] drm/mediatek: move hardware register to node data

[CK Hu]

Hi, Bibby:

One more inline comment.

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> The address of register DPI_H_FRE_CON is different in different IC.
> Using of_node data to find this address.
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dpi.c      | 29 +++++++++++++++++++++++------
>  drivers/gpu/drm/mediatek/mtk_dpi_regs.h |  1 -
>  2 files changed, 23 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index d9373e67d328..3db959fed493 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -72,6 +72,7 @@ struct mtk_dpi {
>  	struct clk *tvd_clk;
>  	int irq;
>  	struct drm_display_mode mode;
> +	const struct mtk_dpi_conf *conf;
>  	enum mtk_dpi_out_color_format color_format;
>  	enum mtk_dpi_out_yc_map yc_map;
>  	enum mtk_dpi_out_bit_num bit_num;
> @@ -117,6 +118,10 @@ struct mtk_dpi_yc_limit {
>  	u16 c_bottom;
>  };
>  
> +struct mtk_dpi_conf {
> +	const u32 reg_h_fre_con;

Remove 'const'.

Regards,
CK

> +};
> +
>  static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
>  {
>  	u32 tmp = readl(dpi->regs + offset) & ~mask;
> @@ -342,7 +347,7 @@ static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
>  
>  static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
>  {
> -	mtk_dpi_mask(dpi, DPI_H_FRE_CON, H_FRE_2N, H_FRE_2N);
> +	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
>  }
>  
>  static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
> @@ -668,6 +673,18 @@ static const struct component_ops mtk_dpi_component_ops = {
>  	.unbind = mtk_dpi_unbind,
>  };
>  
> +static const struct mtk_dpi_conf mt8173_conf = {
> +	.reg_h_fre_con = 0xe0,
> +};
> +
> +static const struct of_device_id mtk_dpi_of_ids[] = {
> +	{ .compatible = "mediatek,mt8173-dpi",
> +	  .data = &mt8173_conf,
> +	},
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
> +
>  static int mtk_dpi_probe(struct platform_device *pdev)
>  {
>  	struct device *dev = &pdev->dev;
> @@ -675,13 +692,18 @@ static int mtk_dpi_probe(struct platform_device *pdev)
>  	struct resource *mem;
>  	struct device_node *bridge_node;
>  	int comp_id;
> +	const struct of_device_id *match;
>  	int ret;
>  
> +	match = of_match_node(mtk_dpi_of_ids, dev->of_node);
> +	if (!match)
> +		return -ENODEV;
>  	dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
>  	if (!dpi)
>  		return -ENOMEM;
>  
>  	dpi->dev = dev;
> +	dpi->conf = (struct mtk_dpi_conf *)match->data;
>  
>  	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	dpi->regs = devm_ioremap_resource(dev, mem);
> @@ -760,11 +782,6 @@ static int mtk_dpi_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> -static const struct of_device_id mtk_dpi_of_ids[] = {
> -	{ .compatible = "mediatek,mt8173-dpi", },
> -	{}
> -};
> -
>  struct platform_driver mtk_dpi_driver = {
>  	.probe = mtk_dpi_probe,
>  	.remove = mtk_dpi_remove,
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> index 4b6ad4751a31..040444d7718d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> @@ -223,6 +223,5 @@
>  #define ESAV_CODE2			(0xFFF << 0)
>  #define ESAV_CODE3_MSB			BIT(16)
>  
> -#define DPI_H_FRE_CON		0xE0
>  #define H_FRE_2N			BIT(25)
>  #endif /* __MTK_DPI_REGS_H */

Re: [PATCH v2 02/13] drm/mediatek: move hardware register to node data

[CK Hu]

Hi, Bibby:

One more inline comment.

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> The address of register DPI_H_FRE_CON is different in different IC.
> Using of_node data to find this address.
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dpi.c      | 29 +++++++++++++++++++++++------
>  drivers/gpu/drm/mediatek/mtk_dpi_regs.h |  1 -
>  2 files changed, 23 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index d9373e67d328..3db959fed493 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -72,6 +72,7 @@ struct mtk_dpi {
>  	struct clk *tvd_clk;
>  	int irq;
>  	struct drm_display_mode mode;
> +	const struct mtk_dpi_conf *conf;
>  	enum mtk_dpi_out_color_format color_format;
>  	enum mtk_dpi_out_yc_map yc_map;
>  	enum mtk_dpi_out_bit_num bit_num;
> @@ -117,6 +118,10 @@ struct mtk_dpi_yc_limit {
>  	u16 c_bottom;
>  };
>  
> +struct mtk_dpi_conf {
> +	const u32 reg_h_fre_con;

Remove 'const'.

Regards,
CK

> +};
> +
>  static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
>  {
>  	u32 tmp = readl(dpi->regs + offset) & ~mask;
> @@ -342,7 +347,7 @@ static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
>  
>  static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
>  {
> -	mtk_dpi_mask(dpi, DPI_H_FRE_CON, H_FRE_2N, H_FRE_2N);
> +	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
>  }
>  
>  static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
> @@ -668,6 +673,18 @@ static const struct component_ops mtk_dpi_component_ops = {
>  	.unbind = mtk_dpi_unbind,
>  };
>  
> +static const struct mtk_dpi_conf mt8173_conf = {
> +	.reg_h_fre_con = 0xe0,
> +};
> +
> +static const struct of_device_id mtk_dpi_of_ids[] = {
> +	{ .compatible = "mediatek,mt8173-dpi",
> +	  .data = &mt8173_conf,
> +	},
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
> +
>  static int mtk_dpi_probe(struct platform_device *pdev)
>  {
>  	struct device *dev = &pdev->dev;
> @@ -675,13 +692,18 @@ static int mtk_dpi_probe(struct platform_device *pdev)
>  	struct resource *mem;
>  	struct device_node *bridge_node;
>  	int comp_id;
> +	const struct of_device_id *match;
>  	int ret;
>  
> +	match = of_match_node(mtk_dpi_of_ids, dev->of_node);
> +	if (!match)
> +		return -ENODEV;
>  	dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
>  	if (!dpi)
>  		return -ENOMEM;
>  
>  	dpi->dev = dev;
> +	dpi->conf = (struct mtk_dpi_conf *)match->data;
>  
>  	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	dpi->regs = devm_ioremap_resource(dev, mem);
> @@ -760,11 +782,6 @@ static int mtk_dpi_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> -static const struct of_device_id mtk_dpi_of_ids[] = {
> -	{ .compatible = "mediatek,mt8173-dpi", },
> -	{}
> -};
> -
>  struct platform_driver mtk_dpi_driver = {
>  	.probe = mtk_dpi_probe,
>  	.remove = mtk_dpi_remove,
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> index 4b6ad4751a31..040444d7718d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> @@ -223,6 +223,5 @@
>  #define ESAV_CODE2			(0xFFF << 0)
>  #define ESAV_CODE3_MSB			BIT(16)
>  
> -#define DPI_H_FRE_CON		0xE0
>  #define H_FRE_2N			BIT(25)
>  #endif /* __MTK_DPI_REGS_H */


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[PATCH v2 02/13] drm/mediatek: move hardware register to node data

[CK Hu]

Hi, Bibby:

One more inline comment.

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> The address of register DPI_H_FRE_CON is different in different IC.
> Using of_node data to find this address.
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dpi.c      | 29 +++++++++++++++++++++++------
>  drivers/gpu/drm/mediatek/mtk_dpi_regs.h |  1 -
>  2 files changed, 23 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index d9373e67d328..3db959fed493 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -72,6 +72,7 @@ struct mtk_dpi {
>  	struct clk *tvd_clk;
>  	int irq;
>  	struct drm_display_mode mode;
> +	const struct mtk_dpi_conf *conf;
>  	enum mtk_dpi_out_color_format color_format;
>  	enum mtk_dpi_out_yc_map yc_map;
>  	enum mtk_dpi_out_bit_num bit_num;
> @@ -117,6 +118,10 @@ struct mtk_dpi_yc_limit {
>  	u16 c_bottom;
>  };
>  
> +struct mtk_dpi_conf {
> +	const u32 reg_h_fre_con;

Remove 'const'.

Regards,
CK

> +};
> +
>  static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
>  {
>  	u32 tmp = readl(dpi->regs + offset) & ~mask;
> @@ -342,7 +347,7 @@ static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
>  
>  static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
>  {
> -	mtk_dpi_mask(dpi, DPI_H_FRE_CON, H_FRE_2N, H_FRE_2N);
> +	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
>  }
>  
>  static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
> @@ -668,6 +673,18 @@ static const struct component_ops mtk_dpi_component_ops = {
>  	.unbind = mtk_dpi_unbind,
>  };
>  
> +static const struct mtk_dpi_conf mt8173_conf = {
> +	.reg_h_fre_con = 0xe0,
> +};
> +
> +static const struct of_device_id mtk_dpi_of_ids[] = {
> +	{ .compatible = "mediatek,mt8173-dpi",
> +	  .data = &mt8173_conf,
> +	},
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
> +
>  static int mtk_dpi_probe(struct platform_device *pdev)
>  {
>  	struct device *dev = &pdev->dev;
> @@ -675,13 +692,18 @@ static int mtk_dpi_probe(struct platform_device *pdev)
>  	struct resource *mem;
>  	struct device_node *bridge_node;
>  	int comp_id;
> +	const struct of_device_id *match;
>  	int ret;
>  
> +	match = of_match_node(mtk_dpi_of_ids, dev->of_node);
> +	if (!match)
> +		return -ENODEV;
>  	dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
>  	if (!dpi)
>  		return -ENOMEM;
>  
>  	dpi->dev = dev;
> +	dpi->conf = (struct mtk_dpi_conf *)match->data;
>  
>  	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	dpi->regs = devm_ioremap_resource(dev, mem);
> @@ -760,11 +782,6 @@ static int mtk_dpi_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> -static const struct of_device_id mtk_dpi_of_ids[] = {
> -	{ .compatible = "mediatek,mt8173-dpi", },
> -	{}
> -};
> -
>  struct platform_driver mtk_dpi_driver = {
>  	.probe = mtk_dpi_probe,
>  	.remove = mtk_dpi_remove,
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> index 4b6ad4751a31..040444d7718d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> @@ -223,6 +223,5 @@
>  #define ESAV_CODE2			(0xFFF << 0)
>  #define ESAV_CODE3_MSB			BIT(16)
>  
> -#define DPI_H_FRE_CON		0xE0
>  #define H_FRE_2N			BIT(25)
>  #endif /* __MTK_DPI_REGS_H */

Re: [PATCH v2 03/13] drm/mediatek: adjust EDGE to match clock and data

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> The default timing of DPI data and clock is not match.
> We could adjust this bit to make them match.
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> ---
>  drivers/gpu/drm/mediatek/mtk_dpi.c      | 8 ++++++++
>  drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 1 +
>  2 files changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 3db959fed493..df27107b1f0b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -120,6 +120,7 @@ struct mtk_dpi_yc_limit {
>  
>  struct mtk_dpi_conf {
>  	const u32 reg_h_fre_con;
> +	bool edge_sel_en;
>  };
>  
>  static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
> @@ -350,6 +351,12 @@ static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
>  	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
>  }
>  
> +static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
> +{
> +	if (dpi->conf->edge_sel_en)
> +		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
> +}
> +
>  static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
>  					enum mtk_dpi_out_color_format format)
>  {
> @@ -535,6 +542,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
>  	mtk_dpi_config_yc_map(dpi, dpi->yc_map);
>  	mtk_dpi_config_color_format(dpi, dpi->color_format);
>  	mtk_dpi_config_2n_h_fre(dpi);
> +	mtk_dpi_config_disable_edge(dpi);
>  	mtk_dpi_sw_reset(dpi, false);
>  
>  	return 0;
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> index 040444d7718d..d9db8c4cacd7 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> @@ -223,5 +223,6 @@
>  #define ESAV_CODE2			(0xFFF << 0)
>  #define ESAV_CODE3_MSB			BIT(16)
>  
> +#define EDGE_SEL_EN			BIT(5)
>  #define H_FRE_2N			BIT(25)
>  #endif /* __MTK_DPI_REGS_H */

Re: [PATCH v2 03/13] drm/mediatek: adjust EDGE to match clock and data

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> The default timing of DPI data and clock is not match.
> We could adjust this bit to make them match.
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> ---
>  drivers/gpu/drm/mediatek/mtk_dpi.c      | 8 ++++++++
>  drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 1 +
>  2 files changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 3db959fed493..df27107b1f0b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -120,6 +120,7 @@ struct mtk_dpi_yc_limit {
>  
>  struct mtk_dpi_conf {
>  	const u32 reg_h_fre_con;
> +	bool edge_sel_en;
>  };
>  
>  static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
> @@ -350,6 +351,12 @@ static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
>  	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
>  }
>  
> +static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
> +{
> +	if (dpi->conf->edge_sel_en)
> +		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
> +}
> +
>  static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
>  					enum mtk_dpi_out_color_format format)
>  {
> @@ -535,6 +542,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
>  	mtk_dpi_config_yc_map(dpi, dpi->yc_map);
>  	mtk_dpi_config_color_format(dpi, dpi->color_format);
>  	mtk_dpi_config_2n_h_fre(dpi);
> +	mtk_dpi_config_disable_edge(dpi);
>  	mtk_dpi_sw_reset(dpi, false);
>  
>  	return 0;
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> index 040444d7718d..d9db8c4cacd7 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> @@ -223,5 +223,6 @@
>  #define ESAV_CODE2			(0xFFF << 0)
>  #define ESAV_CODE3_MSB			BIT(16)
>  
> +#define EDGE_SEL_EN			BIT(5)
>  #define H_FRE_2N			BIT(25)
>  #endif /* __MTK_DPI_REGS_H */

[PATCH v2 03/13] drm/mediatek: adjust EDGE to match clock and data

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> The default timing of DPI data and clock is not match.
> We could adjust this bit to make them match.
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> ---
>  drivers/gpu/drm/mediatek/mtk_dpi.c      | 8 ++++++++
>  drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 1 +
>  2 files changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 3db959fed493..df27107b1f0b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -120,6 +120,7 @@ struct mtk_dpi_yc_limit {
>  
>  struct mtk_dpi_conf {
>  	const u32 reg_h_fre_con;
> +	bool edge_sel_en;
>  };
>  
>  static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
> @@ -350,6 +351,12 @@ static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
>  	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
>  }
>  
> +static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
> +{
> +	if (dpi->conf->edge_sel_en)
> +		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
> +}
> +
>  static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
>  					enum mtk_dpi_out_color_format format)
>  {
> @@ -535,6 +542,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
>  	mtk_dpi_config_yc_map(dpi, dpi->yc_map);
>  	mtk_dpi_config_color_format(dpi, dpi->color_format);
>  	mtk_dpi_config_2n_h_fre(dpi);
> +	mtk_dpi_config_disable_edge(dpi);
>  	mtk_dpi_sw_reset(dpi, false);
>  
>  	return 0;
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> index 040444d7718d..d9db8c4cacd7 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> @@ -223,5 +223,6 @@
>  #define ESAV_CODE2			(0xFFF << 0)
>  #define ESAV_CODE3_MSB			BIT(16)
>  
> +#define EDGE_SEL_EN			BIT(5)
>  #define H_FRE_2N			BIT(25)
>  #endif /* __MTK_DPI_REGS_H */

Re: [PATCH v2 05/13] drm/mediatek: dpi use new API for finding bridge

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> Using new API for finding bridge.
> 

This patch looks good, but your description is so simple that we don't
know why you want to do this. In [1], Rob wants to clean up OF graph
API, so in [2], mtk_dsi.c use drm_of_find_panel_or_bridge() to do this
clean-up. If your reason is clean-up, describe it in commit message.

[1] https://lkml.org/lkml/2017/2/3/716
[2] https://lkml.org/lkml/2017/2/3/719

Regards,
CK

> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dpi.c | 17 +++++++----------
>  1 file changed, 7 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 3758cfeb586b..ed2c153c70a2 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -14,6 +14,7 @@
>  #include <drm/drmP.h>
>  #include <drm/drm_crtc.h>
>  #include <drm/drm_crtc_helper.h>
> +#include <drm/drm_of.h>
>  #include <linux/kernel.h>
>  #include <linux/component.h>
>  #include <linux/platform_device.h>
> @@ -708,7 +709,6 @@ static int mtk_dpi_probe(struct platform_device *pdev)
>  	struct device *dev = &pdev->dev;
>  	struct mtk_dpi *dpi;
>  	struct resource *mem;
> -	struct device_node *bridge_node;
>  	int comp_id;
>  	const struct of_device_id *match;
>  	int ret;
> @@ -758,16 +758,13 @@ static int mtk_dpi_probe(struct platform_device *pdev)
>  		return -EINVAL;
>  	}
>  
> -	bridge_node = of_graph_get_remote_node(dev->of_node, 0, 0);
> -	if (!bridge_node)
> -		return -ENODEV;
> -
> -	dev_info(dev, "Found bridge node: %pOF\n", bridge_node);
> -
> -	dpi->bridge = of_drm_find_bridge(bridge_node);
> -	of_node_put(bridge_node);
> -	if (!dpi->bridge)
> +	ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
> +					  NULL, &dpi->bridge);
> +	if (ret) {
> +		dev_err(dev, "Failed to find panel or bridge: %d\n", ret);
>  		return -EPROBE_DEFER;
> +	}
> +	dev_info(dev, "Found bridge node: %pOF\n", dpi->bridge);
>  
>  	comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DPI);
>  	if (comp_id < 0) {

Re: [PATCH v2 05/13] drm/mediatek: dpi use new API for finding bridge

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> Using new API for finding bridge.
> 

This patch looks good, but your description is so simple that we don't
know why you want to do this. In [1], Rob wants to clean up OF graph
API, so in [2], mtk_dsi.c use drm_of_find_panel_or_bridge() to do this
clean-up. If your reason is clean-up, describe it in commit message.

[1] https://lkml.org/lkml/2017/2/3/716
[2] https://lkml.org/lkml/2017/2/3/719

Regards,
CK

> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dpi.c | 17 +++++++----------
>  1 file changed, 7 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 3758cfeb586b..ed2c153c70a2 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -14,6 +14,7 @@
>  #include <drm/drmP.h>
>  #include <drm/drm_crtc.h>
>  #include <drm/drm_crtc_helper.h>
> +#include <drm/drm_of.h>
>  #include <linux/kernel.h>
>  #include <linux/component.h>
>  #include <linux/platform_device.h>
> @@ -708,7 +709,6 @@ static int mtk_dpi_probe(struct platform_device *pdev)
>  	struct device *dev = &pdev->dev;
>  	struct mtk_dpi *dpi;
>  	struct resource *mem;
> -	struct device_node *bridge_node;
>  	int comp_id;
>  	const struct of_device_id *match;
>  	int ret;
> @@ -758,16 +758,13 @@ static int mtk_dpi_probe(struct platform_device *pdev)
>  		return -EINVAL;
>  	}
>  
> -	bridge_node = of_graph_get_remote_node(dev->of_node, 0, 0);
> -	if (!bridge_node)
> -		return -ENODEV;
> -
> -	dev_info(dev, "Found bridge node: %pOF\n", bridge_node);
> -
> -	dpi->bridge = of_drm_find_bridge(bridge_node);
> -	of_node_put(bridge_node);
> -	if (!dpi->bridge)
> +	ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
> +					  NULL, &dpi->bridge);
> +	if (ret) {
> +		dev_err(dev, "Failed to find panel or bridge: %d\n", ret);
>  		return -EPROBE_DEFER;
> +	}
> +	dev_info(dev, "Found bridge node: %pOF\n", dpi->bridge);
>  
>  	comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DPI);
>  	if (comp_id < 0) {


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[PATCH v2 05/13] drm/mediatek: dpi use new API for finding bridge

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> Using new API for finding bridge.
> 

This patch looks good, but your description is so simple that we don't
know why you want to do this. In [1], Rob wants to clean up OF graph
API, so in [2], mtk_dsi.c use drm_of_find_panel_or_bridge() to do this
clean-up. If your reason is clean-up, describe it in commit message.

[1] https://lkml.org/lkml/2017/2/3/716
[2] https://lkml.org/lkml/2017/2/3/719

Regards,
CK

> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dpi.c | 17 +++++++----------
>  1 file changed, 7 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 3758cfeb586b..ed2c153c70a2 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -14,6 +14,7 @@
>  #include <drm/drmP.h>
>  #include <drm/drm_crtc.h>
>  #include <drm/drm_crtc_helper.h>
> +#include <drm/drm_of.h>
>  #include <linux/kernel.h>
>  #include <linux/component.h>
>  #include <linux/platform_device.h>
> @@ -708,7 +709,6 @@ static int mtk_dpi_probe(struct platform_device *pdev)
>  	struct device *dev = &pdev->dev;
>  	struct mtk_dpi *dpi;
>  	struct resource *mem;
> -	struct device_node *bridge_node;
>  	int comp_id;
>  	const struct of_device_id *match;
>  	int ret;
> @@ -758,16 +758,13 @@ static int mtk_dpi_probe(struct platform_device *pdev)
>  		return -EINVAL;
>  	}
>  
> -	bridge_node = of_graph_get_remote_node(dev->of_node, 0, 0);
> -	if (!bridge_node)
> -		return -ENODEV;
> -
> -	dev_info(dev, "Found bridge node: %pOF\n", bridge_node);
> -
> -	dpi->bridge = of_drm_find_bridge(bridge_node);
> -	of_node_put(bridge_node);
> -	if (!dpi->bridge)
> +	ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
> +					  NULL, &dpi->bridge);
> +	if (ret) {
> +		dev_err(dev, "Failed to find panel or bridge: %d\n", ret);
>  		return -EPROBE_DEFER;
> +	}
> +	dev_info(dev, "Found bridge node: %pOF\n", dpi->bridge);
>  
>  	comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DPI);
>  	if (comp_id < 0) {

Re: [PATCH v2 04/13] drm/mediatek: add clock factor for different IC

[CK Hu]

Hi, Bibby:

One inline comment.

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> different IC has different clock designed in HDMI, the factor for
> calculate clock should be different. Usinng the data in of_node
> to find this factor.
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dpi.c | 28 +++++++++++++++++++---------
>  1 file changed, 19 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index df27107b1f0b..3758cfeb586b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -119,6 +119,7 @@ struct mtk_dpi_yc_limit {
>  };
>  
>  struct mtk_dpi_conf {
> +	unsigned int (*cal_factor)(int clock);
>  	const u32 reg_h_fre_con;
>  	bool edge_sel_en;
>  };
> @@ -458,16 +459,12 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
>  	unsigned long pll_rate;
>  	unsigned int factor;
>  
> +	if (!dpi) {
> +		dev_err(dpi->dev, "invalid argument\n");
> +		return -EINVAL;
> +	}

I think this should not be in this patch, move to an independent patch.

Regards,
CK

>  	/* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
> -
> -	if (mode->clock <= 27000)
> -		factor = 3 << 4;
> -	else if (mode->clock <= 84000)
> -		factor = 3 << 3;
> -	else if (mode->clock <= 167000)
> -		factor = 3 << 2;
> -	else
> -		factor = 3 << 1;
> +	factor = dpi->conf->cal_factor(mode->clock);
>  	drm_display_mode_to_videomode(mode, &vm);
>  	pll_rate = vm.pixelclock * factor;
>  
> @@ -681,7 +678,20 @@ static const struct component_ops mtk_dpi_component_ops = {
>  	.unbind = mtk_dpi_unbind,
>  };
>  
> +static unsigned int mt8173_calculate_factor(int clock)
> +{
> +	if (clock <= 27000)
> +		return 3 << 4;
> +	else if (clock <= 84000)
> +		return 3 << 3;
> +	else if (clock <= 167000)
> +		return 3 << 2;
> +	else
> +		return 3 << 1;
> +}
> +
>  static const struct mtk_dpi_conf mt8173_conf = {
> +	.cal_factor = mt8173_calculate_factor,
>  	.reg_h_fre_con = 0xe0,
>  };
>  

Re: [PATCH v2 04/13] drm/mediatek: add clock factor for different IC

[CK Hu]

Hi, Bibby:

One inline comment.

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> different IC has different clock designed in HDMI, the factor for
> calculate clock should be different. Usinng the data in of_node
> to find this factor.
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dpi.c | 28 +++++++++++++++++++---------
>  1 file changed, 19 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index df27107b1f0b..3758cfeb586b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -119,6 +119,7 @@ struct mtk_dpi_yc_limit {
>  };
>  
>  struct mtk_dpi_conf {
> +	unsigned int (*cal_factor)(int clock);
>  	const u32 reg_h_fre_con;
>  	bool edge_sel_en;
>  };
> @@ -458,16 +459,12 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
>  	unsigned long pll_rate;
>  	unsigned int factor;
>  
> +	if (!dpi) {
> +		dev_err(dpi->dev, "invalid argument\n");
> +		return -EINVAL;
> +	}

I think this should not be in this patch, move to an independent patch.

Regards,
CK

>  	/* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
> -
> -	if (mode->clock <= 27000)
> -		factor = 3 << 4;
> -	else if (mode->clock <= 84000)
> -		factor = 3 << 3;
> -	else if (mode->clock <= 167000)
> -		factor = 3 << 2;
> -	else
> -		factor = 3 << 1;
> +	factor = dpi->conf->cal_factor(mode->clock);
>  	drm_display_mode_to_videomode(mode, &vm);
>  	pll_rate = vm.pixelclock * factor;
>  
> @@ -681,7 +678,20 @@ static const struct component_ops mtk_dpi_component_ops = {
>  	.unbind = mtk_dpi_unbind,
>  };
>  
> +static unsigned int mt8173_calculate_factor(int clock)
> +{
> +	if (clock <= 27000)
> +		return 3 << 4;
> +	else if (clock <= 84000)
> +		return 3 << 3;
> +	else if (clock <= 167000)
> +		return 3 << 2;
> +	else
> +		return 3 << 1;
> +}
> +
>  static const struct mtk_dpi_conf mt8173_conf = {
> +	.cal_factor = mt8173_calculate_factor,
>  	.reg_h_fre_con = 0xe0,
>  };
>  

[PATCH v2 04/13] drm/mediatek: add clock factor for different IC

[CK Hu]

Hi, Bibby:

One inline comment.

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> different IC has different clock designed in HDMI, the factor for
> calculate clock should be different. Usinng the data in of_node
> to find this factor.
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dpi.c | 28 +++++++++++++++++++---------
>  1 file changed, 19 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index df27107b1f0b..3758cfeb586b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -119,6 +119,7 @@ struct mtk_dpi_yc_limit {
>  };
>  
>  struct mtk_dpi_conf {
> +	unsigned int (*cal_factor)(int clock);
>  	const u32 reg_h_fre_con;
>  	bool edge_sel_en;
>  };
> @@ -458,16 +459,12 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
>  	unsigned long pll_rate;
>  	unsigned int factor;
>  
> +	if (!dpi) {
> +		dev_err(dpi->dev, "invalid argument\n");
> +		return -EINVAL;
> +	}

I think this should not be in this patch, move to an independent patch.

Regards,
CK

>  	/* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
> -
> -	if (mode->clock <= 27000)
> -		factor = 3 << 4;
> -	else if (mode->clock <= 84000)
> -		factor = 3 << 3;
> -	else if (mode->clock <= 167000)
> -		factor = 3 << 2;
> -	else
> -		factor = 3 << 1;
> +	factor = dpi->conf->cal_factor(mode->clock);
>  	drm_display_mode_to_videomode(mode, &vm);
>  	pll_rate = vm.pixelclock * factor;
>  
> @@ -681,7 +678,20 @@ static const struct component_ops mtk_dpi_component_ops = {
>  	.unbind = mtk_dpi_unbind,
>  };
>  
> +static unsigned int mt8173_calculate_factor(int clock)
> +{
> +	if (clock <= 27000)
> +		return 3 << 4;
> +	else if (clock <= 84000)
> +		return 3 << 3;
> +	else if (clock <= 167000)
> +		return 3 << 2;
> +	else
> +		return 3 << 1;
> +}
> +
>  static const struct mtk_dpi_conf mt8173_conf = {
> +	.cal_factor = mt8173_calculate_factor,
>  	.reg_h_fre_con = 0xe0,
>  };
>  

Re: [PATCH v2 06/13] drm/mediatek: add dpi driver for mt2701 and mt7623

[CK Hu]

Hi, Bibby:

One inline comment.

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> This patch adds dpi dirver suppot for both mt2701 and mt7623.
> And also support other (existing or future) chips that use
> the same binding and driver.
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dpi.c     | 25 ++++++++++++++++++++++---
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c |  2 ++
>  2 files changed, 24 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index ed2c153c70a2..1af25765ab5f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -641,9 +641,7 @@ static int mtk_dpi_bind(struct device *dev, struct device *master, void *data)
>  	}
>  	drm_encoder_helper_add(&dpi->encoder, &mtk_dpi_encoder_helper_funcs);
>  
> -	/* Currently DPI0 is fixed to be driven by OVL1 */
> -	dpi->encoder.possible_crtcs = BIT(1);
> -
> +	dpi->encoder.possible_crtcs = BIT(0) | BIT(1);

This patch is for MT2701 and MT7623, but this modification would apply
to MT8173 and MT2712. Does MT8173 and MT2712 support this modification?
If the answer is no, apply this modification only for MT2701 and MT7623.
If the answer is yes, move this modification to an independent patch.

Regards,
CK

>  	ret = drm_bridge_attach(&dpi->encoder, dpi->bridge, NULL);
>  	if (ret) {
>  		dev_err(dev, "Failed to attach bridge: %d\n", ret);
> @@ -691,12 +689,33 @@ static unsigned int mt8173_calculate_factor(int clock)
>  		return 3 << 1;
>  }
>  
> +static unsigned int mt2701_calculate_factor(int clock)
> +{
> +	if (clock <= 64000)
> +		return 16;
> +	else if (clock <= 128000)
> +		return 8;
> +	else if (clock <= 256000)
> +		return 4;
> +	else
> +		return 2;
> +}
> +
>  static const struct mtk_dpi_conf mt8173_conf = {
>  	.cal_factor = mt8173_calculate_factor,
>  	.reg_h_fre_con = 0xe0,
>  };
>  
> +static const struct mtk_dpi_conf mt2701_conf = {
> +	.cal_factor = mt2701_calculate_factor,
> +	.reg_h_fre_con = 0xb0,
> +	.edge_sel_en = true,
> +};
> +
>  static const struct of_device_id mtk_dpi_of_ids[] = {
> +	{ .compatible = "mediatek,mt2701-dpi",
> +	  .data = &mt2701_conf,
> +	},
>  	{ .compatible = "mediatek,mt8173-dpi",
>  	  .data = &mt8173_conf,
>  	},
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 39721119713b..d961112fa2f5 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -424,6 +424,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>  	  .data = (void *)MTK_DSI },
>  	{ .compatible = "mediatek,mt8173-dsi",
>  	  .data = (void *)MTK_DSI },
> +	{ .compatible = "mediatek,mt2701-dpi",
> +	  .data = (void *)MTK_DPI },
>  	{ .compatible = "mediatek,mt8173-dpi",
>  	  .data = (void *)MTK_DPI },
>  	{ .compatible = "mediatek,mt2701-disp-mutex",

Re: [PATCH v2 06/13] drm/mediatek: add dpi driver for mt2701 and mt7623

[CK Hu]

Hi, Bibby:

One inline comment.

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> This patch adds dpi dirver suppot for both mt2701 and mt7623.
> And also support other (existing or future) chips that use
> the same binding and driver.
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dpi.c     | 25 ++++++++++++++++++++++---
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c |  2 ++
>  2 files changed, 24 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index ed2c153c70a2..1af25765ab5f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -641,9 +641,7 @@ static int mtk_dpi_bind(struct device *dev, struct device *master, void *data)
>  	}
>  	drm_encoder_helper_add(&dpi->encoder, &mtk_dpi_encoder_helper_funcs);
>  
> -	/* Currently DPI0 is fixed to be driven by OVL1 */
> -	dpi->encoder.possible_crtcs = BIT(1);
> -
> +	dpi->encoder.possible_crtcs = BIT(0) | BIT(1);

This patch is for MT2701 and MT7623, but this modification would apply
to MT8173 and MT2712. Does MT8173 and MT2712 support this modification?
If the answer is no, apply this modification only for MT2701 and MT7623.
If the answer is yes, move this modification to an independent patch.

Regards,
CK

>  	ret = drm_bridge_attach(&dpi->encoder, dpi->bridge, NULL);
>  	if (ret) {
>  		dev_err(dev, "Failed to attach bridge: %d\n", ret);
> @@ -691,12 +689,33 @@ static unsigned int mt8173_calculate_factor(int clock)
>  		return 3 << 1;
>  }
>  
> +static unsigned int mt2701_calculate_factor(int clock)
> +{
> +	if (clock <= 64000)
> +		return 16;
> +	else if (clock <= 128000)
> +		return 8;
> +	else if (clock <= 256000)
> +		return 4;
> +	else
> +		return 2;
> +}
> +
>  static const struct mtk_dpi_conf mt8173_conf = {
>  	.cal_factor = mt8173_calculate_factor,
>  	.reg_h_fre_con = 0xe0,
>  };
>  
> +static const struct mtk_dpi_conf mt2701_conf = {
> +	.cal_factor = mt2701_calculate_factor,
> +	.reg_h_fre_con = 0xb0,
> +	.edge_sel_en = true,
> +};
> +
>  static const struct of_device_id mtk_dpi_of_ids[] = {
> +	{ .compatible = "mediatek,mt2701-dpi",
> +	  .data = &mt2701_conf,
> +	},
>  	{ .compatible = "mediatek,mt8173-dpi",
>  	  .data = &mt8173_conf,
>  	},
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 39721119713b..d961112fa2f5 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -424,6 +424,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>  	  .data = (void *)MTK_DSI },
>  	{ .compatible = "mediatek,mt8173-dsi",
>  	  .data = (void *)MTK_DSI },
> +	{ .compatible = "mediatek,mt2701-dpi",
> +	  .data = (void *)MTK_DPI },
>  	{ .compatible = "mediatek,mt8173-dpi",
>  	  .data = (void *)MTK_DPI },
>  	{ .compatible = "mediatek,mt2701-disp-mutex",

[PATCH v2 06/13] drm/mediatek: add dpi driver for mt2701 and mt7623

[CK Hu]

Hi, Bibby:

One inline comment.

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> This patch adds dpi dirver suppot for both mt2701 and mt7623.
> And also support other (existing or future) chips that use
> the same binding and driver.
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dpi.c     | 25 ++++++++++++++++++++++---
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c |  2 ++
>  2 files changed, 24 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index ed2c153c70a2..1af25765ab5f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -641,9 +641,7 @@ static int mtk_dpi_bind(struct device *dev, struct device *master, void *data)
>  	}
>  	drm_encoder_helper_add(&dpi->encoder, &mtk_dpi_encoder_helper_funcs);
>  
> -	/* Currently DPI0 is fixed to be driven by OVL1 */
> -	dpi->encoder.possible_crtcs = BIT(1);
> -
> +	dpi->encoder.possible_crtcs = BIT(0) | BIT(1);

This patch is for MT2701 and MT7623, but this modification would apply
to MT8173 and MT2712. Does MT8173 and MT2712 support this modification?
If the answer is no, apply this modification only for MT2701 and MT7623.
If the answer is yes, move this modification to an independent patch.

Regards,
CK

>  	ret = drm_bridge_attach(&dpi->encoder, dpi->bridge, NULL);
>  	if (ret) {
>  		dev_err(dev, "Failed to attach bridge: %d\n", ret);
> @@ -691,12 +689,33 @@ static unsigned int mt8173_calculate_factor(int clock)
>  		return 3 << 1;
>  }
>  
> +static unsigned int mt2701_calculate_factor(int clock)
> +{
> +	if (clock <= 64000)
> +		return 16;
> +	else if (clock <= 128000)
> +		return 8;
> +	else if (clock <= 256000)
> +		return 4;
> +	else
> +		return 2;
> +}
> +
>  static const struct mtk_dpi_conf mt8173_conf = {
>  	.cal_factor = mt8173_calculate_factor,
>  	.reg_h_fre_con = 0xe0,
>  };
>  
> +static const struct mtk_dpi_conf mt2701_conf = {
> +	.cal_factor = mt2701_calculate_factor,
> +	.reg_h_fre_con = 0xb0,
> +	.edge_sel_en = true,
> +};
> +
>  static const struct of_device_id mtk_dpi_of_ids[] = {
> +	{ .compatible = "mediatek,mt2701-dpi",
> +	  .data = &mt2701_conf,
> +	},
>  	{ .compatible = "mediatek,mt8173-dpi",
>  	  .data = &mt8173_conf,
>  	},
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 39721119713b..d961112fa2f5 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -424,6 +424,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>  	  .data = (void *)MTK_DSI },
>  	{ .compatible = "mediatek,mt8173-dsi",
>  	  .data = (void *)MTK_DSI },
> +	{ .compatible = "mediatek,mt2701-dpi",
> +	  .data = (void *)MTK_DPI },
>  	{ .compatible = "mediatek,mt8173-dpi",
>  	  .data = (void *)MTK_DPI },
>  	{ .compatible = "mediatek,mt2701-disp-mutex",

Re: [PATCH v2 09/13] drm/mediatek: add support for SPDIF audio in HDMI

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> add support for SPDIF audio  in HDMI
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> ---
>  drivers/gpu/drm/mediatek/mtk_hdmi.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index 2cb33098ec1a..cd8aaeebb436 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -1594,6 +1594,11 @@ static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
>  		hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
>  		hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
>  		break;
> +	case HDMI_SPDIF:
> +		hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
> +		hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
> +		hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
> +		break;
>  	default:
>  		dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
>  			daifmt->fmt);

Re: [PATCH v2 09/13] drm/mediatek: add support for SPDIF audio in HDMI

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> add support for SPDIF audio  in HDMI
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> ---
>  drivers/gpu/drm/mediatek/mtk_hdmi.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index 2cb33098ec1a..cd8aaeebb436 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -1594,6 +1594,11 @@ static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
>  		hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
>  		hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
>  		break;
> +	case HDMI_SPDIF:
> +		hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
> +		hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
> +		hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
> +		break;
>  	default:
>  		dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
>  			daifmt->fmt);

[PATCH v2 09/13] drm/mediatek: add support for SPDIF audio in HDMI

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> add support for SPDIF audio  in HDMI
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> ---
>  drivers/gpu/drm/mediatek/mtk_hdmi.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index 2cb33098ec1a..cd8aaeebb436 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -1594,6 +1594,11 @@ static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
>  		hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
>  		hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
>  		break;
> +	case HDMI_SPDIF:
> +		hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
> +		hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
> +		hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
> +		break;
>  	default:
>  		dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
>  			daifmt->fmt);

Re: [PATCH v2 08/13] drm/mediatek: register hdmi codec more earlier

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> sometimes hdmi reprobe due to encoder probe late,
> but audio dai probe earlier than hdmi. it would make
> audio dai cannot find the hdmi codec. we need to
> register hdmi codec earlier, and the base name which
> used in the register should be PLATFORM_DEVID_NONE,
> otherwise some audio dai dirver could not match it.
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_hdmi.c | 16 +++++++---------
>  1 file changed, 7 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index 7c022f3f53ec..2cb33098ec1a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -1669,15 +1669,14 @@ static void mtk_hdmi_register_audio_driver(struct device *dev)
>  		.max_i2s_channels = 2,
>  		.i2s = 1,
>  	};
> -	struct platform_device *pdev;
> +	static struct platform_device *pdev;
>  
> -	pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
> -					     PLATFORM_DEVID_AUTO, &codec_data,
> -					     sizeof(codec_data));
> -	if (IS_ERR(pdev))
> +	if (!pdev) {
> +		pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
> +						     PLATFORM_DEVID_NONE,
> +						     &codec_data,
> +						     sizeof(codec_data));
> +		DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
> +	}

In the original code, it only register device but not unregister device.
This looks like a bug in hdmi driver. So we need to register and
unregister. You define a 'static' variable here would make
register/unregister asymmetric. And how do you make sure that hdmi
driver is probed before audio dai driver? By the device tree order?
Device tree older may vary for each SoC. I would like more general
solution to make sure that hdmi driver is probed before audio dai
driver. There are some method to make drivers probe in order, so try to
use the better method.

Regards,
CK

>  		return;
> -
> -	DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
>  }
>  
>  static int mtk_drm_hdmi_probe(struct platform_device *pdev)
> @@ -1691,6 +1690,7 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev)
>  		return -ENOMEM;
>  
>  	hdmi->dev = dev;
> +	mtk_hdmi_register_audio_driver(dev);
>  
>  	ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
>  	if (ret)
> @@ -1704,8 +1704,6 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev)
>  		return ret;
>  	}
>  
> -	mtk_hdmi_register_audio_driver(dev);
> -
>  	hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
>  	hdmi->bridge.of_node = pdev->dev.of_node;
>  	drm_bridge_add(&hdmi->bridge);

Re: [PATCH v2 08/13] drm/mediatek: register hdmi codec more earlier

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> sometimes hdmi reprobe due to encoder probe late,
> but audio dai probe earlier than hdmi. it would make
> audio dai cannot find the hdmi codec. we need to
> register hdmi codec earlier, and the base name which
> used in the register should be PLATFORM_DEVID_NONE,
> otherwise some audio dai dirver could not match it.
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_hdmi.c | 16 +++++++---------
>  1 file changed, 7 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index 7c022f3f53ec..2cb33098ec1a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -1669,15 +1669,14 @@ static void mtk_hdmi_register_audio_driver(struct device *dev)
>  		.max_i2s_channels = 2,
>  		.i2s = 1,
>  	};
> -	struct platform_device *pdev;
> +	static struct platform_device *pdev;
>  
> -	pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
> -					     PLATFORM_DEVID_AUTO, &codec_data,
> -					     sizeof(codec_data));
> -	if (IS_ERR(pdev))
> +	if (!pdev) {
> +		pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
> +						     PLATFORM_DEVID_NONE,
> +						     &codec_data,
> +						     sizeof(codec_data));
> +		DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
> +	}

In the original code, it only register device but not unregister device.
This looks like a bug in hdmi driver. So we need to register and
unregister. You define a 'static' variable here would make
register/unregister asymmetric. And how do you make sure that hdmi
driver is probed before audio dai driver? By the device tree order?
Device tree older may vary for each SoC. I would like more general
solution to make sure that hdmi driver is probed before audio dai
driver. There are some method to make drivers probe in order, so try to
use the better method.

Regards,
CK

>  		return;
> -
> -	DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
>  }
>  
>  static int mtk_drm_hdmi_probe(struct platform_device *pdev)
> @@ -1691,6 +1690,7 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev)
>  		return -ENOMEM;
>  
>  	hdmi->dev = dev;
> +	mtk_hdmi_register_audio_driver(dev);
>  
>  	ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
>  	if (ret)
> @@ -1704,8 +1704,6 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev)
>  		return ret;
>  	}
>  
> -	mtk_hdmi_register_audio_driver(dev);
> -
>  	hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
>  	hdmi->bridge.of_node = pdev->dev.of_node;
>  	drm_bridge_add(&hdmi->bridge);


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[PATCH v2 08/13] drm/mediatek: register hdmi codec more earlier

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> sometimes hdmi reprobe due to encoder probe late,
> but audio dai probe earlier than hdmi. it would make
> audio dai cannot find the hdmi codec. we need to
> register hdmi codec earlier, and the base name which
> used in the register should be PLATFORM_DEVID_NONE,
> otherwise some audio dai dirver could not match it.
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_hdmi.c | 16 +++++++---------
>  1 file changed, 7 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index 7c022f3f53ec..2cb33098ec1a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -1669,15 +1669,14 @@ static void mtk_hdmi_register_audio_driver(struct device *dev)
>  		.max_i2s_channels = 2,
>  		.i2s = 1,
>  	};
> -	struct platform_device *pdev;
> +	static struct platform_device *pdev;
>  
> -	pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
> -					     PLATFORM_DEVID_AUTO, &codec_data,
> -					     sizeof(codec_data));
> -	if (IS_ERR(pdev))
> +	if (!pdev) {
> +		pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
> +						     PLATFORM_DEVID_NONE,
> +						     &codec_data,
> +						     sizeof(codec_data));
> +		DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
> +	}

In the original code, it only register device but not unregister device.
This looks like a bug in hdmi driver. So we need to register and
unregister. You define a 'static' variable here would make
register/unregister asymmetric. And how do you make sure that hdmi
driver is probed before audio dai driver? By the device tree order?
Device tree older may vary for each SoC. I would like more general
solution to make sure that hdmi driver is probed before audio dai
driver. There are some method to make drivers probe in order, so try to
use the better method.

Regards,
CK

>  		return;
> -
> -	DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
>  }
>  
>  static int mtk_drm_hdmi_probe(struct platform_device *pdev)
> @@ -1691,6 +1690,7 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev)
>  		return -ENOMEM;
>  
>  	hdmi->dev = dev;
> +	mtk_hdmi_register_audio_driver(dev);
>  
>  	ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
>  	if (ret)
> @@ -1704,8 +1704,6 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev)
>  		return ret;
>  	}
>  
> -	mtk_hdmi_register_audio_driver(dev);
> -
>  	hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
>  	hdmi->bridge.of_node = pdev->dev.of_node;
>  	drm_bridge_add(&hdmi->bridge);

Re: [PATCH v2 11/13] drm/mediatek: implement connection from BLS to DPI0

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> Modify display driver to support connection from BLS to DPI.
> 
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> ---
>  drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 19 ++++++++++++++++++-
>  1 file changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index 87e4191c250e..cc8d49e60c7e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -39,6 +39,7 @@
>  #define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
>  #define DISP_REG_CONFIG_OUT_SEL			0x04c
>  #define DISP_REG_CONFIG_DSI_SEL			0x050
> +#define DISP_REG_CONFIG_DPI_SEL			0x064
>  
>  #define DISP_REG_MUTEX_EN(n)	(0x20 + 0x20 * (n))
>  #define DISP_REG_MUTEX(n)	(0x24 + 0x20 * (n))
> @@ -132,7 +133,11 @@
>  
>  #define OVL_MOUT_EN_RDMA		0x1
>  #define BLS_TO_DSI_RDMA1_TO_DPI1	0x8
> +#define BLS_TO_DPI_RDMA1_TO_DSI		0x2
>  #define DSI_SEL_IN_BLS			0x0
> +#define DPI_SEL_IN_BLS			0x0
> +#define DSI_SEL_IN_RDMA			0x1
> +#define DPI_SEL_IN_RDMA			0x1
>  
>  struct mtk_disp_mutex {
>  	int id;
> @@ -323,9 +328,21 @@ static void mtk_ddp_sout_sel(void __iomem *config_regs,
>  			     enum mtk_ddp_comp_id cur,
>  			     enum mtk_ddp_comp_id next)
>  {
> -	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0)
> +	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>  		writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
>  			       config_regs + DISP_REG_CONFIG_OUT_SEL);
> +		writel_relaxed(DSI_SEL_IN_BLS,
> +			       config_regs + DISP_REG_CONFIG_DSI_SEL);
> +		writel_relaxed(DPI_SEL_IN_RDMA,
> +			       config_regs + DISP_REG_CONFIG_DPI_SEL);
> +	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> +		writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
> +			       config_regs + DISP_REG_CONFIG_OUT_SEL);
> +		writel_relaxed(DSI_SEL_IN_RDMA,
> +			       config_regs + DISP_REG_CONFIG_DSI_SEL);
> +		writel_relaxed(DPI_SEL_IN_BLS,
> +			       config_regs + DISP_REG_CONFIG_DPI_SEL);
> +	}
>  }
>  
>  void mtk_ddp_add_comp_to_path(void __iomem *config_regs,

Re: [PATCH v2 11/13] drm/mediatek: implement connection from BLS to DPI0

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> Modify display driver to support connection from BLS to DPI.
> 
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> ---
>  drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 19 ++++++++++++++++++-
>  1 file changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index 87e4191c250e..cc8d49e60c7e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -39,6 +39,7 @@
>  #define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
>  #define DISP_REG_CONFIG_OUT_SEL			0x04c
>  #define DISP_REG_CONFIG_DSI_SEL			0x050
> +#define DISP_REG_CONFIG_DPI_SEL			0x064
>  
>  #define DISP_REG_MUTEX_EN(n)	(0x20 + 0x20 * (n))
>  #define DISP_REG_MUTEX(n)	(0x24 + 0x20 * (n))
> @@ -132,7 +133,11 @@
>  
>  #define OVL_MOUT_EN_RDMA		0x1
>  #define BLS_TO_DSI_RDMA1_TO_DPI1	0x8
> +#define BLS_TO_DPI_RDMA1_TO_DSI		0x2
>  #define DSI_SEL_IN_BLS			0x0
> +#define DPI_SEL_IN_BLS			0x0
> +#define DSI_SEL_IN_RDMA			0x1
> +#define DPI_SEL_IN_RDMA			0x1
>  
>  struct mtk_disp_mutex {
>  	int id;
> @@ -323,9 +328,21 @@ static void mtk_ddp_sout_sel(void __iomem *config_regs,
>  			     enum mtk_ddp_comp_id cur,
>  			     enum mtk_ddp_comp_id next)
>  {
> -	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0)
> +	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>  		writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
>  			       config_regs + DISP_REG_CONFIG_OUT_SEL);
> +		writel_relaxed(DSI_SEL_IN_BLS,
> +			       config_regs + DISP_REG_CONFIG_DSI_SEL);
> +		writel_relaxed(DPI_SEL_IN_RDMA,
> +			       config_regs + DISP_REG_CONFIG_DPI_SEL);
> +	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> +		writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
> +			       config_regs + DISP_REG_CONFIG_OUT_SEL);
> +		writel_relaxed(DSI_SEL_IN_RDMA,
> +			       config_regs + DISP_REG_CONFIG_DSI_SEL);
> +		writel_relaxed(DPI_SEL_IN_BLS,
> +			       config_regs + DISP_REG_CONFIG_DPI_SEL);
> +	}
>  }
>  
>  void mtk_ddp_add_comp_to_path(void __iomem *config_regs,


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[PATCH v2 11/13] drm/mediatek: implement connection from BLS to DPI0

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> Modify display driver to support connection from BLS to DPI.
> 
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> ---
>  drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 19 ++++++++++++++++++-
>  1 file changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index 87e4191c250e..cc8d49e60c7e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -39,6 +39,7 @@
>  #define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
>  #define DISP_REG_CONFIG_OUT_SEL			0x04c
>  #define DISP_REG_CONFIG_DSI_SEL			0x050
> +#define DISP_REG_CONFIG_DPI_SEL			0x064
>  
>  #define DISP_REG_MUTEX_EN(n)	(0x20 + 0x20 * (n))
>  #define DISP_REG_MUTEX(n)	(0x24 + 0x20 * (n))
> @@ -132,7 +133,11 @@
>  
>  #define OVL_MOUT_EN_RDMA		0x1
>  #define BLS_TO_DSI_RDMA1_TO_DPI1	0x8
> +#define BLS_TO_DPI_RDMA1_TO_DSI		0x2
>  #define DSI_SEL_IN_BLS			0x0
> +#define DPI_SEL_IN_BLS			0x0
> +#define DSI_SEL_IN_RDMA			0x1
> +#define DPI_SEL_IN_RDMA			0x1
>  
>  struct mtk_disp_mutex {
>  	int id;
> @@ -323,9 +328,21 @@ static void mtk_ddp_sout_sel(void __iomem *config_regs,
>  			     enum mtk_ddp_comp_id cur,
>  			     enum mtk_ddp_comp_id next)
>  {
> -	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0)
> +	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>  		writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
>  			       config_regs + DISP_REG_CONFIG_OUT_SEL);
> +		writel_relaxed(DSI_SEL_IN_BLS,
> +			       config_regs + DISP_REG_CONFIG_DSI_SEL);
> +		writel_relaxed(DPI_SEL_IN_RDMA,
> +			       config_regs + DISP_REG_CONFIG_DPI_SEL);
> +	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> +		writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
> +			       config_regs + DISP_REG_CONFIG_OUT_SEL);
> +		writel_relaxed(DSI_SEL_IN_RDMA,
> +			       config_regs + DISP_REG_CONFIG_DSI_SEL);
> +		writel_relaxed(DPI_SEL_IN_BLS,
> +			       config_regs + DISP_REG_CONFIG_DPI_SEL);
> +	}
>  }
>  
>  void mtk_ddp_add_comp_to_path(void __iomem *config_regs,

Re: [PATCH v2 13/13] drm/mediatek: config component output by device node port

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> We can select output component by decive node port.
> Main path default output component is DSI.
> External path default output component is DPI.
> 
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c | 37 ++++++++++++++++++++++++++++++----
>  drivers/gpu/drm/mediatek/mtk_drm_drv.h |  4 ++--
>  2 files changed, 35 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index d961112fa2f5..a477fb878c06 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -21,7 +21,9 @@
>  #include <drm/drm_of.h>
>  #include <linux/component.h>
>  #include <linux/iommu.h>
> +#include <linux/of.h>
>  #include <linux/of_address.h>
> +#include <linux/of_graph.h>
>  #include <linux/of_platform.h>
>  #include <linux/pm_runtime.h>
>  
> @@ -133,7 +135,7 @@ static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
>  	.atomic_commit = mtk_atomic_commit,
>  };
>  
> -static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
> +static enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
>  	DDP_COMPONENT_OVL0,
>  	DDP_COMPONENT_RDMA0,
>  	DDP_COMPONENT_COLOR0,
> @@ -141,7 +143,7 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
>  	DDP_COMPONENT_DSI0,
>  };
>  
> -static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
> +static enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
>  	DDP_COMPONENT_RDMA1,
>  	DDP_COMPONENT_DPI0,
>  };
> @@ -172,7 +174,7 @@ static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = {
>  	DDP_COMPONENT_PWM2,
>  };
>  
> -static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
> +static enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
>  	DDP_COMPONENT_OVL0,
>  	DDP_COMPONENT_COLOR0,
>  	DDP_COMPONENT_AAL0,
> @@ -183,7 +185,7 @@ static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
>  	DDP_COMPONENT_PWM0,
>  };
>  
> -static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
> +static enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
>  	DDP_COMPONENT_OVL1,
>  	DDP_COMPONENT_COLOR1,
>  	DDP_COMPONENT_GAMMA,
> @@ -472,6 +474,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
>  
>  	/* Iterate over sibling DISP function blocks */
>  	for_each_child_of_node(dev->of_node->parent, node) {
> +		struct device_node *port, *ep, *remote;
>  		const struct of_device_id *of_id;
>  		enum mtk_ddp_comp_type comp_type;
>  		int comp_id;
> @@ -531,6 +534,32 @@ static int mtk_drm_probe(struct platform_device *pdev)
>  
>  			private->ddp_comp[comp_id] = comp;
>  		}
> +
> +		if (comp_type != MTK_DSI && comp_type != MTK_DPI) {
> +			port = of_graph_get_port_by_id(node, 0);
> +			if (!port)
> +				continue;
> +			ep = of_get_child_by_name(port, "endpoint");
> +			of_node_put(port);
> +			if (!ep)
> +				continue;
> +			remote = of_graph_get_remote_port_parent(ep);
> +			of_node_put(ep);
> +			if (!remote)
> +				continue;
> +			of_id = of_match_node(mtk_ddp_comp_dt_ids, remote);
> +			if (!of_id)
> +				continue;
> +			comp_type = (enum mtk_ddp_comp_type)of_id->data;
> +			for (i = 0; i < private->data->main_len - 1; i++)
> +				if (private->data->main_path[i] == comp_id)
> +					private->data->main_path[i + 1] =
> +					mtk_ddp_comp_get_id(node, comp_type);
> +			for (i = 0; i < private->data->ext_len - 1; i++)
> +				if (private->data->ext_path[i] == comp_id)
> +					private->data->ext_path[i + 1] =
> +					mtk_ddp_comp_get_id(node, comp_type);
> +		}

I think you should add description in binding document
(Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt)
for this. After the binding document is fully reviewed, we could start
to review this patch.

Regards,
CK

>  	}
>  
>  	if (!private->mutex_node) {
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index ecc00ca3221d..256a3ff2e66e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -29,9 +29,9 @@ struct drm_property;
>  struct regmap;
>  
>  struct mtk_mmsys_driver_data {
> -	const enum mtk_ddp_comp_id *main_path;
> +	enum mtk_ddp_comp_id *main_path;
>  	unsigned int main_len;
> -	const enum mtk_ddp_comp_id *ext_path;
> +	enum mtk_ddp_comp_id *ext_path;
>  	unsigned int ext_len;
>  	const enum mtk_ddp_comp_id *third_path;
>  	unsigned int third_len;

Re: [PATCH v2 13/13] drm/mediatek: config component output by device node port

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> We can select output component by decive node port.
> Main path default output component is DSI.
> External path default output component is DPI.
> 
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c | 37 ++++++++++++++++++++++++++++++----
>  drivers/gpu/drm/mediatek/mtk_drm_drv.h |  4 ++--
>  2 files changed, 35 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index d961112fa2f5..a477fb878c06 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -21,7 +21,9 @@
>  #include <drm/drm_of.h>
>  #include <linux/component.h>
>  #include <linux/iommu.h>
> +#include <linux/of.h>
>  #include <linux/of_address.h>
> +#include <linux/of_graph.h>
>  #include <linux/of_platform.h>
>  #include <linux/pm_runtime.h>
>  
> @@ -133,7 +135,7 @@ static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
>  	.atomic_commit = mtk_atomic_commit,
>  };
>  
> -static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
> +static enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
>  	DDP_COMPONENT_OVL0,
>  	DDP_COMPONENT_RDMA0,
>  	DDP_COMPONENT_COLOR0,
> @@ -141,7 +143,7 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
>  	DDP_COMPONENT_DSI0,
>  };
>  
> -static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
> +static enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
>  	DDP_COMPONENT_RDMA1,
>  	DDP_COMPONENT_DPI0,
>  };
> @@ -172,7 +174,7 @@ static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = {
>  	DDP_COMPONENT_PWM2,
>  };
>  
> -static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
> +static enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
>  	DDP_COMPONENT_OVL0,
>  	DDP_COMPONENT_COLOR0,
>  	DDP_COMPONENT_AAL0,
> @@ -183,7 +185,7 @@ static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
>  	DDP_COMPONENT_PWM0,
>  };
>  
> -static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
> +static enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
>  	DDP_COMPONENT_OVL1,
>  	DDP_COMPONENT_COLOR1,
>  	DDP_COMPONENT_GAMMA,
> @@ -472,6 +474,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
>  
>  	/* Iterate over sibling DISP function blocks */
>  	for_each_child_of_node(dev->of_node->parent, node) {
> +		struct device_node *port, *ep, *remote;
>  		const struct of_device_id *of_id;
>  		enum mtk_ddp_comp_type comp_type;
>  		int comp_id;
> @@ -531,6 +534,32 @@ static int mtk_drm_probe(struct platform_device *pdev)
>  
>  			private->ddp_comp[comp_id] = comp;
>  		}
> +
> +		if (comp_type != MTK_DSI && comp_type != MTK_DPI) {
> +			port = of_graph_get_port_by_id(node, 0);
> +			if (!port)
> +				continue;
> +			ep = of_get_child_by_name(port, "endpoint");
> +			of_node_put(port);
> +			if (!ep)
> +				continue;
> +			remote = of_graph_get_remote_port_parent(ep);
> +			of_node_put(ep);
> +			if (!remote)
> +				continue;
> +			of_id = of_match_node(mtk_ddp_comp_dt_ids, remote);
> +			if (!of_id)
> +				continue;
> +			comp_type = (enum mtk_ddp_comp_type)of_id->data;
> +			for (i = 0; i < private->data->main_len - 1; i++)
> +				if (private->data->main_path[i] == comp_id)
> +					private->data->main_path[i + 1] =
> +					mtk_ddp_comp_get_id(node, comp_type);
> +			for (i = 0; i < private->data->ext_len - 1; i++)
> +				if (private->data->ext_path[i] == comp_id)
> +					private->data->ext_path[i + 1] =
> +					mtk_ddp_comp_get_id(node, comp_type);
> +		}

I think you should add description in binding document
(Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt)
for this. After the binding document is fully reviewed, we could start
to review this patch.

Regards,
CK

>  	}
>  
>  	if (!private->mutex_node) {
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index ecc00ca3221d..256a3ff2e66e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -29,9 +29,9 @@ struct drm_property;
>  struct regmap;
>  
>  struct mtk_mmsys_driver_data {
> -	const enum mtk_ddp_comp_id *main_path;
> +	enum mtk_ddp_comp_id *main_path;
>  	unsigned int main_len;
> -	const enum mtk_ddp_comp_id *ext_path;
> +	enum mtk_ddp_comp_id *ext_path;
>  	unsigned int ext_len;
>  	const enum mtk_ddp_comp_id *third_path;
>  	unsigned int third_len;


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[PATCH v2 13/13] drm/mediatek: config component output by device node port

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> We can select output component by decive node port.
> Main path default output component is DSI.
> External path default output component is DPI.
> 
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c | 37 ++++++++++++++++++++++++++++++----
>  drivers/gpu/drm/mediatek/mtk_drm_drv.h |  4 ++--
>  2 files changed, 35 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index d961112fa2f5..a477fb878c06 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -21,7 +21,9 @@
>  #include <drm/drm_of.h>
>  #include <linux/component.h>
>  #include <linux/iommu.h>
> +#include <linux/of.h>
>  #include <linux/of_address.h>
> +#include <linux/of_graph.h>
>  #include <linux/of_platform.h>
>  #include <linux/pm_runtime.h>
>  
> @@ -133,7 +135,7 @@ static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
>  	.atomic_commit = mtk_atomic_commit,
>  };
>  
> -static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
> +static enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
>  	DDP_COMPONENT_OVL0,
>  	DDP_COMPONENT_RDMA0,
>  	DDP_COMPONENT_COLOR0,
> @@ -141,7 +143,7 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
>  	DDP_COMPONENT_DSI0,
>  };
>  
> -static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
> +static enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
>  	DDP_COMPONENT_RDMA1,
>  	DDP_COMPONENT_DPI0,
>  };
> @@ -172,7 +174,7 @@ static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = {
>  	DDP_COMPONENT_PWM2,
>  };
>  
> -static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
> +static enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
>  	DDP_COMPONENT_OVL0,
>  	DDP_COMPONENT_COLOR0,
>  	DDP_COMPONENT_AAL0,
> @@ -183,7 +185,7 @@ static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
>  	DDP_COMPONENT_PWM0,
>  };
>  
> -static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
> +static enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
>  	DDP_COMPONENT_OVL1,
>  	DDP_COMPONENT_COLOR1,
>  	DDP_COMPONENT_GAMMA,
> @@ -472,6 +474,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
>  
>  	/* Iterate over sibling DISP function blocks */
>  	for_each_child_of_node(dev->of_node->parent, node) {
> +		struct device_node *port, *ep, *remote;
>  		const struct of_device_id *of_id;
>  		enum mtk_ddp_comp_type comp_type;
>  		int comp_id;
> @@ -531,6 +534,32 @@ static int mtk_drm_probe(struct platform_device *pdev)
>  
>  			private->ddp_comp[comp_id] = comp;
>  		}
> +
> +		if (comp_type != MTK_DSI && comp_type != MTK_DPI) {
> +			port = of_graph_get_port_by_id(node, 0);
> +			if (!port)
> +				continue;
> +			ep = of_get_child_by_name(port, "endpoint");
> +			of_node_put(port);
> +			if (!ep)
> +				continue;
> +			remote = of_graph_get_remote_port_parent(ep);
> +			of_node_put(ep);
> +			if (!remote)
> +				continue;
> +			of_id = of_match_node(mtk_ddp_comp_dt_ids, remote);
> +			if (!of_id)
> +				continue;
> +			comp_type = (enum mtk_ddp_comp_type)of_id->data;
> +			for (i = 0; i < private->data->main_len - 1; i++)
> +				if (private->data->main_path[i] == comp_id)
> +					private->data->main_path[i + 1] =
> +					mtk_ddp_comp_get_id(node, comp_type);
> +			for (i = 0; i < private->data->ext_len - 1; i++)
> +				if (private->data->ext_path[i] == comp_id)
> +					private->data->ext_path[i + 1] =
> +					mtk_ddp_comp_get_id(node, comp_type);
> +		}

I think you should add description in binding document
(Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt)
for this. After the binding document is fully reviewed, we could start
to review this patch.

Regards,
CK

>  	}
>  
>  	if (!private->mutex_node) {
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index ecc00ca3221d..256a3ff2e66e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -29,9 +29,9 @@ struct drm_property;
>  struct regmap;
>  
>  struct mtk_mmsys_driver_data {
> -	const enum mtk_ddp_comp_id *main_path;
> +	enum mtk_ddp_comp_id *main_path;
>  	unsigned int main_len;
> -	const enum mtk_ddp_comp_id *ext_path;
> +	enum mtk_ddp_comp_id *ext_path;
>  	unsigned int ext_len;
>  	const enum mtk_ddp_comp_id *third_path;
>  	unsigned int third_len;

Re: [PATCH v2 07/13] drm/mediatek: separae hdmi phy to different file

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> Different IC has different phy setting of HDMI.
> This patch separaes the phy hardware relate part for mt8173.

I guess 'separae' is 'separate'. Am I right?

Regards,
CK

> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/Makefile              |  15 +--
>  drivers/gpu/drm/mediatek/mtk_hdmi.c            |  30 +++--
>  drivers/gpu/drm/mediatek/mtk_hdmi.h            |  26 +++++
>  drivers/gpu/drm/mediatek/mtk_hdmi_phy.c        | 154 +++++++++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 129 ++-------------------
>  5 files changed, 216 insertions(+), 138 deletions(-)
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> 
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index ce83c396a742..7f947979d68f 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -1,4 +1,12 @@
>  # SPDX-License-Identifier: GPL-2.0
> +mediatek-drm-hdmi-objs := mtk_cec.o \
> +			  mtk_hdmi.o \
> +			  mtk_hdmi_ddc.o \
> +			  mtk_mt8173_hdmi_phy.o \
> +			  mtk_hdmi_phy.o
> +
> +obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
> +
>  mediatek-drm-y := mtk_disp_color.o \
>  		  mtk_disp_ovl.o \
>  		  mtk_disp_rdma.o \
> @@ -14,10 +22,3 @@ mediatek-drm-y := mtk_disp_color.o \
>  		  mtk_dpi.o
>  
>  obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> -
> -mediatek-drm-hdmi-objs := mtk_cec.o \
> -			  mtk_hdmi.o \
> -			  mtk_hdmi_ddc.o \
> -			  mtk_mt8173_hdmi_phy.o
> -
> -obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index 2d45d1dd9554..7c022f3f53ec 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -233,6 +233,7 @@ static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
>  static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
>  {
>  	struct arm_smccc_res res;
> +	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(hdmi->phy);
>  
>  	/*
>  	 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI
> @@ -240,8 +241,13 @@ static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
>  	 * The ARM trusted firmware provides an API for the HDMI driver to set
>  	 * this control bit to enable HDMI output in supervisor mode.
>  	 */
> -	arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, 0x80000000,
> -		      0, 0, 0, 0, 0, &res);
> +	if (hdmi_phy->conf && hdmi_phy->conf->tz_enabled)
> +		arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904,
> +			      0x80000000, 0, 0, 0, 0, 0, &res);
> +	else
> +		regmap_update_bits(hdmi->sys_regmap,
> +				   hdmi->sys_offset + HDMI_SYS_CFG20,
> +				   0x80008005, enable ? 0x80000005 : 0x8000);
>  
>  	regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
>  			   HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
> @@ -1437,6 +1443,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
>  	struct platform_device *cec_pdev;
>  	struct regmap *regmap;
>  	struct resource *mem;
> +	const char *phy_name;
>  	int ret;
>  
>  	ret = mtk_hdmi_get_all_clk(hdmi, np);
> @@ -1445,6 +1452,18 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
>  		return ret;
>  	}
>  
> +	ret = of_property_read_string(np, "phy-names", &phy_name);
> +	if (ret < 0) {
> +		dev_err(dev, "Failed to read phy-names: %d\n", ret);
> +		return ret;
> +	}
> +	hdmi->phy = devm_phy_get(dev, phy_name);
> +	if (IS_ERR(hdmi->phy)) {
> +		ret = PTR_ERR(hdmi->phy);
> +		dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
> +		return ret;
> +	}
> +
>  	/* The CEC module handles HDMI hotplug detection */
>  	cec_np = of_find_compatible_node(np->parent, NULL,
>  					 "mediatek,mt8173-cec");
> @@ -1677,13 +1696,6 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev)
>  	if (ret)
>  		return ret;
>  
> -	hdmi->phy = devm_phy_get(dev, "hdmi");
> -	if (IS_ERR(hdmi->phy)) {
> -		ret = PTR_ERR(hdmi->phy);
> -		dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
> -		return ret;
> -	}
> -
>  	platform_set_drvdata(pdev, hdmi);
>  
>  	ret = mtk_hdmi_output_init(hdmi);
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.h b/drivers/gpu/drm/mediatek/mtk_hdmi.h
> index 6371b3de1ff6..a350a6c9271f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.h
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.h
> @@ -13,11 +13,37 @@
>   */
>  #ifndef _MTK_HDMI_CTRL_H
>  #define _MTK_HDMI_CTRL_H
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +
> +struct mtk_hdmi_phy_conf {
> +	bool tz_enabled;
> +	const struct clk_ops *hdmi_phy_clk_ops;
> +	const struct phy_ops *hdmi_phy_dev_ops;
> +};
> +
> +struct mtk_hdmi_phy {
> +	void __iomem *regs;
> +	struct device *dev;
> +	struct mtk_hdmi_phy_conf *conf;
> +	struct clk *pll;
> +	struct clk_hw pll_hw;
> +	unsigned long pll_rate;
> +	unsigned char drv_imp_clk;
> +	unsigned char drv_imp_d2;
> +	unsigned char drv_imp_d1;
> +	unsigned char drv_imp_d0;
> +	unsigned int ibias;
> +	unsigned int ibias_up;
> +};
>  
>  struct platform_driver;
>  
>  extern struct platform_driver mtk_cec_driver;
>  extern struct platform_driver mtk_hdmi_ddc_driver;
>  extern struct platform_driver mtk_hdmi_phy_driver;
> +extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
>  
>  #endif /* _MTK_HDMI_CTRL_H */
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> new file mode 100644
> index 000000000000..82ed73575e04
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> @@ -0,0 +1,154 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Jie Qiu <jie.qiu@mediatek.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/of.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include "mtk_hdmi.h"
> +
> +static void mtk_hdmi_phy_clk_get_ops(struct mtk_hdmi_phy *hdmi_phy,
> +				     const struct clk_ops **ops)
> +{
> +	if (hdmi_phy && hdmi_phy->conf && hdmi_phy->conf->hdmi_phy_clk_ops)
> +		*ops = hdmi_phy->conf->hdmi_phy_clk_ops;
> +	else
> +		dev_err(hdmi_phy->dev, "Failed to get clk ops of phy\n");
> +}
> +
> +static const struct phy_ops *
> +mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy)
> +{
> +	if (hdmi_phy && hdmi_phy->conf && hdmi_phy->conf->hdmi_phy_dev_ops)
> +		return hdmi_phy->conf->hdmi_phy_dev_ops;
> +	dev_err(hdmi_phy->dev, "Failed to get dev ops of phy\n");
> +		return NULL;
> +}
> +
> +static int mtk_hdmi_phy_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct mtk_hdmi_phy *hdmi_phy;
> +	struct resource *mem;
> +	struct clk *ref_clk;
> +	const char *ref_clk_name;
> +	struct clk_init_data clk_init = {
> +		.num_parents = 1,
> +		.parent_names = (const char * const *)&ref_clk_name,
> +		.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
> +	};
> +
> +	struct phy *phy;
> +	struct phy_provider *phy_provider;
> +	int ret;
> +
> +	hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
> +	if (!hdmi_phy)
> +		return -ENOMEM;
> +
> +	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	hdmi_phy->regs = devm_ioremap_resource(dev, mem);
> +	if (IS_ERR(hdmi_phy->regs)) {
> +		ret = PTR_ERR(hdmi_phy->regs);
> +		dev_err(dev, "Failed to get memory resource: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ref_clk = devm_clk_get(dev, "pll_ref");
> +	if (IS_ERR(ref_clk)) {
> +		ret = PTR_ERR(ref_clk);
> +		dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
> +			ret);
> +		return ret;
> +	}
> +	ref_clk_name = __clk_get_name(ref_clk);
> +
> +	ret = of_property_read_string(dev->of_node, "clock-output-names",
> +				      &clk_init.name);
> +	if (ret < 0) {
> +		dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
> +		return ret;
> +	}
> +
> +	hdmi_phy->dev = dev;
> +	hdmi_phy->conf =
> +		(struct mtk_hdmi_phy_conf *)of_device_get_match_data(dev);
> +	mtk_hdmi_phy_clk_get_ops(hdmi_phy, &clk_init.ops);
> +	hdmi_phy->pll_hw.init = &clk_init;
> +	hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
> +	if (IS_ERR(hdmi_phy->pll)) {
> +		ret = PTR_ERR(hdmi_phy->pll);
> +		dev_err(dev, "Failed to register PLL: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
> +				   &hdmi_phy->ibias);
> +	if (ret < 0) {
> +		dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
> +				   &hdmi_phy->ibias_up);
> +	if (ret < 0) {
> +		dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
> +		return ret;
> +	}
> +
> +	dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
> +	hdmi_phy->drv_imp_clk = 0x30;
> +	hdmi_phy->drv_imp_d2 = 0x30;
> +	hdmi_phy->drv_imp_d1 = 0x30;
> +	hdmi_phy->drv_imp_d0 = 0x30;
> +
> +	phy = devm_phy_create(dev, NULL, mtk_hdmi_phy_dev_get_ops(hdmi_phy));
> +	if (IS_ERR(phy)) {
> +		dev_err(dev, "Failed to create HDMI PHY\n");
> +		return PTR_ERR(phy);
> +	}
> +	phy_set_drvdata(phy, hdmi_phy);
> +
> +	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +	if (IS_ERR(phy_provider)) {
> +		dev_err(dev, "Failed to register HDMI PHY\n");
> +		return PTR_ERR(phy_provider);
> +	}
> +
> +	return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
> +				   hdmi_phy->pll);
> +}
> +
> +static int mtk_hdmi_phy_remove(struct platform_device *pdev)
> +{
> +	return 0;
> +}
> +
> +static const struct of_device_id mtk_hdmi_phy_match[] = {
> +	{ .compatible = "mediatek,mt8173-hdmi-phy",
> +	  .data = &mtk_hdmi_phy_8173_conf,
> +	},
> +	{},
> +};
> +
> +struct platform_driver mtk_hdmi_phy_driver = {
> +	.probe = mtk_hdmi_phy_probe,
> +	.remove = mtk_hdmi_phy_remove,
> +	.driver = {
> +		.name = "mediatek-hdmi-phy",
> +		.of_match_table = mtk_hdmi_phy_match,
> +	},
> +};
> +
> +MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> index 51cb9cfb6646..1a35fdd405d8 100644
> --- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> +++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> @@ -21,6 +21,7 @@
>  #include <linux/phy/phy.h>
>  #include <linux/platform_device.h>
>  #include <linux/types.h>
> +#include "mtk_hdmi.h"
>  
>  #define HDMI_CON0		0x00
>  #define RG_HDMITX_PLL_EN		BIT(31)
> @@ -123,20 +124,6 @@
>  #define RGS_HDMITX_5T1_EDG		(0xf << 4)
>  #define RGS_HDMITX_PLUG_TST		BIT(0)
>  
> -struct mtk_hdmi_phy {
> -	void __iomem *regs;
> -	struct device *dev;
> -	struct clk *pll;
> -	struct clk_hw pll_hw;
> -	unsigned long pll_rate;
> -	u8 drv_imp_clk;
> -	u8 drv_imp_d2;
> -	u8 drv_imp_d1;
> -	u8 drv_imp_d0;
> -	u32 ibias;
> -	u32 ibias_up;
> -};
> -
>  static const u8 PREDIV[3][4] = {
>  	{0x0, 0x0, 0x0, 0x0},	/* 27Mhz */
>  	{0x1, 0x1, 0x1, 0x1},	/* 74Mhz */
> @@ -367,7 +354,7 @@ static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
>  	return hdmi_phy->pll_rate;
>  }
>  
> -static const struct clk_ops mtk_hdmi_pll_ops = {
> +static const struct clk_ops mtk_hdmi_phy_pll_ops = {
>  	.prepare = mtk_hdmi_pll_prepare,
>  	.unprepare = mtk_hdmi_pll_unprepare,
>  	.set_rate = mtk_hdmi_pll_set_rate,
> @@ -414,118 +401,16 @@ static int mtk_hdmi_phy_power_off(struct phy *phy)
>  	return 0;
>  }
>  
> -static const struct phy_ops mtk_hdmi_phy_ops = {
> +static const struct phy_ops mtk_hdmi_phy_dev_ops = {
>  	.power_on = mtk_hdmi_phy_power_on,
>  	.power_off = mtk_hdmi_phy_power_off,
>  	.owner = THIS_MODULE,
>  };
>  
> -static int mtk_hdmi_phy_probe(struct platform_device *pdev)
> -{
> -	struct device *dev = &pdev->dev;
> -	struct mtk_hdmi_phy *hdmi_phy;
> -	struct resource *mem;
> -	struct clk *ref_clk;
> -	const char *ref_clk_name;
> -	struct clk_init_data clk_init = {
> -		.ops = &mtk_hdmi_pll_ops,
> -		.num_parents = 1,
> -		.parent_names = (const char * const *)&ref_clk_name,
> -		.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
> -	};
> -	struct phy *phy;
> -	struct phy_provider *phy_provider;
> -	int ret;
> -
> -	hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
> -	if (!hdmi_phy)
> -		return -ENOMEM;
> -
> -	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	hdmi_phy->regs = devm_ioremap_resource(dev, mem);
> -	if (IS_ERR(hdmi_phy->regs)) {
> -		ret = PTR_ERR(hdmi_phy->regs);
> -		dev_err(dev, "Failed to get memory resource: %d\n", ret);
> -		return ret;
> -	}
> -
> -	ref_clk = devm_clk_get(dev, "pll_ref");
> -	if (IS_ERR(ref_clk)) {
> -		ret = PTR_ERR(ref_clk);
> -		dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
> -			ret);
> -		return ret;
> -	}
> -	ref_clk_name = __clk_get_name(ref_clk);
> -
> -	ret = of_property_read_string(dev->of_node, "clock-output-names",
> -				      &clk_init.name);
> -	if (ret < 0) {
> -		dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
> -		return ret;
> -	}
> -
> -	hdmi_phy->pll_hw.init = &clk_init;
> -	hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
> -	if (IS_ERR(hdmi_phy->pll)) {
> -		ret = PTR_ERR(hdmi_phy->pll);
> -		dev_err(dev, "Failed to register PLL: %d\n", ret);
> -		return ret;
> -	}
> -
> -	ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
> -				   &hdmi_phy->ibias);
> -	if (ret < 0) {
> -		dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
> -		return ret;
> -	}
> -
> -	ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
> -				   &hdmi_phy->ibias_up);
> -	if (ret < 0) {
> -		dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
> -		return ret;
> -	}
> -
> -	dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
> -	hdmi_phy->drv_imp_clk = 0x30;
> -	hdmi_phy->drv_imp_d2 = 0x30;
> -	hdmi_phy->drv_imp_d1 = 0x30;
> -	hdmi_phy->drv_imp_d0 = 0x30;
> -
> -	phy = devm_phy_create(dev, NULL, &mtk_hdmi_phy_ops);
> -	if (IS_ERR(phy)) {
> -		dev_err(dev, "Failed to create HDMI PHY\n");
> -		return PTR_ERR(phy);
> -	}
> -	phy_set_drvdata(phy, hdmi_phy);
> -
> -	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> -	if (IS_ERR(phy_provider))
> -		return PTR_ERR(phy_provider);
> -
> -	hdmi_phy->dev = dev;
> -	return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
> -				   hdmi_phy->pll);
> -}
> -
> -static int mtk_hdmi_phy_remove(struct platform_device *pdev)
> -{
> -	return 0;
> -}
> -
> -static const struct of_device_id mtk_hdmi_phy_match[] = {
> -	{ .compatible = "mediatek,mt8173-hdmi-phy", },
> -	{},
> -};
> -
> -struct platform_driver mtk_hdmi_phy_driver = {
> -	.probe = mtk_hdmi_phy_probe,
> -	.remove = mtk_hdmi_phy_remove,
> -	.driver = {
> -		.name = "mediatek-hdmi-phy",
> -		.of_match_table = mtk_hdmi_phy_match,
> -	},
> +struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = {
> +	.tz_enabled = true,
> +	.hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
> +	.hdmi_phy_dev_ops = &mtk_hdmi_phy_dev_ops,
>  };
>  
>  MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");

Re: [PATCH v2 07/13] drm/mediatek: separae hdmi phy to different file

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> Different IC has different phy setting of HDMI.
> This patch separaes the phy hardware relate part for mt8173.

I guess 'separae' is 'separate'. Am I right?

Regards,
CK

> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/Makefile              |  15 +--
>  drivers/gpu/drm/mediatek/mtk_hdmi.c            |  30 +++--
>  drivers/gpu/drm/mediatek/mtk_hdmi.h            |  26 +++++
>  drivers/gpu/drm/mediatek/mtk_hdmi_phy.c        | 154 +++++++++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 129 ++-------------------
>  5 files changed, 216 insertions(+), 138 deletions(-)
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> 
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index ce83c396a742..7f947979d68f 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -1,4 +1,12 @@
>  # SPDX-License-Identifier: GPL-2.0
> +mediatek-drm-hdmi-objs := mtk_cec.o \
> +			  mtk_hdmi.o \
> +			  mtk_hdmi_ddc.o \
> +			  mtk_mt8173_hdmi_phy.o \
> +			  mtk_hdmi_phy.o
> +
> +obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
> +
>  mediatek-drm-y := mtk_disp_color.o \
>  		  mtk_disp_ovl.o \
>  		  mtk_disp_rdma.o \
> @@ -14,10 +22,3 @@ mediatek-drm-y := mtk_disp_color.o \
>  		  mtk_dpi.o
>  
>  obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> -
> -mediatek-drm-hdmi-objs := mtk_cec.o \
> -			  mtk_hdmi.o \
> -			  mtk_hdmi_ddc.o \
> -			  mtk_mt8173_hdmi_phy.o
> -
> -obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index 2d45d1dd9554..7c022f3f53ec 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -233,6 +233,7 @@ static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
>  static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
>  {
>  	struct arm_smccc_res res;
> +	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(hdmi->phy);
>  
>  	/*
>  	 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI
> @@ -240,8 +241,13 @@ static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
>  	 * The ARM trusted firmware provides an API for the HDMI driver to set
>  	 * this control bit to enable HDMI output in supervisor mode.
>  	 */
> -	arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, 0x80000000,
> -		      0, 0, 0, 0, 0, &res);
> +	if (hdmi_phy->conf && hdmi_phy->conf->tz_enabled)
> +		arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904,
> +			      0x80000000, 0, 0, 0, 0, 0, &res);
> +	else
> +		regmap_update_bits(hdmi->sys_regmap,
> +				   hdmi->sys_offset + HDMI_SYS_CFG20,
> +				   0x80008005, enable ? 0x80000005 : 0x8000);
>  
>  	regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
>  			   HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
> @@ -1437,6 +1443,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
>  	struct platform_device *cec_pdev;
>  	struct regmap *regmap;
>  	struct resource *mem;
> +	const char *phy_name;
>  	int ret;
>  
>  	ret = mtk_hdmi_get_all_clk(hdmi, np);
> @@ -1445,6 +1452,18 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
>  		return ret;
>  	}
>  
> +	ret = of_property_read_string(np, "phy-names", &phy_name);
> +	if (ret < 0) {
> +		dev_err(dev, "Failed to read phy-names: %d\n", ret);
> +		return ret;
> +	}
> +	hdmi->phy = devm_phy_get(dev, phy_name);
> +	if (IS_ERR(hdmi->phy)) {
> +		ret = PTR_ERR(hdmi->phy);
> +		dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
> +		return ret;
> +	}
> +
>  	/* The CEC module handles HDMI hotplug detection */
>  	cec_np = of_find_compatible_node(np->parent, NULL,
>  					 "mediatek,mt8173-cec");
> @@ -1677,13 +1696,6 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev)
>  	if (ret)
>  		return ret;
>  
> -	hdmi->phy = devm_phy_get(dev, "hdmi");
> -	if (IS_ERR(hdmi->phy)) {
> -		ret = PTR_ERR(hdmi->phy);
> -		dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
> -		return ret;
> -	}
> -
>  	platform_set_drvdata(pdev, hdmi);
>  
>  	ret = mtk_hdmi_output_init(hdmi);
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.h b/drivers/gpu/drm/mediatek/mtk_hdmi.h
> index 6371b3de1ff6..a350a6c9271f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.h
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.h
> @@ -13,11 +13,37 @@
>   */
>  #ifndef _MTK_HDMI_CTRL_H
>  #define _MTK_HDMI_CTRL_H
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +
> +struct mtk_hdmi_phy_conf {
> +	bool tz_enabled;
> +	const struct clk_ops *hdmi_phy_clk_ops;
> +	const struct phy_ops *hdmi_phy_dev_ops;
> +};
> +
> +struct mtk_hdmi_phy {
> +	void __iomem *regs;
> +	struct device *dev;
> +	struct mtk_hdmi_phy_conf *conf;
> +	struct clk *pll;
> +	struct clk_hw pll_hw;
> +	unsigned long pll_rate;
> +	unsigned char drv_imp_clk;
> +	unsigned char drv_imp_d2;
> +	unsigned char drv_imp_d1;
> +	unsigned char drv_imp_d0;
> +	unsigned int ibias;
> +	unsigned int ibias_up;
> +};
>  
>  struct platform_driver;
>  
>  extern struct platform_driver mtk_cec_driver;
>  extern struct platform_driver mtk_hdmi_ddc_driver;
>  extern struct platform_driver mtk_hdmi_phy_driver;
> +extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
>  
>  #endif /* _MTK_HDMI_CTRL_H */
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> new file mode 100644
> index 000000000000..82ed73575e04
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> @@ -0,0 +1,154 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Jie Qiu <jie.qiu@mediatek.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/of.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include "mtk_hdmi.h"
> +
> +static void mtk_hdmi_phy_clk_get_ops(struct mtk_hdmi_phy *hdmi_phy,
> +				     const struct clk_ops **ops)
> +{
> +	if (hdmi_phy && hdmi_phy->conf && hdmi_phy->conf->hdmi_phy_clk_ops)
> +		*ops = hdmi_phy->conf->hdmi_phy_clk_ops;
> +	else
> +		dev_err(hdmi_phy->dev, "Failed to get clk ops of phy\n");
> +}
> +
> +static const struct phy_ops *
> +mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy)
> +{
> +	if (hdmi_phy && hdmi_phy->conf && hdmi_phy->conf->hdmi_phy_dev_ops)
> +		return hdmi_phy->conf->hdmi_phy_dev_ops;
> +	dev_err(hdmi_phy->dev, "Failed to get dev ops of phy\n");
> +		return NULL;
> +}
> +
> +static int mtk_hdmi_phy_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct mtk_hdmi_phy *hdmi_phy;
> +	struct resource *mem;
> +	struct clk *ref_clk;
> +	const char *ref_clk_name;
> +	struct clk_init_data clk_init = {
> +		.num_parents = 1,
> +		.parent_names = (const char * const *)&ref_clk_name,
> +		.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
> +	};
> +
> +	struct phy *phy;
> +	struct phy_provider *phy_provider;
> +	int ret;
> +
> +	hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
> +	if (!hdmi_phy)
> +		return -ENOMEM;
> +
> +	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	hdmi_phy->regs = devm_ioremap_resource(dev, mem);
> +	if (IS_ERR(hdmi_phy->regs)) {
> +		ret = PTR_ERR(hdmi_phy->regs);
> +		dev_err(dev, "Failed to get memory resource: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ref_clk = devm_clk_get(dev, "pll_ref");
> +	if (IS_ERR(ref_clk)) {
> +		ret = PTR_ERR(ref_clk);
> +		dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
> +			ret);
> +		return ret;
> +	}
> +	ref_clk_name = __clk_get_name(ref_clk);
> +
> +	ret = of_property_read_string(dev->of_node, "clock-output-names",
> +				      &clk_init.name);
> +	if (ret < 0) {
> +		dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
> +		return ret;
> +	}
> +
> +	hdmi_phy->dev = dev;
> +	hdmi_phy->conf =
> +		(struct mtk_hdmi_phy_conf *)of_device_get_match_data(dev);
> +	mtk_hdmi_phy_clk_get_ops(hdmi_phy, &clk_init.ops);
> +	hdmi_phy->pll_hw.init = &clk_init;
> +	hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
> +	if (IS_ERR(hdmi_phy->pll)) {
> +		ret = PTR_ERR(hdmi_phy->pll);
> +		dev_err(dev, "Failed to register PLL: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
> +				   &hdmi_phy->ibias);
> +	if (ret < 0) {
> +		dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
> +				   &hdmi_phy->ibias_up);
> +	if (ret < 0) {
> +		dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
> +		return ret;
> +	}
> +
> +	dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
> +	hdmi_phy->drv_imp_clk = 0x30;
> +	hdmi_phy->drv_imp_d2 = 0x30;
> +	hdmi_phy->drv_imp_d1 = 0x30;
> +	hdmi_phy->drv_imp_d0 = 0x30;
> +
> +	phy = devm_phy_create(dev, NULL, mtk_hdmi_phy_dev_get_ops(hdmi_phy));
> +	if (IS_ERR(phy)) {
> +		dev_err(dev, "Failed to create HDMI PHY\n");
> +		return PTR_ERR(phy);
> +	}
> +	phy_set_drvdata(phy, hdmi_phy);
> +
> +	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +	if (IS_ERR(phy_provider)) {
> +		dev_err(dev, "Failed to register HDMI PHY\n");
> +		return PTR_ERR(phy_provider);
> +	}
> +
> +	return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
> +				   hdmi_phy->pll);
> +}
> +
> +static int mtk_hdmi_phy_remove(struct platform_device *pdev)
> +{
> +	return 0;
> +}
> +
> +static const struct of_device_id mtk_hdmi_phy_match[] = {
> +	{ .compatible = "mediatek,mt8173-hdmi-phy",
> +	  .data = &mtk_hdmi_phy_8173_conf,
> +	},
> +	{},
> +};
> +
> +struct platform_driver mtk_hdmi_phy_driver = {
> +	.probe = mtk_hdmi_phy_probe,
> +	.remove = mtk_hdmi_phy_remove,
> +	.driver = {
> +		.name = "mediatek-hdmi-phy",
> +		.of_match_table = mtk_hdmi_phy_match,
> +	},
> +};
> +
> +MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> index 51cb9cfb6646..1a35fdd405d8 100644
> --- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> +++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> @@ -21,6 +21,7 @@
>  #include <linux/phy/phy.h>
>  #include <linux/platform_device.h>
>  #include <linux/types.h>
> +#include "mtk_hdmi.h"
>  
>  #define HDMI_CON0		0x00
>  #define RG_HDMITX_PLL_EN		BIT(31)
> @@ -123,20 +124,6 @@
>  #define RGS_HDMITX_5T1_EDG		(0xf << 4)
>  #define RGS_HDMITX_PLUG_TST		BIT(0)
>  
> -struct mtk_hdmi_phy {
> -	void __iomem *regs;
> -	struct device *dev;
> -	struct clk *pll;
> -	struct clk_hw pll_hw;
> -	unsigned long pll_rate;
> -	u8 drv_imp_clk;
> -	u8 drv_imp_d2;
> -	u8 drv_imp_d1;
> -	u8 drv_imp_d0;
> -	u32 ibias;
> -	u32 ibias_up;
> -};
> -
>  static const u8 PREDIV[3][4] = {
>  	{0x0, 0x0, 0x0, 0x0},	/* 27Mhz */
>  	{0x1, 0x1, 0x1, 0x1},	/* 74Mhz */
> @@ -367,7 +354,7 @@ static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
>  	return hdmi_phy->pll_rate;
>  }
>  
> -static const struct clk_ops mtk_hdmi_pll_ops = {
> +static const struct clk_ops mtk_hdmi_phy_pll_ops = {
>  	.prepare = mtk_hdmi_pll_prepare,
>  	.unprepare = mtk_hdmi_pll_unprepare,
>  	.set_rate = mtk_hdmi_pll_set_rate,
> @@ -414,118 +401,16 @@ static int mtk_hdmi_phy_power_off(struct phy *phy)
>  	return 0;
>  }
>  
> -static const struct phy_ops mtk_hdmi_phy_ops = {
> +static const struct phy_ops mtk_hdmi_phy_dev_ops = {
>  	.power_on = mtk_hdmi_phy_power_on,
>  	.power_off = mtk_hdmi_phy_power_off,
>  	.owner = THIS_MODULE,
>  };
>  
> -static int mtk_hdmi_phy_probe(struct platform_device *pdev)
> -{
> -	struct device *dev = &pdev->dev;
> -	struct mtk_hdmi_phy *hdmi_phy;
> -	struct resource *mem;
> -	struct clk *ref_clk;
> -	const char *ref_clk_name;
> -	struct clk_init_data clk_init = {
> -		.ops = &mtk_hdmi_pll_ops,
> -		.num_parents = 1,
> -		.parent_names = (const char * const *)&ref_clk_name,
> -		.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
> -	};
> -	struct phy *phy;
> -	struct phy_provider *phy_provider;
> -	int ret;
> -
> -	hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
> -	if (!hdmi_phy)
> -		return -ENOMEM;
> -
> -	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	hdmi_phy->regs = devm_ioremap_resource(dev, mem);
> -	if (IS_ERR(hdmi_phy->regs)) {
> -		ret = PTR_ERR(hdmi_phy->regs);
> -		dev_err(dev, "Failed to get memory resource: %d\n", ret);
> -		return ret;
> -	}
> -
> -	ref_clk = devm_clk_get(dev, "pll_ref");
> -	if (IS_ERR(ref_clk)) {
> -		ret = PTR_ERR(ref_clk);
> -		dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
> -			ret);
> -		return ret;
> -	}
> -	ref_clk_name = __clk_get_name(ref_clk);
> -
> -	ret = of_property_read_string(dev->of_node, "clock-output-names",
> -				      &clk_init.name);
> -	if (ret < 0) {
> -		dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
> -		return ret;
> -	}
> -
> -	hdmi_phy->pll_hw.init = &clk_init;
> -	hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
> -	if (IS_ERR(hdmi_phy->pll)) {
> -		ret = PTR_ERR(hdmi_phy->pll);
> -		dev_err(dev, "Failed to register PLL: %d\n", ret);
> -		return ret;
> -	}
> -
> -	ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
> -				   &hdmi_phy->ibias);
> -	if (ret < 0) {
> -		dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
> -		return ret;
> -	}
> -
> -	ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
> -				   &hdmi_phy->ibias_up);
> -	if (ret < 0) {
> -		dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
> -		return ret;
> -	}
> -
> -	dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
> -	hdmi_phy->drv_imp_clk = 0x30;
> -	hdmi_phy->drv_imp_d2 = 0x30;
> -	hdmi_phy->drv_imp_d1 = 0x30;
> -	hdmi_phy->drv_imp_d0 = 0x30;
> -
> -	phy = devm_phy_create(dev, NULL, &mtk_hdmi_phy_ops);
> -	if (IS_ERR(phy)) {
> -		dev_err(dev, "Failed to create HDMI PHY\n");
> -		return PTR_ERR(phy);
> -	}
> -	phy_set_drvdata(phy, hdmi_phy);
> -
> -	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> -	if (IS_ERR(phy_provider))
> -		return PTR_ERR(phy_provider);
> -
> -	hdmi_phy->dev = dev;
> -	return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
> -				   hdmi_phy->pll);
> -}
> -
> -static int mtk_hdmi_phy_remove(struct platform_device *pdev)
> -{
> -	return 0;
> -}
> -
> -static const struct of_device_id mtk_hdmi_phy_match[] = {
> -	{ .compatible = "mediatek,mt8173-hdmi-phy", },
> -	{},
> -};
> -
> -struct platform_driver mtk_hdmi_phy_driver = {
> -	.probe = mtk_hdmi_phy_probe,
> -	.remove = mtk_hdmi_phy_remove,
> -	.driver = {
> -		.name = "mediatek-hdmi-phy",
> -		.of_match_table = mtk_hdmi_phy_match,
> -	},
> +struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = {
> +	.tz_enabled = true,
> +	.hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
> +	.hdmi_phy_dev_ops = &mtk_hdmi_phy_dev_ops,
>  };
>  
>  MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");


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[PATCH v2 07/13] drm/mediatek: separae hdmi phy to different file

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> Different IC has different phy setting of HDMI.
> This patch separaes the phy hardware relate part for mt8173.

I guess 'separae' is 'separate'. Am I right?

Regards,
CK

> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/Makefile              |  15 +--
>  drivers/gpu/drm/mediatek/mtk_hdmi.c            |  30 +++--
>  drivers/gpu/drm/mediatek/mtk_hdmi.h            |  26 +++++
>  drivers/gpu/drm/mediatek/mtk_hdmi_phy.c        | 154 +++++++++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 129 ++-------------------
>  5 files changed, 216 insertions(+), 138 deletions(-)
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> 
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index ce83c396a742..7f947979d68f 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -1,4 +1,12 @@
>  # SPDX-License-Identifier: GPL-2.0
> +mediatek-drm-hdmi-objs := mtk_cec.o \
> +			  mtk_hdmi.o \
> +			  mtk_hdmi_ddc.o \
> +			  mtk_mt8173_hdmi_phy.o \
> +			  mtk_hdmi_phy.o
> +
> +obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
> +
>  mediatek-drm-y := mtk_disp_color.o \
>  		  mtk_disp_ovl.o \
>  		  mtk_disp_rdma.o \
> @@ -14,10 +22,3 @@ mediatek-drm-y := mtk_disp_color.o \
>  		  mtk_dpi.o
>  
>  obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> -
> -mediatek-drm-hdmi-objs := mtk_cec.o \
> -			  mtk_hdmi.o \
> -			  mtk_hdmi_ddc.o \
> -			  mtk_mt8173_hdmi_phy.o
> -
> -obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index 2d45d1dd9554..7c022f3f53ec 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -233,6 +233,7 @@ static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
>  static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
>  {
>  	struct arm_smccc_res res;
> +	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(hdmi->phy);
>  
>  	/*
>  	 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI
> @@ -240,8 +241,13 @@ static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
>  	 * The ARM trusted firmware provides an API for the HDMI driver to set
>  	 * this control bit to enable HDMI output in supervisor mode.
>  	 */
> -	arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, 0x80000000,
> -		      0, 0, 0, 0, 0, &res);
> +	if (hdmi_phy->conf && hdmi_phy->conf->tz_enabled)
> +		arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904,
> +			      0x80000000, 0, 0, 0, 0, 0, &res);
> +	else
> +		regmap_update_bits(hdmi->sys_regmap,
> +				   hdmi->sys_offset + HDMI_SYS_CFG20,
> +				   0x80008005, enable ? 0x80000005 : 0x8000);
>  
>  	regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
>  			   HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
> @@ -1437,6 +1443,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
>  	struct platform_device *cec_pdev;
>  	struct regmap *regmap;
>  	struct resource *mem;
> +	const char *phy_name;
>  	int ret;
>  
>  	ret = mtk_hdmi_get_all_clk(hdmi, np);
> @@ -1445,6 +1452,18 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
>  		return ret;
>  	}
>  
> +	ret = of_property_read_string(np, "phy-names", &phy_name);
> +	if (ret < 0) {
> +		dev_err(dev, "Failed to read phy-names: %d\n", ret);
> +		return ret;
> +	}
> +	hdmi->phy = devm_phy_get(dev, phy_name);
> +	if (IS_ERR(hdmi->phy)) {
> +		ret = PTR_ERR(hdmi->phy);
> +		dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
> +		return ret;
> +	}
> +
>  	/* The CEC module handles HDMI hotplug detection */
>  	cec_np = of_find_compatible_node(np->parent, NULL,
>  					 "mediatek,mt8173-cec");
> @@ -1677,13 +1696,6 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev)
>  	if (ret)
>  		return ret;
>  
> -	hdmi->phy = devm_phy_get(dev, "hdmi");
> -	if (IS_ERR(hdmi->phy)) {
> -		ret = PTR_ERR(hdmi->phy);
> -		dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
> -		return ret;
> -	}
> -
>  	platform_set_drvdata(pdev, hdmi);
>  
>  	ret = mtk_hdmi_output_init(hdmi);
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.h b/drivers/gpu/drm/mediatek/mtk_hdmi.h
> index 6371b3de1ff6..a350a6c9271f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.h
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.h
> @@ -13,11 +13,37 @@
>   */
>  #ifndef _MTK_HDMI_CTRL_H
>  #define _MTK_HDMI_CTRL_H
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +
> +struct mtk_hdmi_phy_conf {
> +	bool tz_enabled;
> +	const struct clk_ops *hdmi_phy_clk_ops;
> +	const struct phy_ops *hdmi_phy_dev_ops;
> +};
> +
> +struct mtk_hdmi_phy {
> +	void __iomem *regs;
> +	struct device *dev;
> +	struct mtk_hdmi_phy_conf *conf;
> +	struct clk *pll;
> +	struct clk_hw pll_hw;
> +	unsigned long pll_rate;
> +	unsigned char drv_imp_clk;
> +	unsigned char drv_imp_d2;
> +	unsigned char drv_imp_d1;
> +	unsigned char drv_imp_d0;
> +	unsigned int ibias;
> +	unsigned int ibias_up;
> +};
>  
>  struct platform_driver;
>  
>  extern struct platform_driver mtk_cec_driver;
>  extern struct platform_driver mtk_hdmi_ddc_driver;
>  extern struct platform_driver mtk_hdmi_phy_driver;
> +extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
>  
>  #endif /* _MTK_HDMI_CTRL_H */
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> new file mode 100644
> index 000000000000..82ed73575e04
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> @@ -0,0 +1,154 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Jie Qiu <jie.qiu@mediatek.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/of.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include "mtk_hdmi.h"
> +
> +static void mtk_hdmi_phy_clk_get_ops(struct mtk_hdmi_phy *hdmi_phy,
> +				     const struct clk_ops **ops)
> +{
> +	if (hdmi_phy && hdmi_phy->conf && hdmi_phy->conf->hdmi_phy_clk_ops)
> +		*ops = hdmi_phy->conf->hdmi_phy_clk_ops;
> +	else
> +		dev_err(hdmi_phy->dev, "Failed to get clk ops of phy\n");
> +}
> +
> +static const struct phy_ops *
> +mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy)
> +{
> +	if (hdmi_phy && hdmi_phy->conf && hdmi_phy->conf->hdmi_phy_dev_ops)
> +		return hdmi_phy->conf->hdmi_phy_dev_ops;
> +	dev_err(hdmi_phy->dev, "Failed to get dev ops of phy\n");
> +		return NULL;
> +}
> +
> +static int mtk_hdmi_phy_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct mtk_hdmi_phy *hdmi_phy;
> +	struct resource *mem;
> +	struct clk *ref_clk;
> +	const char *ref_clk_name;
> +	struct clk_init_data clk_init = {
> +		.num_parents = 1,
> +		.parent_names = (const char * const *)&ref_clk_name,
> +		.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
> +	};
> +
> +	struct phy *phy;
> +	struct phy_provider *phy_provider;
> +	int ret;
> +
> +	hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
> +	if (!hdmi_phy)
> +		return -ENOMEM;
> +
> +	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	hdmi_phy->regs = devm_ioremap_resource(dev, mem);
> +	if (IS_ERR(hdmi_phy->regs)) {
> +		ret = PTR_ERR(hdmi_phy->regs);
> +		dev_err(dev, "Failed to get memory resource: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ref_clk = devm_clk_get(dev, "pll_ref");
> +	if (IS_ERR(ref_clk)) {
> +		ret = PTR_ERR(ref_clk);
> +		dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
> +			ret);
> +		return ret;
> +	}
> +	ref_clk_name = __clk_get_name(ref_clk);
> +
> +	ret = of_property_read_string(dev->of_node, "clock-output-names",
> +				      &clk_init.name);
> +	if (ret < 0) {
> +		dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
> +		return ret;
> +	}
> +
> +	hdmi_phy->dev = dev;
> +	hdmi_phy->conf =
> +		(struct mtk_hdmi_phy_conf *)of_device_get_match_data(dev);
> +	mtk_hdmi_phy_clk_get_ops(hdmi_phy, &clk_init.ops);
> +	hdmi_phy->pll_hw.init = &clk_init;
> +	hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
> +	if (IS_ERR(hdmi_phy->pll)) {
> +		ret = PTR_ERR(hdmi_phy->pll);
> +		dev_err(dev, "Failed to register PLL: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
> +				   &hdmi_phy->ibias);
> +	if (ret < 0) {
> +		dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
> +				   &hdmi_phy->ibias_up);
> +	if (ret < 0) {
> +		dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
> +		return ret;
> +	}
> +
> +	dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
> +	hdmi_phy->drv_imp_clk = 0x30;
> +	hdmi_phy->drv_imp_d2 = 0x30;
> +	hdmi_phy->drv_imp_d1 = 0x30;
> +	hdmi_phy->drv_imp_d0 = 0x30;
> +
> +	phy = devm_phy_create(dev, NULL, mtk_hdmi_phy_dev_get_ops(hdmi_phy));
> +	if (IS_ERR(phy)) {
> +		dev_err(dev, "Failed to create HDMI PHY\n");
> +		return PTR_ERR(phy);
> +	}
> +	phy_set_drvdata(phy, hdmi_phy);
> +
> +	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +	if (IS_ERR(phy_provider)) {
> +		dev_err(dev, "Failed to register HDMI PHY\n");
> +		return PTR_ERR(phy_provider);
> +	}
> +
> +	return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
> +				   hdmi_phy->pll);
> +}
> +
> +static int mtk_hdmi_phy_remove(struct platform_device *pdev)
> +{
> +	return 0;
> +}
> +
> +static const struct of_device_id mtk_hdmi_phy_match[] = {
> +	{ .compatible = "mediatek,mt8173-hdmi-phy",
> +	  .data = &mtk_hdmi_phy_8173_conf,
> +	},
> +	{},
> +};
> +
> +struct platform_driver mtk_hdmi_phy_driver = {
> +	.probe = mtk_hdmi_phy_probe,
> +	.remove = mtk_hdmi_phy_remove,
> +	.driver = {
> +		.name = "mediatek-hdmi-phy",
> +		.of_match_table = mtk_hdmi_phy_match,
> +	},
> +};
> +
> +MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> index 51cb9cfb6646..1a35fdd405d8 100644
> --- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> +++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> @@ -21,6 +21,7 @@
>  #include <linux/phy/phy.h>
>  #include <linux/platform_device.h>
>  #include <linux/types.h>
> +#include "mtk_hdmi.h"
>  
>  #define HDMI_CON0		0x00
>  #define RG_HDMITX_PLL_EN		BIT(31)
> @@ -123,20 +124,6 @@
>  #define RGS_HDMITX_5T1_EDG		(0xf << 4)
>  #define RGS_HDMITX_PLUG_TST		BIT(0)
>  
> -struct mtk_hdmi_phy {
> -	void __iomem *regs;
> -	struct device *dev;
> -	struct clk *pll;
> -	struct clk_hw pll_hw;
> -	unsigned long pll_rate;
> -	u8 drv_imp_clk;
> -	u8 drv_imp_d2;
> -	u8 drv_imp_d1;
> -	u8 drv_imp_d0;
> -	u32 ibias;
> -	u32 ibias_up;
> -};
> -
>  static const u8 PREDIV[3][4] = {
>  	{0x0, 0x0, 0x0, 0x0},	/* 27Mhz */
>  	{0x1, 0x1, 0x1, 0x1},	/* 74Mhz */
> @@ -367,7 +354,7 @@ static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
>  	return hdmi_phy->pll_rate;
>  }
>  
> -static const struct clk_ops mtk_hdmi_pll_ops = {
> +static const struct clk_ops mtk_hdmi_phy_pll_ops = {
>  	.prepare = mtk_hdmi_pll_prepare,
>  	.unprepare = mtk_hdmi_pll_unprepare,
>  	.set_rate = mtk_hdmi_pll_set_rate,
> @@ -414,118 +401,16 @@ static int mtk_hdmi_phy_power_off(struct phy *phy)
>  	return 0;
>  }
>  
> -static const struct phy_ops mtk_hdmi_phy_ops = {
> +static const struct phy_ops mtk_hdmi_phy_dev_ops = {
>  	.power_on = mtk_hdmi_phy_power_on,
>  	.power_off = mtk_hdmi_phy_power_off,
>  	.owner = THIS_MODULE,
>  };
>  
> -static int mtk_hdmi_phy_probe(struct platform_device *pdev)
> -{
> -	struct device *dev = &pdev->dev;
> -	struct mtk_hdmi_phy *hdmi_phy;
> -	struct resource *mem;
> -	struct clk *ref_clk;
> -	const char *ref_clk_name;
> -	struct clk_init_data clk_init = {
> -		.ops = &mtk_hdmi_pll_ops,
> -		.num_parents = 1,
> -		.parent_names = (const char * const *)&ref_clk_name,
> -		.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
> -	};
> -	struct phy *phy;
> -	struct phy_provider *phy_provider;
> -	int ret;
> -
> -	hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
> -	if (!hdmi_phy)
> -		return -ENOMEM;
> -
> -	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	hdmi_phy->regs = devm_ioremap_resource(dev, mem);
> -	if (IS_ERR(hdmi_phy->regs)) {
> -		ret = PTR_ERR(hdmi_phy->regs);
> -		dev_err(dev, "Failed to get memory resource: %d\n", ret);
> -		return ret;
> -	}
> -
> -	ref_clk = devm_clk_get(dev, "pll_ref");
> -	if (IS_ERR(ref_clk)) {
> -		ret = PTR_ERR(ref_clk);
> -		dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
> -			ret);
> -		return ret;
> -	}
> -	ref_clk_name = __clk_get_name(ref_clk);
> -
> -	ret = of_property_read_string(dev->of_node, "clock-output-names",
> -				      &clk_init.name);
> -	if (ret < 0) {
> -		dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
> -		return ret;
> -	}
> -
> -	hdmi_phy->pll_hw.init = &clk_init;
> -	hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
> -	if (IS_ERR(hdmi_phy->pll)) {
> -		ret = PTR_ERR(hdmi_phy->pll);
> -		dev_err(dev, "Failed to register PLL: %d\n", ret);
> -		return ret;
> -	}
> -
> -	ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
> -				   &hdmi_phy->ibias);
> -	if (ret < 0) {
> -		dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
> -		return ret;
> -	}
> -
> -	ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
> -				   &hdmi_phy->ibias_up);
> -	if (ret < 0) {
> -		dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
> -		return ret;
> -	}
> -
> -	dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
> -	hdmi_phy->drv_imp_clk = 0x30;
> -	hdmi_phy->drv_imp_d2 = 0x30;
> -	hdmi_phy->drv_imp_d1 = 0x30;
> -	hdmi_phy->drv_imp_d0 = 0x30;
> -
> -	phy = devm_phy_create(dev, NULL, &mtk_hdmi_phy_ops);
> -	if (IS_ERR(phy)) {
> -		dev_err(dev, "Failed to create HDMI PHY\n");
> -		return PTR_ERR(phy);
> -	}
> -	phy_set_drvdata(phy, hdmi_phy);
> -
> -	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> -	if (IS_ERR(phy_provider))
> -		return PTR_ERR(phy_provider);
> -
> -	hdmi_phy->dev = dev;
> -	return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
> -				   hdmi_phy->pll);
> -}
> -
> -static int mtk_hdmi_phy_remove(struct platform_device *pdev)
> -{
> -	return 0;
> -}
> -
> -static const struct of_device_id mtk_hdmi_phy_match[] = {
> -	{ .compatible = "mediatek,mt8173-hdmi-phy", },
> -	{},
> -};
> -
> -struct platform_driver mtk_hdmi_phy_driver = {
> -	.probe = mtk_hdmi_phy_probe,
> -	.remove = mtk_hdmi_phy_remove,
> -	.driver = {
> -		.name = "mediatek-hdmi-phy",
> -		.of_match_table = mtk_hdmi_phy_match,
> -	},
> +struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = {
> +	.tz_enabled = true,
> +	.hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
> +	.hdmi_phy_dev_ops = &mtk_hdmi_phy_dev_ops,
>  };
>  
>  MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");

Re: [PATCH v2 10/13] drm/mediatek: add hdmi driver for MT2701 and MT7623

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> This patch adds hdmi dirver suppot for both MT2701 and MT7623.
> And also support other (existing or future) chips that use
> the same binding and driver.
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/Makefile              |   1 +
>  drivers/gpu/drm/mediatek/mtk_hdmi.h            |   1 +
>  drivers/gpu/drm/mediatek/mtk_hdmi_phy.c        |   3 +
>  drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 307 +++++++++++++++++++++++++
>  4 files changed, 312 insertions(+)
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> 
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 7f947979d68f..bf0067b5ee6f 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -2,6 +2,7 @@
>  mediatek-drm-hdmi-objs := mtk_cec.o \
>  			  mtk_hdmi.o \
>  			  mtk_hdmi_ddc.o \
> +                          mtk_mt2701_hdmi_phy.o \
>  			  mtk_mt8173_hdmi_phy.o \
>  			  mtk_hdmi_phy.o
>  
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.h b/drivers/gpu/drm/mediatek/mtk_hdmi.h
> index a350a6c9271f..fa12eb6288f3 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.h
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.h
> @@ -45,5 +45,6 @@ extern struct platform_driver mtk_cec_driver;
>  extern struct platform_driver mtk_hdmi_ddc_driver;
>  extern struct platform_driver mtk_hdmi_phy_driver;
>  extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
> +extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf;
>  
>  #endif /* _MTK_HDMI_CTRL_H */
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> index 82ed73575e04..606fc7a0c13b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> @@ -135,6 +135,9 @@ static int mtk_hdmi_phy_remove(struct platform_device *pdev)
>  }
>  
>  static const struct of_device_id mtk_hdmi_phy_match[] = {
> +	{ .compatible = "mediatek,mt2701-hdmi-phy",
> +	  .data = &mtk_hdmi_phy_2701_conf,
> +	},
>  	{ .compatible = "mediatek,mt8173-hdmi-phy",
>  	  .data = &mtk_hdmi_phy_8173_conf,
>  	},
> diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> new file mode 100644
> index 000000000000..428ef1557a14
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> @@ -0,0 +1,307 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Chunhui Dai <chunhui.dai@mediatek.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/debugfs.h>

Why need debugfs.h?

> +#include <linux/delay.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/phy/phy.h>
> +#include <linux/slab.h>
> +#include "mtk_hdmi.h"

I don't know why the included file is different in mtk_mt8173_hdmi_phy.c
with this file. The difference of these two files are hardware control,
so I think these two files would include the same header files. If these
two file include the same files, maybe we should move the common include
statement in some header file to prevent duplicate in these two files.

> +
> +#define HDMI_CON0	0x00
> +#define RG_HDMITX_DRV_IBIAS		(0)

You need not to embrace a single number.

> +#define RG_HDMITX_DRV_IBIAS_MASK	(0x3F << 0)

Use lower case for hex number.

> +#define RG_HDMITX_EN_SER		(12)
> +#define RG_HDMITX_EN_SER_MASK		(0x0F << 12)
> +#define RG_HDMITX_EN_SLDO		(16)
> +#define RG_HDMITX_EN_SLDO_MASK		(0x0F << 16)
> +#define RG_HDMITX_EN_PRED		(20)
> +#define RG_HDMITX_EN_PRED_MASK		(0x0F << 20)
> +#define RG_HDMITX_EN_IMP		(24)
> +#define RG_HDMITX_EN_IMP_MASK		(0x0F << 24)
> +#define RG_HDMITX_EN_DRV		(28)
> +#define RG_HDMITX_EN_DRV_MASK		(0x0F << 28)
> +
> +#define HDMI_CON1	0x04
> +#define RG_HDMITX_PRED_IBIAS		(18)
> +#define RG_HDMITX_PRED_IBIAS_MASK	(0x0F << 18)
> +#define RG_HDMITX_PRED_IMP		(0x01 << 22)
> +#define RG_HDMITX_DRV_IMP		(26)
> +#define RG_HDMITX_DRV_IMP_MASK		(0x3F << 26)
> +
> +#define HDMI_CON2	0x08
> +#define RG_HDMITX_EN_TX_CKLDO		(0x01 << 0)
> +#define RG_HDMITX_EN_TX_POSDIV		(0x01 << 1)
> +#define RG_HDMITX_TX_POSDIV		(3)
> +#define RG_HDMITX_TX_POSDIV_MASK	(0x03 << 3)
> +#define RG_HDMITX_EN_MBIAS		(0x01 << 6)
> +#define RG_HDMITX_MBIAS_LPF_EN		(0x01 << 7)
> +
> +#define HDMI_CON4	0x10
> +#define RG_HDMITX_RESERVE_MASK		(0xFFFFFFFF << 0)
> +
> +#define HDMI_CON6	0x18
> +#define RG_HTPLL_BR			(0)
> +#define RG_HTPLL_BR_MASK		(0x03 << 0)
> +#define RG_HTPLL_BC			(2)
> +#define RG_HTPLL_BC_MASK		(0x03 << 2)
> +#define RG_HTPLL_BP			(4)
> +#define RG_HTPLL_BP_MASK		(0x0F << 4)
> +#define RG_HTPLL_IR			(8)
> +#define RG_HTPLL_IR_MASK		(0x0F << 8)
> +#define RG_HTPLL_IC			(12)
> +#define RG_HTPLL_IC_MASK		(0x0F << 12)
> +#define RG_HTPLL_POSDIV			(16)
> +#define RG_HTPLL_POSDIV_MASK		(0x03 << 16)
> +#define RG_HTPLL_PREDIV			(18)
> +#define RG_HTPLL_PREDIV_MASK		(0x03 << 18)
> +#define RG_HTPLL_FBKSEL			(20)
> +#define RG_HTPLL_FBKSEL_MASK		(0x03 << 20)
> +#define RG_HTPLL_RLH_EN			(0x01 << 22)
> +#define RG_HTPLL_FBKDIV			(24)
> +#define RG_HTPLL_FBKDIV_MASK		(0x7F << 24)
> +#define RG_HTPLL_EN			(0x01 << 31)
> +
> +#define HDMI_CON7	0x1c
> +#define RG_HTPLL_AUTOK_EN		(0x01 << 23)
> +#define RG_HTPLL_DIVEN			(28)
> +#define RG_HTPLL_DIVEN_MASK		(0x07 << 28)
> +
> +static inline struct mtk_hdmi_phy *to_mtk_hdmi_pll(struct clk_hw *hw)
> +{
> +	return container_of(hw, struct mtk_hdmi_phy, pll_hw);
> +}

to_mtk_hdmi_pll() is the same as to_mtk_hdmi_phy() in
mtk_mt8173_hdmi_phy.c, I would like the merge these two functions. Maybe
you could these common function to a .h or .c file.

> +
> +static inline void mtk_hdmi_pll_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
> +				     u32 val, u32 mask)
> +{
> +	u32 tmp = readl(hdmi_phy->regs  + offset) & ~mask;
> +
> +	tmp |= (val & mask);
> +	writel(tmp, hdmi_phy->regs + offset);
> +}

Ditto.

> +
> +static int mtk_hdmi_pll_enable(struct clk_hw *hw)
> +{
> +	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
> +
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN,
> +			  RG_HTPLL_AUTOK_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_RLH_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x3 << RG_HTPLL_POSDIV),
> +			  RG_HTPLL_POSDIV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS,
> +			  RG_HDMITX_EN_MBIAS);
> +	usleep_range(80, 100);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, RG_HTPLL_EN, RG_HTPLL_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO,
> +			  RG_HDMITX_EN_TX_CKLDO);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_SLDO),
> +			  RG_HDMITX_EN_SLDO_MASK);
> +	usleep_range(80, 100);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN,
> +			  RG_HDMITX_MBIAS_LPF_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV,
> +			  RG_HDMITX_EN_TX_POSDIV);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_SER),
> +			  RG_HDMITX_EN_SER_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_PRED),
> +			  RG_HDMITX_EN_PRED_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_DRV),
> +			  RG_HDMITX_EN_DRV_MASK);
> +	usleep_range(80, 100);
> +	return 0;
> +}
> +
> +static void mtk_hdmi_pll_disable(struct clk_hw *hw)
> +{
> +	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
> +
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_DRV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_PRED_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_SER_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_TX_POSDIV);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_MBIAS_LPF_EN);
> +	usleep_range(80, 100);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_SLDO_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_TX_CKLDO);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_EN);
> +	usleep_range(80, 100);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_MBIAS);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_POSDIV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_RLH_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, 0, RG_HTPLL_AUTOK_EN);
> +	usleep_range(80, 100);
> +}
> +
> +static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> +				 unsigned long parent_rate)
> +{
> +	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
> +	u32 pos_div;
> +
> +	if (rate <= 64000000)
> +		pos_div = 3;
> +	else if (rate <= 12800000)
> +		pos_div = 1;
> +	else
> +		pos_div = 1;
> +
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x3 << RG_HTPLL_PREDIV),
> +			  RG_HTPLL_PREDIV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x3 << RG_HTPLL_POSDIV),
> +			  RG_HTPLL_POSDIV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IC),
> +			  RG_HTPLL_IC_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IR),
> +			  RG_HTPLL_IR_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, (pos_div << RG_HDMITX_TX_POSDIV),
> +			  RG_HDMITX_TX_POSDIV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (1 << RG_HTPLL_FBKSEL),
> +			  RG_HTPLL_FBKSEL_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (19 << RG_HTPLL_FBKDIV),
> +			  RG_HTPLL_FBKDIV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, (0x2 << RG_HTPLL_DIVEN),
> +			  RG_HTPLL_DIVEN_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0xc << RG_HTPLL_BP),
> +			  RG_HTPLL_BP_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x2 << RG_HTPLL_BC),
> +			  RG_HTPLL_BC_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_BR),
> +			  RG_HTPLL_BR_MASK);
> +
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON1, 0, RG_HDMITX_PRED_IMP);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON1, (0x3 << RG_HDMITX_PRED_IBIAS),
> +			  RG_HDMITX_PRED_IBIAS_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0x0 << RG_HDMITX_EN_IMP),
> +			  RG_HDMITX_EN_IMP_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON1, (0x28 << RG_HDMITX_DRV_IMP),
> +			  RG_HDMITX_DRV_IMP_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON4, 0x28, RG_HDMITX_RESERVE_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xa << RG_HDMITX_DRV_IBIAS),
> +			  RG_HDMITX_DRV_IBIAS_MASK);
> +	return 0;
> +}
> +
> +static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> +				    unsigned long *parent_rate)
> +{
> +	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
> +
> +	hdmi_phy->pll_rate = rate;

In mtk_mt8173_hdmi_phy.c, mtk_hdmi_pll_round_rate adjust the
parent_rate, so mt2701 need not to adjust?

> +	return rate;
> +}
> +
> +static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
> +					      unsigned long parent_rate)
> +{
> +	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
> +
> +	return hdmi_phy->pll_rate;
> +}
> +
> +static const struct clk_ops mtk_hdmi_phy_pll_ops = {
> +	.enable = mtk_hdmi_pll_enable,
> +	.disable = mtk_hdmi_pll_disable,

Why mt2701 implement enable/disable, but mt8173 implement
prepare/unprepare? I would like these two use the same method. If these
two would be different, describe 'why' in commit message.

> +	.set_rate = mtk_hdmi_pll_set_rate,
> +	.round_rate = mtk_hdmi_pll_round_rate,
> +	.recalc_rate = mtk_hdmi_pll_recalc_rate,
> +};
> +
> +static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
> +{
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN,
> +			  RG_HTPLL_AUTOK_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_RLH_EN);

In mtk_mt8173_hdmi_phy.c, it define mtk_hdmi_phy_set_bits() and
mtk_hdmi_phy_clear_bits(). I think we could reuse it to reduce the code
size.

> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x3 << RG_HTPLL_POSDIV),
> +			  RG_HTPLL_POSDIV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS,
> +			  RG_HDMITX_EN_MBIAS);
> +	usleep_range(80, 100);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, RG_HTPLL_EN, RG_HTPLL_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO,
> +			  RG_HDMITX_EN_TX_CKLDO);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_SLDO),
> +			  RG_HDMITX_EN_SLDO_MASK);
> +	usleep_range(80, 100);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN,
> +			  RG_HDMITX_MBIAS_LPF_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV,
> +			  RG_HDMITX_EN_TX_POSDIV);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_SER),
> +			  RG_HDMITX_EN_SER_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_PRED),
> +			  RG_HDMITX_EN_PRED_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_DRV),
> +			  RG_HDMITX_EN_DRV_MASK);
> +	usleep_range(80, 100);
> +}
> +
> +static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
> +{
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_DRV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_PRED_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_SER_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_TX_POSDIV);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_MBIAS_LPF_EN);
> +	usleep_range(80, 100);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_SLDO_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_TX_CKLDO);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_EN);
> +	usleep_range(80, 100);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_MBIAS);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_POSDIV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_RLH_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, 0, RG_HTPLL_AUTOK_EN);
> +	usleep_range(80, 100);
> +}
> +
> +static int mtk_hdmi_phy_power_on(struct phy *phy)
> +{
> +	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
> +	int ret;
> +
> +	ret = clk_prepare_enable(hdmi_phy->pll);
> +	if (ret < 0)
> +		return ret;
> +
> +	mtk_hdmi_phy_enable_tmds(hdmi_phy);
> +
> +	return 0;
> +}
> +
> +static int mtk_hdmi_phy_power_off(struct phy *phy)
> +{
> +	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
> +
> +	mtk_hdmi_phy_disable_tmds(hdmi_phy);
> +	clk_disable_unprepare(hdmi_phy->pll);
> +
> +	return 0;
> +}
> +
> +static const struct phy_ops mtk_hdmi_phy_dev_ops = {
> +	.power_on = mtk_hdmi_phy_power_on,
> +	.power_off = mtk_hdmi_phy_power_off,
> +	.owner = THIS_MODULE,
> +};


mtk_hdmi_phy_power_on(), mtk_hdmi_phy_power_off(), mtk_hdmi_phy_dev_ops
is the same as those in mtk_mt8173_hdmi_phy.c, so I think you should
merge them to prevent duplicate code.

Regards,
CK

> +
> +struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf = {
> +	.tz_enabled = false,
> +	.hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
> +	.hdmi_phy_dev_ops = &mtk_hdmi_phy_dev_ops,
> +};
> +
> +MODULE_AUTHOR("Chunhui Dai <chunhui.dai@mediatek.com>");
> +MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
> +MODULE_LICENSE("GPL v2");

Re: [PATCH v2 10/13] drm/mediatek: add hdmi driver for MT2701 and MT7623

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> This patch adds hdmi dirver suppot for both MT2701 and MT7623.
> And also support other (existing or future) chips that use
> the same binding and driver.
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/Makefile              |   1 +
>  drivers/gpu/drm/mediatek/mtk_hdmi.h            |   1 +
>  drivers/gpu/drm/mediatek/mtk_hdmi_phy.c        |   3 +
>  drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 307 +++++++++++++++++++++++++
>  4 files changed, 312 insertions(+)
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> 
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 7f947979d68f..bf0067b5ee6f 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -2,6 +2,7 @@
>  mediatek-drm-hdmi-objs := mtk_cec.o \
>  			  mtk_hdmi.o \
>  			  mtk_hdmi_ddc.o \
> +                          mtk_mt2701_hdmi_phy.o \
>  			  mtk_mt8173_hdmi_phy.o \
>  			  mtk_hdmi_phy.o
>  
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.h b/drivers/gpu/drm/mediatek/mtk_hdmi.h
> index a350a6c9271f..fa12eb6288f3 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.h
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.h
> @@ -45,5 +45,6 @@ extern struct platform_driver mtk_cec_driver;
>  extern struct platform_driver mtk_hdmi_ddc_driver;
>  extern struct platform_driver mtk_hdmi_phy_driver;
>  extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
> +extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf;
>  
>  #endif /* _MTK_HDMI_CTRL_H */
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> index 82ed73575e04..606fc7a0c13b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> @@ -135,6 +135,9 @@ static int mtk_hdmi_phy_remove(struct platform_device *pdev)
>  }
>  
>  static const struct of_device_id mtk_hdmi_phy_match[] = {
> +	{ .compatible = "mediatek,mt2701-hdmi-phy",
> +	  .data = &mtk_hdmi_phy_2701_conf,
> +	},
>  	{ .compatible = "mediatek,mt8173-hdmi-phy",
>  	  .data = &mtk_hdmi_phy_8173_conf,
>  	},
> diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> new file mode 100644
> index 000000000000..428ef1557a14
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> @@ -0,0 +1,307 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Chunhui Dai <chunhui.dai@mediatek.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/debugfs.h>

Why need debugfs.h?

> +#include <linux/delay.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/phy/phy.h>
> +#include <linux/slab.h>
> +#include "mtk_hdmi.h"

I don't know why the included file is different in mtk_mt8173_hdmi_phy.c
with this file. The difference of these two files are hardware control,
so I think these two files would include the same header files. If these
two file include the same files, maybe we should move the common include
statement in some header file to prevent duplicate in these two files.

> +
> +#define HDMI_CON0	0x00
> +#define RG_HDMITX_DRV_IBIAS		(0)

You need not to embrace a single number.

> +#define RG_HDMITX_DRV_IBIAS_MASK	(0x3F << 0)

Use lower case for hex number.

> +#define RG_HDMITX_EN_SER		(12)
> +#define RG_HDMITX_EN_SER_MASK		(0x0F << 12)
> +#define RG_HDMITX_EN_SLDO		(16)
> +#define RG_HDMITX_EN_SLDO_MASK		(0x0F << 16)
> +#define RG_HDMITX_EN_PRED		(20)
> +#define RG_HDMITX_EN_PRED_MASK		(0x0F << 20)
> +#define RG_HDMITX_EN_IMP		(24)
> +#define RG_HDMITX_EN_IMP_MASK		(0x0F << 24)
> +#define RG_HDMITX_EN_DRV		(28)
> +#define RG_HDMITX_EN_DRV_MASK		(0x0F << 28)
> +
> +#define HDMI_CON1	0x04
> +#define RG_HDMITX_PRED_IBIAS		(18)
> +#define RG_HDMITX_PRED_IBIAS_MASK	(0x0F << 18)
> +#define RG_HDMITX_PRED_IMP		(0x01 << 22)
> +#define RG_HDMITX_DRV_IMP		(26)
> +#define RG_HDMITX_DRV_IMP_MASK		(0x3F << 26)
> +
> +#define HDMI_CON2	0x08
> +#define RG_HDMITX_EN_TX_CKLDO		(0x01 << 0)
> +#define RG_HDMITX_EN_TX_POSDIV		(0x01 << 1)
> +#define RG_HDMITX_TX_POSDIV		(3)
> +#define RG_HDMITX_TX_POSDIV_MASK	(0x03 << 3)
> +#define RG_HDMITX_EN_MBIAS		(0x01 << 6)
> +#define RG_HDMITX_MBIAS_LPF_EN		(0x01 << 7)
> +
> +#define HDMI_CON4	0x10
> +#define RG_HDMITX_RESERVE_MASK		(0xFFFFFFFF << 0)
> +
> +#define HDMI_CON6	0x18
> +#define RG_HTPLL_BR			(0)
> +#define RG_HTPLL_BR_MASK		(0x03 << 0)
> +#define RG_HTPLL_BC			(2)
> +#define RG_HTPLL_BC_MASK		(0x03 << 2)
> +#define RG_HTPLL_BP			(4)
> +#define RG_HTPLL_BP_MASK		(0x0F << 4)
> +#define RG_HTPLL_IR			(8)
> +#define RG_HTPLL_IR_MASK		(0x0F << 8)
> +#define RG_HTPLL_IC			(12)
> +#define RG_HTPLL_IC_MASK		(0x0F << 12)
> +#define RG_HTPLL_POSDIV			(16)
> +#define RG_HTPLL_POSDIV_MASK		(0x03 << 16)
> +#define RG_HTPLL_PREDIV			(18)
> +#define RG_HTPLL_PREDIV_MASK		(0x03 << 18)
> +#define RG_HTPLL_FBKSEL			(20)
> +#define RG_HTPLL_FBKSEL_MASK		(0x03 << 20)
> +#define RG_HTPLL_RLH_EN			(0x01 << 22)
> +#define RG_HTPLL_FBKDIV			(24)
> +#define RG_HTPLL_FBKDIV_MASK		(0x7F << 24)
> +#define RG_HTPLL_EN			(0x01 << 31)
> +
> +#define HDMI_CON7	0x1c
> +#define RG_HTPLL_AUTOK_EN		(0x01 << 23)
> +#define RG_HTPLL_DIVEN			(28)
> +#define RG_HTPLL_DIVEN_MASK		(0x07 << 28)
> +
> +static inline struct mtk_hdmi_phy *to_mtk_hdmi_pll(struct clk_hw *hw)
> +{
> +	return container_of(hw, struct mtk_hdmi_phy, pll_hw);
> +}

to_mtk_hdmi_pll() is the same as to_mtk_hdmi_phy() in
mtk_mt8173_hdmi_phy.c, I would like the merge these two functions. Maybe
you could these common function to a .h or .c file.

> +
> +static inline void mtk_hdmi_pll_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
> +				     u32 val, u32 mask)
> +{
> +	u32 tmp = readl(hdmi_phy->regs  + offset) & ~mask;
> +
> +	tmp |= (val & mask);
> +	writel(tmp, hdmi_phy->regs + offset);
> +}

Ditto.

> +
> +static int mtk_hdmi_pll_enable(struct clk_hw *hw)
> +{
> +	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
> +
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN,
> +			  RG_HTPLL_AUTOK_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_RLH_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x3 << RG_HTPLL_POSDIV),
> +			  RG_HTPLL_POSDIV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS,
> +			  RG_HDMITX_EN_MBIAS);
> +	usleep_range(80, 100);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, RG_HTPLL_EN, RG_HTPLL_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO,
> +			  RG_HDMITX_EN_TX_CKLDO);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_SLDO),
> +			  RG_HDMITX_EN_SLDO_MASK);
> +	usleep_range(80, 100);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN,
> +			  RG_HDMITX_MBIAS_LPF_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV,
> +			  RG_HDMITX_EN_TX_POSDIV);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_SER),
> +			  RG_HDMITX_EN_SER_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_PRED),
> +			  RG_HDMITX_EN_PRED_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_DRV),
> +			  RG_HDMITX_EN_DRV_MASK);
> +	usleep_range(80, 100);
> +	return 0;
> +}
> +
> +static void mtk_hdmi_pll_disable(struct clk_hw *hw)
> +{
> +	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
> +
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_DRV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_PRED_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_SER_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_TX_POSDIV);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_MBIAS_LPF_EN);
> +	usleep_range(80, 100);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_SLDO_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_TX_CKLDO);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_EN);
> +	usleep_range(80, 100);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_MBIAS);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_POSDIV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_RLH_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, 0, RG_HTPLL_AUTOK_EN);
> +	usleep_range(80, 100);
> +}
> +
> +static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> +				 unsigned long parent_rate)
> +{
> +	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
> +	u32 pos_div;
> +
> +	if (rate <= 64000000)
> +		pos_div = 3;
> +	else if (rate <= 12800000)
> +		pos_div = 1;
> +	else
> +		pos_div = 1;
> +
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x3 << RG_HTPLL_PREDIV),
> +			  RG_HTPLL_PREDIV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x3 << RG_HTPLL_POSDIV),
> +			  RG_HTPLL_POSDIV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IC),
> +			  RG_HTPLL_IC_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IR),
> +			  RG_HTPLL_IR_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, (pos_div << RG_HDMITX_TX_POSDIV),
> +			  RG_HDMITX_TX_POSDIV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (1 << RG_HTPLL_FBKSEL),
> +			  RG_HTPLL_FBKSEL_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (19 << RG_HTPLL_FBKDIV),
> +			  RG_HTPLL_FBKDIV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, (0x2 << RG_HTPLL_DIVEN),
> +			  RG_HTPLL_DIVEN_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0xc << RG_HTPLL_BP),
> +			  RG_HTPLL_BP_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x2 << RG_HTPLL_BC),
> +			  RG_HTPLL_BC_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_BR),
> +			  RG_HTPLL_BR_MASK);
> +
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON1, 0, RG_HDMITX_PRED_IMP);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON1, (0x3 << RG_HDMITX_PRED_IBIAS),
> +			  RG_HDMITX_PRED_IBIAS_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0x0 << RG_HDMITX_EN_IMP),
> +			  RG_HDMITX_EN_IMP_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON1, (0x28 << RG_HDMITX_DRV_IMP),
> +			  RG_HDMITX_DRV_IMP_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON4, 0x28, RG_HDMITX_RESERVE_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xa << RG_HDMITX_DRV_IBIAS),
> +			  RG_HDMITX_DRV_IBIAS_MASK);
> +	return 0;
> +}
> +
> +static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> +				    unsigned long *parent_rate)
> +{
> +	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
> +
> +	hdmi_phy->pll_rate = rate;

In mtk_mt8173_hdmi_phy.c, mtk_hdmi_pll_round_rate adjust the
parent_rate, so mt2701 need not to adjust?

> +	return rate;
> +}
> +
> +static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
> +					      unsigned long parent_rate)
> +{
> +	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
> +
> +	return hdmi_phy->pll_rate;
> +}
> +
> +static const struct clk_ops mtk_hdmi_phy_pll_ops = {
> +	.enable = mtk_hdmi_pll_enable,
> +	.disable = mtk_hdmi_pll_disable,

Why mt2701 implement enable/disable, but mt8173 implement
prepare/unprepare? I would like these two use the same method. If these
two would be different, describe 'why' in commit message.

> +	.set_rate = mtk_hdmi_pll_set_rate,
> +	.round_rate = mtk_hdmi_pll_round_rate,
> +	.recalc_rate = mtk_hdmi_pll_recalc_rate,
> +};
> +
> +static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
> +{
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN,
> +			  RG_HTPLL_AUTOK_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_RLH_EN);

In mtk_mt8173_hdmi_phy.c, it define mtk_hdmi_phy_set_bits() and
mtk_hdmi_phy_clear_bits(). I think we could reuse it to reduce the code
size.

> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x3 << RG_HTPLL_POSDIV),
> +			  RG_HTPLL_POSDIV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS,
> +			  RG_HDMITX_EN_MBIAS);
> +	usleep_range(80, 100);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, RG_HTPLL_EN, RG_HTPLL_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO,
> +			  RG_HDMITX_EN_TX_CKLDO);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_SLDO),
> +			  RG_HDMITX_EN_SLDO_MASK);
> +	usleep_range(80, 100);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN,
> +			  RG_HDMITX_MBIAS_LPF_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV,
> +			  RG_HDMITX_EN_TX_POSDIV);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_SER),
> +			  RG_HDMITX_EN_SER_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_PRED),
> +			  RG_HDMITX_EN_PRED_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_DRV),
> +			  RG_HDMITX_EN_DRV_MASK);
> +	usleep_range(80, 100);
> +}
> +
> +static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
> +{
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_DRV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_PRED_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_SER_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_TX_POSDIV);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_MBIAS_LPF_EN);
> +	usleep_range(80, 100);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_SLDO_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_TX_CKLDO);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_EN);
> +	usleep_range(80, 100);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_MBIAS);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_POSDIV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_RLH_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, 0, RG_HTPLL_AUTOK_EN);
> +	usleep_range(80, 100);
> +}
> +
> +static int mtk_hdmi_phy_power_on(struct phy *phy)
> +{
> +	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
> +	int ret;
> +
> +	ret = clk_prepare_enable(hdmi_phy->pll);
> +	if (ret < 0)
> +		return ret;
> +
> +	mtk_hdmi_phy_enable_tmds(hdmi_phy);
> +
> +	return 0;
> +}
> +
> +static int mtk_hdmi_phy_power_off(struct phy *phy)
> +{
> +	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
> +
> +	mtk_hdmi_phy_disable_tmds(hdmi_phy);
> +	clk_disable_unprepare(hdmi_phy->pll);
> +
> +	return 0;
> +}
> +
> +static const struct phy_ops mtk_hdmi_phy_dev_ops = {
> +	.power_on = mtk_hdmi_phy_power_on,
> +	.power_off = mtk_hdmi_phy_power_off,
> +	.owner = THIS_MODULE,
> +};


mtk_hdmi_phy_power_on(), mtk_hdmi_phy_power_off(), mtk_hdmi_phy_dev_ops
is the same as those in mtk_mt8173_hdmi_phy.c, so I think you should
merge them to prevent duplicate code.

Regards,
CK

> +
> +struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf = {
> +	.tz_enabled = false,
> +	.hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
> +	.hdmi_phy_dev_ops = &mtk_hdmi_phy_dev_ops,
> +};
> +
> +MODULE_AUTHOR("Chunhui Dai <chunhui.dai@mediatek.com>");
> +MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
> +MODULE_LICENSE("GPL v2");


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[PATCH v2 10/13] drm/mediatek: add hdmi driver for MT2701 and MT7623

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> This patch adds hdmi dirver suppot for both MT2701 and MT7623.
> And also support other (existing or future) chips that use
> the same binding and driver.
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/Makefile              |   1 +
>  drivers/gpu/drm/mediatek/mtk_hdmi.h            |   1 +
>  drivers/gpu/drm/mediatek/mtk_hdmi_phy.c        |   3 +
>  drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 307 +++++++++++++++++++++++++
>  4 files changed, 312 insertions(+)
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> 
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 7f947979d68f..bf0067b5ee6f 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -2,6 +2,7 @@
>  mediatek-drm-hdmi-objs := mtk_cec.o \
>  			  mtk_hdmi.o \
>  			  mtk_hdmi_ddc.o \
> +                          mtk_mt2701_hdmi_phy.o \
>  			  mtk_mt8173_hdmi_phy.o \
>  			  mtk_hdmi_phy.o
>  
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.h b/drivers/gpu/drm/mediatek/mtk_hdmi.h
> index a350a6c9271f..fa12eb6288f3 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.h
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.h
> @@ -45,5 +45,6 @@ extern struct platform_driver mtk_cec_driver;
>  extern struct platform_driver mtk_hdmi_ddc_driver;
>  extern struct platform_driver mtk_hdmi_phy_driver;
>  extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
> +extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf;
>  
>  #endif /* _MTK_HDMI_CTRL_H */
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> index 82ed73575e04..606fc7a0c13b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> @@ -135,6 +135,9 @@ static int mtk_hdmi_phy_remove(struct platform_device *pdev)
>  }
>  
>  static const struct of_device_id mtk_hdmi_phy_match[] = {
> +	{ .compatible = "mediatek,mt2701-hdmi-phy",
> +	  .data = &mtk_hdmi_phy_2701_conf,
> +	},
>  	{ .compatible = "mediatek,mt8173-hdmi-phy",
>  	  .data = &mtk_hdmi_phy_8173_conf,
>  	},
> diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> new file mode 100644
> index 000000000000..428ef1557a14
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> @@ -0,0 +1,307 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Chunhui Dai <chunhui.dai@mediatek.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/debugfs.h>

Why need debugfs.h?

> +#include <linux/delay.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/phy/phy.h>
> +#include <linux/slab.h>
> +#include "mtk_hdmi.h"

I don't know why the included file is different in mtk_mt8173_hdmi_phy.c
with this file. The difference of these two files are hardware control,
so I think these two files would include the same header files. If these
two file include the same files, maybe we should move the common include
statement in some header file to prevent duplicate in these two files.

> +
> +#define HDMI_CON0	0x00
> +#define RG_HDMITX_DRV_IBIAS		(0)

You need not to embrace a single number.

> +#define RG_HDMITX_DRV_IBIAS_MASK	(0x3F << 0)

Use lower case for hex number.

> +#define RG_HDMITX_EN_SER		(12)
> +#define RG_HDMITX_EN_SER_MASK		(0x0F << 12)
> +#define RG_HDMITX_EN_SLDO		(16)
> +#define RG_HDMITX_EN_SLDO_MASK		(0x0F << 16)
> +#define RG_HDMITX_EN_PRED		(20)
> +#define RG_HDMITX_EN_PRED_MASK		(0x0F << 20)
> +#define RG_HDMITX_EN_IMP		(24)
> +#define RG_HDMITX_EN_IMP_MASK		(0x0F << 24)
> +#define RG_HDMITX_EN_DRV		(28)
> +#define RG_HDMITX_EN_DRV_MASK		(0x0F << 28)
> +
> +#define HDMI_CON1	0x04
> +#define RG_HDMITX_PRED_IBIAS		(18)
> +#define RG_HDMITX_PRED_IBIAS_MASK	(0x0F << 18)
> +#define RG_HDMITX_PRED_IMP		(0x01 << 22)
> +#define RG_HDMITX_DRV_IMP		(26)
> +#define RG_HDMITX_DRV_IMP_MASK		(0x3F << 26)
> +
> +#define HDMI_CON2	0x08
> +#define RG_HDMITX_EN_TX_CKLDO		(0x01 << 0)
> +#define RG_HDMITX_EN_TX_POSDIV		(0x01 << 1)
> +#define RG_HDMITX_TX_POSDIV		(3)
> +#define RG_HDMITX_TX_POSDIV_MASK	(0x03 << 3)
> +#define RG_HDMITX_EN_MBIAS		(0x01 << 6)
> +#define RG_HDMITX_MBIAS_LPF_EN		(0x01 << 7)
> +
> +#define HDMI_CON4	0x10
> +#define RG_HDMITX_RESERVE_MASK		(0xFFFFFFFF << 0)
> +
> +#define HDMI_CON6	0x18
> +#define RG_HTPLL_BR			(0)
> +#define RG_HTPLL_BR_MASK		(0x03 << 0)
> +#define RG_HTPLL_BC			(2)
> +#define RG_HTPLL_BC_MASK		(0x03 << 2)
> +#define RG_HTPLL_BP			(4)
> +#define RG_HTPLL_BP_MASK		(0x0F << 4)
> +#define RG_HTPLL_IR			(8)
> +#define RG_HTPLL_IR_MASK		(0x0F << 8)
> +#define RG_HTPLL_IC			(12)
> +#define RG_HTPLL_IC_MASK		(0x0F << 12)
> +#define RG_HTPLL_POSDIV			(16)
> +#define RG_HTPLL_POSDIV_MASK		(0x03 << 16)
> +#define RG_HTPLL_PREDIV			(18)
> +#define RG_HTPLL_PREDIV_MASK		(0x03 << 18)
> +#define RG_HTPLL_FBKSEL			(20)
> +#define RG_HTPLL_FBKSEL_MASK		(0x03 << 20)
> +#define RG_HTPLL_RLH_EN			(0x01 << 22)
> +#define RG_HTPLL_FBKDIV			(24)
> +#define RG_HTPLL_FBKDIV_MASK		(0x7F << 24)
> +#define RG_HTPLL_EN			(0x01 << 31)
> +
> +#define HDMI_CON7	0x1c
> +#define RG_HTPLL_AUTOK_EN		(0x01 << 23)
> +#define RG_HTPLL_DIVEN			(28)
> +#define RG_HTPLL_DIVEN_MASK		(0x07 << 28)
> +
> +static inline struct mtk_hdmi_phy *to_mtk_hdmi_pll(struct clk_hw *hw)
> +{
> +	return container_of(hw, struct mtk_hdmi_phy, pll_hw);
> +}

to_mtk_hdmi_pll() is the same as to_mtk_hdmi_phy() in
mtk_mt8173_hdmi_phy.c, I would like the merge these two functions. Maybe
you could these common function to a .h or .c file.

> +
> +static inline void mtk_hdmi_pll_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
> +				     u32 val, u32 mask)
> +{
> +	u32 tmp = readl(hdmi_phy->regs  + offset) & ~mask;
> +
> +	tmp |= (val & mask);
> +	writel(tmp, hdmi_phy->regs + offset);
> +}

Ditto.

> +
> +static int mtk_hdmi_pll_enable(struct clk_hw *hw)
> +{
> +	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
> +
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN,
> +			  RG_HTPLL_AUTOK_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_RLH_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x3 << RG_HTPLL_POSDIV),
> +			  RG_HTPLL_POSDIV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS,
> +			  RG_HDMITX_EN_MBIAS);
> +	usleep_range(80, 100);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, RG_HTPLL_EN, RG_HTPLL_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO,
> +			  RG_HDMITX_EN_TX_CKLDO);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_SLDO),
> +			  RG_HDMITX_EN_SLDO_MASK);
> +	usleep_range(80, 100);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN,
> +			  RG_HDMITX_MBIAS_LPF_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV,
> +			  RG_HDMITX_EN_TX_POSDIV);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_SER),
> +			  RG_HDMITX_EN_SER_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_PRED),
> +			  RG_HDMITX_EN_PRED_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_DRV),
> +			  RG_HDMITX_EN_DRV_MASK);
> +	usleep_range(80, 100);
> +	return 0;
> +}
> +
> +static void mtk_hdmi_pll_disable(struct clk_hw *hw)
> +{
> +	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
> +
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_DRV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_PRED_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_SER_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_TX_POSDIV);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_MBIAS_LPF_EN);
> +	usleep_range(80, 100);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_SLDO_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_TX_CKLDO);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_EN);
> +	usleep_range(80, 100);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_MBIAS);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_POSDIV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_RLH_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, 0, RG_HTPLL_AUTOK_EN);
> +	usleep_range(80, 100);
> +}
> +
> +static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> +				 unsigned long parent_rate)
> +{
> +	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
> +	u32 pos_div;
> +
> +	if (rate <= 64000000)
> +		pos_div = 3;
> +	else if (rate <= 12800000)
> +		pos_div = 1;
> +	else
> +		pos_div = 1;
> +
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x3 << RG_HTPLL_PREDIV),
> +			  RG_HTPLL_PREDIV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x3 << RG_HTPLL_POSDIV),
> +			  RG_HTPLL_POSDIV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IC),
> +			  RG_HTPLL_IC_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IR),
> +			  RG_HTPLL_IR_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, (pos_div << RG_HDMITX_TX_POSDIV),
> +			  RG_HDMITX_TX_POSDIV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (1 << RG_HTPLL_FBKSEL),
> +			  RG_HTPLL_FBKSEL_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (19 << RG_HTPLL_FBKDIV),
> +			  RG_HTPLL_FBKDIV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, (0x2 << RG_HTPLL_DIVEN),
> +			  RG_HTPLL_DIVEN_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0xc << RG_HTPLL_BP),
> +			  RG_HTPLL_BP_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x2 << RG_HTPLL_BC),
> +			  RG_HTPLL_BC_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_BR),
> +			  RG_HTPLL_BR_MASK);
> +
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON1, 0, RG_HDMITX_PRED_IMP);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON1, (0x3 << RG_HDMITX_PRED_IBIAS),
> +			  RG_HDMITX_PRED_IBIAS_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0x0 << RG_HDMITX_EN_IMP),
> +			  RG_HDMITX_EN_IMP_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON1, (0x28 << RG_HDMITX_DRV_IMP),
> +			  RG_HDMITX_DRV_IMP_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON4, 0x28, RG_HDMITX_RESERVE_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xa << RG_HDMITX_DRV_IBIAS),
> +			  RG_HDMITX_DRV_IBIAS_MASK);
> +	return 0;
> +}
> +
> +static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> +				    unsigned long *parent_rate)
> +{
> +	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
> +
> +	hdmi_phy->pll_rate = rate;

In mtk_mt8173_hdmi_phy.c, mtk_hdmi_pll_round_rate adjust the
parent_rate, so mt2701 need not to adjust?

> +	return rate;
> +}
> +
> +static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
> +					      unsigned long parent_rate)
> +{
> +	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_pll(hw);
> +
> +	return hdmi_phy->pll_rate;
> +}
> +
> +static const struct clk_ops mtk_hdmi_phy_pll_ops = {
> +	.enable = mtk_hdmi_pll_enable,
> +	.disable = mtk_hdmi_pll_disable,

Why mt2701 implement enable/disable, but mt8173 implement
prepare/unprepare? I would like these two use the same method. If these
two would be different, describe 'why' in commit message.

> +	.set_rate = mtk_hdmi_pll_set_rate,
> +	.round_rate = mtk_hdmi_pll_round_rate,
> +	.recalc_rate = mtk_hdmi_pll_recalc_rate,
> +};
> +
> +static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
> +{
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN,
> +			  RG_HTPLL_AUTOK_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_RLH_EN);

In mtk_mt8173_hdmi_phy.c, it define mtk_hdmi_phy_set_bits() and
mtk_hdmi_phy_clear_bits(). I think we could reuse it to reduce the code
size.

> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, (0x3 << RG_HTPLL_POSDIV),
> +			  RG_HTPLL_POSDIV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS,
> +			  RG_HDMITX_EN_MBIAS);
> +	usleep_range(80, 100);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, RG_HTPLL_EN, RG_HTPLL_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO,
> +			  RG_HDMITX_EN_TX_CKLDO);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_SLDO),
> +			  RG_HDMITX_EN_SLDO_MASK);
> +	usleep_range(80, 100);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN,
> +			  RG_HDMITX_MBIAS_LPF_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV,
> +			  RG_HDMITX_EN_TX_POSDIV);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_SER),
> +			  RG_HDMITX_EN_SER_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_PRED),
> +			  RG_HDMITX_EN_PRED_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, (0xf << RG_HDMITX_EN_DRV),
> +			  RG_HDMITX_EN_DRV_MASK);
> +	usleep_range(80, 100);
> +}
> +
> +static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
> +{
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_DRV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_PRED_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_SER_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_TX_POSDIV);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_MBIAS_LPF_EN);
> +	usleep_range(80, 100);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON0, 0, RG_HDMITX_EN_SLDO_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_TX_CKLDO);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_EN);
> +	usleep_range(80, 100);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON2, 0, RG_HDMITX_EN_MBIAS);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_POSDIV_MASK);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON6, 0, RG_HTPLL_RLH_EN);
> +	mtk_hdmi_pll_mask(hdmi_phy, HDMI_CON7, 0, RG_HTPLL_AUTOK_EN);
> +	usleep_range(80, 100);
> +}
> +
> +static int mtk_hdmi_phy_power_on(struct phy *phy)
> +{
> +	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
> +	int ret;
> +
> +	ret = clk_prepare_enable(hdmi_phy->pll);
> +	if (ret < 0)
> +		return ret;
> +
> +	mtk_hdmi_phy_enable_tmds(hdmi_phy);
> +
> +	return 0;
> +}
> +
> +static int mtk_hdmi_phy_power_off(struct phy *phy)
> +{
> +	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
> +
> +	mtk_hdmi_phy_disable_tmds(hdmi_phy);
> +	clk_disable_unprepare(hdmi_phy->pll);
> +
> +	return 0;
> +}
> +
> +static const struct phy_ops mtk_hdmi_phy_dev_ops = {
> +	.power_on = mtk_hdmi_phy_power_on,
> +	.power_off = mtk_hdmi_phy_power_off,
> +	.owner = THIS_MODULE,
> +};


mtk_hdmi_phy_power_on(), mtk_hdmi_phy_power_off(), mtk_hdmi_phy_dev_ops
is the same as those in mtk_mt8173_hdmi_phy.c, so I think you should
merge them to prevent duplicate code.

Regards,
CK

> +
> +struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf = {
> +	.tz_enabled = false,
> +	.hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
> +	.hdmi_phy_dev_ops = &mtk_hdmi_phy_dev_ops,
> +};
> +
> +MODULE_AUTHOR("Chunhui Dai <chunhui.dai@mediatek.com>");
> +MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
> +MODULE_LICENSE("GPL v2");

Re: [PATCH v2 07/13] drm/mediatek: separae hdmi phy to different file

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> Different IC has different phy setting of HDMI.
> This patch separaes the phy hardware relate part for mt8173.
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/Makefile              |  15 +--
>  drivers/gpu/drm/mediatek/mtk_hdmi.c            |  30 +++--
>  drivers/gpu/drm/mediatek/mtk_hdmi.h            |  26 +++++
>  drivers/gpu/drm/mediatek/mtk_hdmi_phy.c        | 154 +++++++++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 129 ++-------------------
>  5 files changed, 216 insertions(+), 138 deletions(-)
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> 
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index ce83c396a742..7f947979d68f 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -1,4 +1,12 @@
>  # SPDX-License-Identifier: GPL-2.0
> +mediatek-drm-hdmi-objs := mtk_cec.o \
> +			  mtk_hdmi.o \
> +			  mtk_hdmi_ddc.o \
> +			  mtk_mt8173_hdmi_phy.o \
> +			  mtk_hdmi_phy.o
> +
> +obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
> +

It looks like you just want to add mtk_hdmi_phy.o, I think you need not
to move mediatek-drm-hdmi-objs.

>  mediatek-drm-y := mtk_disp_color.o \
>  		  mtk_disp_ovl.o \
>  		  mtk_disp_rdma.o \
> @@ -14,10 +22,3 @@ mediatek-drm-y := mtk_disp_color.o \
>  		  mtk_dpi.o
>  
>  obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> -
> -mediatek-drm-hdmi-objs := mtk_cec.o \
> -			  mtk_hdmi.o \
> -			  mtk_hdmi_ddc.o \
> -			  mtk_mt8173_hdmi_phy.o
> -
> -obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index 2d45d1dd9554..7c022f3f53ec 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -233,6 +233,7 @@ static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
>  static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
>  {
>  	struct arm_smccc_res res;
> +	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(hdmi->phy);
>  
>  	/*
>  	 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI
> @@ -240,8 +241,13 @@ static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
>  	 * The ARM trusted firmware provides an API for the HDMI driver to set
>  	 * this control bit to enable HDMI output in supervisor mode.
>  	 */
> -	arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, 0x80000000,
> -		      0, 0, 0, 0, 0, &res);
> +	if (hdmi_phy->conf && hdmi_phy->conf->tz_enabled)
> +		arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904,
> +			      0x80000000, 0, 0, 0, 0, 0, &res);
> +	else
> +		regmap_update_bits(hdmi->sys_regmap,
> +				   hdmi->sys_offset + HDMI_SYS_CFG20,
> +				   0x80008005, enable ? 0x80000005 : 0x8000);

I think this should be moved to 'drm/mediatek: add hdmi driver for
MT2701 and MT7623'. If you change the variable name to tz_disabled, you
could modify this in just one patch.

>  
>  	regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
>  			   HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
> @@ -1437,6 +1443,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
>  	struct platform_device *cec_pdev;
>  	struct regmap *regmap;
>  	struct resource *mem;
> +	const char *phy_name;
>  	int ret;
>  
>  	ret = mtk_hdmi_get_all_clk(hdmi, np);
> @@ -1445,6 +1452,18 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
>  		return ret;
>  	}
>  
> +	ret = of_property_read_string(np, "phy-names", &phy_name);
> +	if (ret < 0) {
> +		dev_err(dev, "Failed to read phy-names: %d\n", ret);
> +		return ret;
> +	}
> +	hdmi->phy = devm_phy_get(dev, phy_name);
> +	if (IS_ERR(hdmi->phy)) {
> +		ret = PTR_ERR(hdmi->phy);
> +		dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
> +		return ret;
> +	}
> +

I think this part is not related to 'separate hdmi phy to different
file' and I don't know why you do this? If you really need this,
separate this to an independent patch and describe why you do this.

Regards,
CK

>  	/* The CEC module handles HDMI hotplug detection */
>  	cec_np = of_find_compatible_node(np->parent, NULL,
>  					 "mediatek,mt8173-cec");
> @@ -1677,13 +1696,6 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev)
>  	if (ret)
>  		return ret;
>  
> -	hdmi->phy = devm_phy_get(dev, "hdmi");
> -	if (IS_ERR(hdmi->phy)) {
> -		ret = PTR_ERR(hdmi->phy);
> -		dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
> -		return ret;
> -	}
> -
>  	platform_set_drvdata(pdev, hdmi);
>  
>  	ret = mtk_hdmi_output_init(hdmi);
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.h b/drivers/gpu/drm/mediatek/mtk_hdmi.h
> index 6371b3de1ff6..a350a6c9271f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.h
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.h
> @@ -13,11 +13,37 @@
>   */
>  #ifndef _MTK_HDMI_CTRL_H
>  #define _MTK_HDMI_CTRL_H
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +
> +struct mtk_hdmi_phy_conf {
> +	bool tz_enabled;
> +	const struct clk_ops *hdmi_phy_clk_ops;
> +	const struct phy_ops *hdmi_phy_dev_ops;
> +};
> +
> +struct mtk_hdmi_phy {
> +	void __iomem *regs;
> +	struct device *dev;
> +	struct mtk_hdmi_phy_conf *conf;
> +	struct clk *pll;
> +	struct clk_hw pll_hw;
> +	unsigned long pll_rate;
> +	unsigned char drv_imp_clk;
> +	unsigned char drv_imp_d2;
> +	unsigned char drv_imp_d1;
> +	unsigned char drv_imp_d0;
> +	unsigned int ibias;
> +	unsigned int ibias_up;
> +};
>  
>  struct platform_driver;
>  
>  extern struct platform_driver mtk_cec_driver;
>  extern struct platform_driver mtk_hdmi_ddc_driver;
>  extern struct platform_driver mtk_hdmi_phy_driver;
> +extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
>  
>  #endif /* _MTK_HDMI_CTRL_H */
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> new file mode 100644
> index 000000000000..82ed73575e04
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> @@ -0,0 +1,154 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Jie Qiu <jie.qiu@mediatek.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/of.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include "mtk_hdmi.h"
> +
> +static void mtk_hdmi_phy_clk_get_ops(struct mtk_hdmi_phy *hdmi_phy,
> +				     const struct clk_ops **ops)
> +{
> +	if (hdmi_phy && hdmi_phy->conf && hdmi_phy->conf->hdmi_phy_clk_ops)
> +		*ops = hdmi_phy->conf->hdmi_phy_clk_ops;
> +	else
> +		dev_err(hdmi_phy->dev, "Failed to get clk ops of phy\n");
> +}
> +
> +static const struct phy_ops *
> +mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy)
> +{
> +	if (hdmi_phy && hdmi_phy->conf && hdmi_phy->conf->hdmi_phy_dev_ops)
> +		return hdmi_phy->conf->hdmi_phy_dev_ops;
> +	dev_err(hdmi_phy->dev, "Failed to get dev ops of phy\n");
> +		return NULL;
> +}
> +
> +static int mtk_hdmi_phy_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct mtk_hdmi_phy *hdmi_phy;
> +	struct resource *mem;
> +	struct clk *ref_clk;
> +	const char *ref_clk_name;
> +	struct clk_init_data clk_init = {
> +		.num_parents = 1,
> +		.parent_names = (const char * const *)&ref_clk_name,
> +		.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
> +	};
> +
> +	struct phy *phy;
> +	struct phy_provider *phy_provider;
> +	int ret;
> +
> +	hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
> +	if (!hdmi_phy)
> +		return -ENOMEM;
> +
> +	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	hdmi_phy->regs = devm_ioremap_resource(dev, mem);
> +	if (IS_ERR(hdmi_phy->regs)) {
> +		ret = PTR_ERR(hdmi_phy->regs);
> +		dev_err(dev, "Failed to get memory resource: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ref_clk = devm_clk_get(dev, "pll_ref");
> +	if (IS_ERR(ref_clk)) {
> +		ret = PTR_ERR(ref_clk);
> +		dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
> +			ret);
> +		return ret;
> +	}
> +	ref_clk_name = __clk_get_name(ref_clk);
> +
> +	ret = of_property_read_string(dev->of_node, "clock-output-names",
> +				      &clk_init.name);
> +	if (ret < 0) {
> +		dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
> +		return ret;
> +	}
> +
> +	hdmi_phy->dev = dev;
> +	hdmi_phy->conf =
> +		(struct mtk_hdmi_phy_conf *)of_device_get_match_data(dev);
> +	mtk_hdmi_phy_clk_get_ops(hdmi_phy, &clk_init.ops);
> +	hdmi_phy->pll_hw.init = &clk_init;
> +	hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
> +	if (IS_ERR(hdmi_phy->pll)) {
> +		ret = PTR_ERR(hdmi_phy->pll);
> +		dev_err(dev, "Failed to register PLL: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
> +				   &hdmi_phy->ibias);
> +	if (ret < 0) {
> +		dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
> +				   &hdmi_phy->ibias_up);
> +	if (ret < 0) {
> +		dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
> +		return ret;
> +	}
> +
> +	dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
> +	hdmi_phy->drv_imp_clk = 0x30;
> +	hdmi_phy->drv_imp_d2 = 0x30;
> +	hdmi_phy->drv_imp_d1 = 0x30;
> +	hdmi_phy->drv_imp_d0 = 0x30;
> +
> +	phy = devm_phy_create(dev, NULL, mtk_hdmi_phy_dev_get_ops(hdmi_phy));
> +	if (IS_ERR(phy)) {
> +		dev_err(dev, "Failed to create HDMI PHY\n");
> +		return PTR_ERR(phy);
> +	}
> +	phy_set_drvdata(phy, hdmi_phy);
> +
> +	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +	if (IS_ERR(phy_provider)) {
> +		dev_err(dev, "Failed to register HDMI PHY\n");
> +		return PTR_ERR(phy_provider);
> +	}
> +
> +	return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
> +				   hdmi_phy->pll);
> +}
> +
> +static int mtk_hdmi_phy_remove(struct platform_device *pdev)
> +{
> +	return 0;
> +}
> +
> +static const struct of_device_id mtk_hdmi_phy_match[] = {
> +	{ .compatible = "mediatek,mt8173-hdmi-phy",
> +	  .data = &mtk_hdmi_phy_8173_conf,
> +	},
> +	{},
> +};
> +
> +struct platform_driver mtk_hdmi_phy_driver = {
> +	.probe = mtk_hdmi_phy_probe,
> +	.remove = mtk_hdmi_phy_remove,
> +	.driver = {
> +		.name = "mediatek-hdmi-phy",
> +		.of_match_table = mtk_hdmi_phy_match,
> +	},
> +};
> +
> +MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> index 51cb9cfb6646..1a35fdd405d8 100644
> --- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> +++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> @@ -21,6 +21,7 @@
>  #include <linux/phy/phy.h>
>  #include <linux/platform_device.h>
>  #include <linux/types.h>
> +#include "mtk_hdmi.h"
>  
>  #define HDMI_CON0		0x00
>  #define RG_HDMITX_PLL_EN		BIT(31)
> @@ -123,20 +124,6 @@
>  #define RGS_HDMITX_5T1_EDG		(0xf << 4)
>  #define RGS_HDMITX_PLUG_TST		BIT(0)
>  
> -struct mtk_hdmi_phy {
> -	void __iomem *regs;
> -	struct device *dev;
> -	struct clk *pll;
> -	struct clk_hw pll_hw;
> -	unsigned long pll_rate;
> -	u8 drv_imp_clk;
> -	u8 drv_imp_d2;
> -	u8 drv_imp_d1;
> -	u8 drv_imp_d0;
> -	u32 ibias;
> -	u32 ibias_up;
> -};
> -
>  static const u8 PREDIV[3][4] = {
>  	{0x0, 0x0, 0x0, 0x0},	/* 27Mhz */
>  	{0x1, 0x1, 0x1, 0x1},	/* 74Mhz */
> @@ -367,7 +354,7 @@ static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
>  	return hdmi_phy->pll_rate;
>  }
>  
> -static const struct clk_ops mtk_hdmi_pll_ops = {
> +static const struct clk_ops mtk_hdmi_phy_pll_ops = {
>  	.prepare = mtk_hdmi_pll_prepare,
>  	.unprepare = mtk_hdmi_pll_unprepare,
>  	.set_rate = mtk_hdmi_pll_set_rate,
> @@ -414,118 +401,16 @@ static int mtk_hdmi_phy_power_off(struct phy *phy)
>  	return 0;
>  }
>  
> -static const struct phy_ops mtk_hdmi_phy_ops = {
> +static const struct phy_ops mtk_hdmi_phy_dev_ops = {
>  	.power_on = mtk_hdmi_phy_power_on,
>  	.power_off = mtk_hdmi_phy_power_off,
>  	.owner = THIS_MODULE,
>  };
>  
> -static int mtk_hdmi_phy_probe(struct platform_device *pdev)
> -{
> -	struct device *dev = &pdev->dev;
> -	struct mtk_hdmi_phy *hdmi_phy;
> -	struct resource *mem;
> -	struct clk *ref_clk;
> -	const char *ref_clk_name;
> -	struct clk_init_data clk_init = {
> -		.ops = &mtk_hdmi_pll_ops,
> -		.num_parents = 1,
> -		.parent_names = (const char * const *)&ref_clk_name,
> -		.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
> -	};
> -	struct phy *phy;
> -	struct phy_provider *phy_provider;
> -	int ret;
> -
> -	hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
> -	if (!hdmi_phy)
> -		return -ENOMEM;
> -
> -	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	hdmi_phy->regs = devm_ioremap_resource(dev, mem);
> -	if (IS_ERR(hdmi_phy->regs)) {
> -		ret = PTR_ERR(hdmi_phy->regs);
> -		dev_err(dev, "Failed to get memory resource: %d\n", ret);
> -		return ret;
> -	}
> -
> -	ref_clk = devm_clk_get(dev, "pll_ref");
> -	if (IS_ERR(ref_clk)) {
> -		ret = PTR_ERR(ref_clk);
> -		dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
> -			ret);
> -		return ret;
> -	}
> -	ref_clk_name = __clk_get_name(ref_clk);
> -
> -	ret = of_property_read_string(dev->of_node, "clock-output-names",
> -				      &clk_init.name);
> -	if (ret < 0) {
> -		dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
> -		return ret;
> -	}
> -
> -	hdmi_phy->pll_hw.init = &clk_init;
> -	hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
> -	if (IS_ERR(hdmi_phy->pll)) {
> -		ret = PTR_ERR(hdmi_phy->pll);
> -		dev_err(dev, "Failed to register PLL: %d\n", ret);
> -		return ret;
> -	}
> -
> -	ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
> -				   &hdmi_phy->ibias);
> -	if (ret < 0) {
> -		dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
> -		return ret;
> -	}
> -
> -	ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
> -				   &hdmi_phy->ibias_up);
> -	if (ret < 0) {
> -		dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
> -		return ret;
> -	}
> -
> -	dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
> -	hdmi_phy->drv_imp_clk = 0x30;
> -	hdmi_phy->drv_imp_d2 = 0x30;
> -	hdmi_phy->drv_imp_d1 = 0x30;
> -	hdmi_phy->drv_imp_d0 = 0x30;
> -
> -	phy = devm_phy_create(dev, NULL, &mtk_hdmi_phy_ops);
> -	if (IS_ERR(phy)) {
> -		dev_err(dev, "Failed to create HDMI PHY\n");
> -		return PTR_ERR(phy);
> -	}
> -	phy_set_drvdata(phy, hdmi_phy);
> -
> -	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> -	if (IS_ERR(phy_provider))
> -		return PTR_ERR(phy_provider);
> -
> -	hdmi_phy->dev = dev;
> -	return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
> -				   hdmi_phy->pll);
> -}
> -
> -static int mtk_hdmi_phy_remove(struct platform_device *pdev)
> -{
> -	return 0;
> -}
> -
> -static const struct of_device_id mtk_hdmi_phy_match[] = {
> -	{ .compatible = "mediatek,mt8173-hdmi-phy", },
> -	{},
> -};
> -
> -struct platform_driver mtk_hdmi_phy_driver = {
> -	.probe = mtk_hdmi_phy_probe,
> -	.remove = mtk_hdmi_phy_remove,
> -	.driver = {
> -		.name = "mediatek-hdmi-phy",
> -		.of_match_table = mtk_hdmi_phy_match,
> -	},
> +struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = {
> +	.tz_enabled = true,
> +	.hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
> +	.hdmi_phy_dev_ops = &mtk_hdmi_phy_dev_ops,
>  };
>  
>  MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");

Re: [PATCH v2 07/13] drm/mediatek: separae hdmi phy to different file

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> Different IC has different phy setting of HDMI.
> This patch separaes the phy hardware relate part for mt8173.
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/Makefile              |  15 +--
>  drivers/gpu/drm/mediatek/mtk_hdmi.c            |  30 +++--
>  drivers/gpu/drm/mediatek/mtk_hdmi.h            |  26 +++++
>  drivers/gpu/drm/mediatek/mtk_hdmi_phy.c        | 154 +++++++++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 129 ++-------------------
>  5 files changed, 216 insertions(+), 138 deletions(-)
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> 
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index ce83c396a742..7f947979d68f 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -1,4 +1,12 @@
>  # SPDX-License-Identifier: GPL-2.0
> +mediatek-drm-hdmi-objs := mtk_cec.o \
> +			  mtk_hdmi.o \
> +			  mtk_hdmi_ddc.o \
> +			  mtk_mt8173_hdmi_phy.o \
> +			  mtk_hdmi_phy.o
> +
> +obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
> +

It looks like you just want to add mtk_hdmi_phy.o, I think you need not
to move mediatek-drm-hdmi-objs.

>  mediatek-drm-y := mtk_disp_color.o \
>  		  mtk_disp_ovl.o \
>  		  mtk_disp_rdma.o \
> @@ -14,10 +22,3 @@ mediatek-drm-y := mtk_disp_color.o \
>  		  mtk_dpi.o
>  
>  obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> -
> -mediatek-drm-hdmi-objs := mtk_cec.o \
> -			  mtk_hdmi.o \
> -			  mtk_hdmi_ddc.o \
> -			  mtk_mt8173_hdmi_phy.o
> -
> -obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index 2d45d1dd9554..7c022f3f53ec 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -233,6 +233,7 @@ static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
>  static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
>  {
>  	struct arm_smccc_res res;
> +	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(hdmi->phy);
>  
>  	/*
>  	 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI
> @@ -240,8 +241,13 @@ static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
>  	 * The ARM trusted firmware provides an API for the HDMI driver to set
>  	 * this control bit to enable HDMI output in supervisor mode.
>  	 */
> -	arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, 0x80000000,
> -		      0, 0, 0, 0, 0, &res);
> +	if (hdmi_phy->conf && hdmi_phy->conf->tz_enabled)
> +		arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904,
> +			      0x80000000, 0, 0, 0, 0, 0, &res);
> +	else
> +		regmap_update_bits(hdmi->sys_regmap,
> +				   hdmi->sys_offset + HDMI_SYS_CFG20,
> +				   0x80008005, enable ? 0x80000005 : 0x8000);

I think this should be moved to 'drm/mediatek: add hdmi driver for
MT2701 and MT7623'. If you change the variable name to tz_disabled, you
could modify this in just one patch.

>  
>  	regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
>  			   HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
> @@ -1437,6 +1443,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
>  	struct platform_device *cec_pdev;
>  	struct regmap *regmap;
>  	struct resource *mem;
> +	const char *phy_name;
>  	int ret;
>  
>  	ret = mtk_hdmi_get_all_clk(hdmi, np);
> @@ -1445,6 +1452,18 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
>  		return ret;
>  	}
>  
> +	ret = of_property_read_string(np, "phy-names", &phy_name);
> +	if (ret < 0) {
> +		dev_err(dev, "Failed to read phy-names: %d\n", ret);
> +		return ret;
> +	}
> +	hdmi->phy = devm_phy_get(dev, phy_name);
> +	if (IS_ERR(hdmi->phy)) {
> +		ret = PTR_ERR(hdmi->phy);
> +		dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
> +		return ret;
> +	}
> +

I think this part is not related to 'separate hdmi phy to different
file' and I don't know why you do this? If you really need this,
separate this to an independent patch and describe why you do this.

Regards,
CK

>  	/* The CEC module handles HDMI hotplug detection */
>  	cec_np = of_find_compatible_node(np->parent, NULL,
>  					 "mediatek,mt8173-cec");
> @@ -1677,13 +1696,6 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev)
>  	if (ret)
>  		return ret;
>  
> -	hdmi->phy = devm_phy_get(dev, "hdmi");
> -	if (IS_ERR(hdmi->phy)) {
> -		ret = PTR_ERR(hdmi->phy);
> -		dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
> -		return ret;
> -	}
> -
>  	platform_set_drvdata(pdev, hdmi);
>  
>  	ret = mtk_hdmi_output_init(hdmi);
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.h b/drivers/gpu/drm/mediatek/mtk_hdmi.h
> index 6371b3de1ff6..a350a6c9271f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.h
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.h
> @@ -13,11 +13,37 @@
>   */
>  #ifndef _MTK_HDMI_CTRL_H
>  #define _MTK_HDMI_CTRL_H
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +
> +struct mtk_hdmi_phy_conf {
> +	bool tz_enabled;
> +	const struct clk_ops *hdmi_phy_clk_ops;
> +	const struct phy_ops *hdmi_phy_dev_ops;
> +};
> +
> +struct mtk_hdmi_phy {
> +	void __iomem *regs;
> +	struct device *dev;
> +	struct mtk_hdmi_phy_conf *conf;
> +	struct clk *pll;
> +	struct clk_hw pll_hw;
> +	unsigned long pll_rate;
> +	unsigned char drv_imp_clk;
> +	unsigned char drv_imp_d2;
> +	unsigned char drv_imp_d1;
> +	unsigned char drv_imp_d0;
> +	unsigned int ibias;
> +	unsigned int ibias_up;
> +};
>  
>  struct platform_driver;
>  
>  extern struct platform_driver mtk_cec_driver;
>  extern struct platform_driver mtk_hdmi_ddc_driver;
>  extern struct platform_driver mtk_hdmi_phy_driver;
> +extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
>  
>  #endif /* _MTK_HDMI_CTRL_H */
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> new file mode 100644
> index 000000000000..82ed73575e04
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> @@ -0,0 +1,154 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Jie Qiu <jie.qiu@mediatek.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/of.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include "mtk_hdmi.h"
> +
> +static void mtk_hdmi_phy_clk_get_ops(struct mtk_hdmi_phy *hdmi_phy,
> +				     const struct clk_ops **ops)
> +{
> +	if (hdmi_phy && hdmi_phy->conf && hdmi_phy->conf->hdmi_phy_clk_ops)
> +		*ops = hdmi_phy->conf->hdmi_phy_clk_ops;
> +	else
> +		dev_err(hdmi_phy->dev, "Failed to get clk ops of phy\n");
> +}
> +
> +static const struct phy_ops *
> +mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy)
> +{
> +	if (hdmi_phy && hdmi_phy->conf && hdmi_phy->conf->hdmi_phy_dev_ops)
> +		return hdmi_phy->conf->hdmi_phy_dev_ops;
> +	dev_err(hdmi_phy->dev, "Failed to get dev ops of phy\n");
> +		return NULL;
> +}
> +
> +static int mtk_hdmi_phy_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct mtk_hdmi_phy *hdmi_phy;
> +	struct resource *mem;
> +	struct clk *ref_clk;
> +	const char *ref_clk_name;
> +	struct clk_init_data clk_init = {
> +		.num_parents = 1,
> +		.parent_names = (const char * const *)&ref_clk_name,
> +		.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
> +	};
> +
> +	struct phy *phy;
> +	struct phy_provider *phy_provider;
> +	int ret;
> +
> +	hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
> +	if (!hdmi_phy)
> +		return -ENOMEM;
> +
> +	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	hdmi_phy->regs = devm_ioremap_resource(dev, mem);
> +	if (IS_ERR(hdmi_phy->regs)) {
> +		ret = PTR_ERR(hdmi_phy->regs);
> +		dev_err(dev, "Failed to get memory resource: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ref_clk = devm_clk_get(dev, "pll_ref");
> +	if (IS_ERR(ref_clk)) {
> +		ret = PTR_ERR(ref_clk);
> +		dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
> +			ret);
> +		return ret;
> +	}
> +	ref_clk_name = __clk_get_name(ref_clk);
> +
> +	ret = of_property_read_string(dev->of_node, "clock-output-names",
> +				      &clk_init.name);
> +	if (ret < 0) {
> +		dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
> +		return ret;
> +	}
> +
> +	hdmi_phy->dev = dev;
> +	hdmi_phy->conf =
> +		(struct mtk_hdmi_phy_conf *)of_device_get_match_data(dev);
> +	mtk_hdmi_phy_clk_get_ops(hdmi_phy, &clk_init.ops);
> +	hdmi_phy->pll_hw.init = &clk_init;
> +	hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
> +	if (IS_ERR(hdmi_phy->pll)) {
> +		ret = PTR_ERR(hdmi_phy->pll);
> +		dev_err(dev, "Failed to register PLL: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
> +				   &hdmi_phy->ibias);
> +	if (ret < 0) {
> +		dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
> +				   &hdmi_phy->ibias_up);
> +	if (ret < 0) {
> +		dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
> +		return ret;
> +	}
> +
> +	dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
> +	hdmi_phy->drv_imp_clk = 0x30;
> +	hdmi_phy->drv_imp_d2 = 0x30;
> +	hdmi_phy->drv_imp_d1 = 0x30;
> +	hdmi_phy->drv_imp_d0 = 0x30;
> +
> +	phy = devm_phy_create(dev, NULL, mtk_hdmi_phy_dev_get_ops(hdmi_phy));
> +	if (IS_ERR(phy)) {
> +		dev_err(dev, "Failed to create HDMI PHY\n");
> +		return PTR_ERR(phy);
> +	}
> +	phy_set_drvdata(phy, hdmi_phy);
> +
> +	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +	if (IS_ERR(phy_provider)) {
> +		dev_err(dev, "Failed to register HDMI PHY\n");
> +		return PTR_ERR(phy_provider);
> +	}
> +
> +	return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
> +				   hdmi_phy->pll);
> +}
> +
> +static int mtk_hdmi_phy_remove(struct platform_device *pdev)
> +{
> +	return 0;
> +}
> +
> +static const struct of_device_id mtk_hdmi_phy_match[] = {
> +	{ .compatible = "mediatek,mt8173-hdmi-phy",
> +	  .data = &mtk_hdmi_phy_8173_conf,
> +	},
> +	{},
> +};
> +
> +struct platform_driver mtk_hdmi_phy_driver = {
> +	.probe = mtk_hdmi_phy_probe,
> +	.remove = mtk_hdmi_phy_remove,
> +	.driver = {
> +		.name = "mediatek-hdmi-phy",
> +		.of_match_table = mtk_hdmi_phy_match,
> +	},
> +};
> +
> +MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> index 51cb9cfb6646..1a35fdd405d8 100644
> --- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> +++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> @@ -21,6 +21,7 @@
>  #include <linux/phy/phy.h>
>  #include <linux/platform_device.h>
>  #include <linux/types.h>
> +#include "mtk_hdmi.h"
>  
>  #define HDMI_CON0		0x00
>  #define RG_HDMITX_PLL_EN		BIT(31)
> @@ -123,20 +124,6 @@
>  #define RGS_HDMITX_5T1_EDG		(0xf << 4)
>  #define RGS_HDMITX_PLUG_TST		BIT(0)
>  
> -struct mtk_hdmi_phy {
> -	void __iomem *regs;
> -	struct device *dev;
> -	struct clk *pll;
> -	struct clk_hw pll_hw;
> -	unsigned long pll_rate;
> -	u8 drv_imp_clk;
> -	u8 drv_imp_d2;
> -	u8 drv_imp_d1;
> -	u8 drv_imp_d0;
> -	u32 ibias;
> -	u32 ibias_up;
> -};
> -
>  static const u8 PREDIV[3][4] = {
>  	{0x0, 0x0, 0x0, 0x0},	/* 27Mhz */
>  	{0x1, 0x1, 0x1, 0x1},	/* 74Mhz */
> @@ -367,7 +354,7 @@ static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
>  	return hdmi_phy->pll_rate;
>  }
>  
> -static const struct clk_ops mtk_hdmi_pll_ops = {
> +static const struct clk_ops mtk_hdmi_phy_pll_ops = {
>  	.prepare = mtk_hdmi_pll_prepare,
>  	.unprepare = mtk_hdmi_pll_unprepare,
>  	.set_rate = mtk_hdmi_pll_set_rate,
> @@ -414,118 +401,16 @@ static int mtk_hdmi_phy_power_off(struct phy *phy)
>  	return 0;
>  }
>  
> -static const struct phy_ops mtk_hdmi_phy_ops = {
> +static const struct phy_ops mtk_hdmi_phy_dev_ops = {
>  	.power_on = mtk_hdmi_phy_power_on,
>  	.power_off = mtk_hdmi_phy_power_off,
>  	.owner = THIS_MODULE,
>  };
>  
> -static int mtk_hdmi_phy_probe(struct platform_device *pdev)
> -{
> -	struct device *dev = &pdev->dev;
> -	struct mtk_hdmi_phy *hdmi_phy;
> -	struct resource *mem;
> -	struct clk *ref_clk;
> -	const char *ref_clk_name;
> -	struct clk_init_data clk_init = {
> -		.ops = &mtk_hdmi_pll_ops,
> -		.num_parents = 1,
> -		.parent_names = (const char * const *)&ref_clk_name,
> -		.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
> -	};
> -	struct phy *phy;
> -	struct phy_provider *phy_provider;
> -	int ret;
> -
> -	hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
> -	if (!hdmi_phy)
> -		return -ENOMEM;
> -
> -	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	hdmi_phy->regs = devm_ioremap_resource(dev, mem);
> -	if (IS_ERR(hdmi_phy->regs)) {
> -		ret = PTR_ERR(hdmi_phy->regs);
> -		dev_err(dev, "Failed to get memory resource: %d\n", ret);
> -		return ret;
> -	}
> -
> -	ref_clk = devm_clk_get(dev, "pll_ref");
> -	if (IS_ERR(ref_clk)) {
> -		ret = PTR_ERR(ref_clk);
> -		dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
> -			ret);
> -		return ret;
> -	}
> -	ref_clk_name = __clk_get_name(ref_clk);
> -
> -	ret = of_property_read_string(dev->of_node, "clock-output-names",
> -				      &clk_init.name);
> -	if (ret < 0) {
> -		dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
> -		return ret;
> -	}
> -
> -	hdmi_phy->pll_hw.init = &clk_init;
> -	hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
> -	if (IS_ERR(hdmi_phy->pll)) {
> -		ret = PTR_ERR(hdmi_phy->pll);
> -		dev_err(dev, "Failed to register PLL: %d\n", ret);
> -		return ret;
> -	}
> -
> -	ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
> -				   &hdmi_phy->ibias);
> -	if (ret < 0) {
> -		dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
> -		return ret;
> -	}
> -
> -	ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
> -				   &hdmi_phy->ibias_up);
> -	if (ret < 0) {
> -		dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
> -		return ret;
> -	}
> -
> -	dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
> -	hdmi_phy->drv_imp_clk = 0x30;
> -	hdmi_phy->drv_imp_d2 = 0x30;
> -	hdmi_phy->drv_imp_d1 = 0x30;
> -	hdmi_phy->drv_imp_d0 = 0x30;
> -
> -	phy = devm_phy_create(dev, NULL, &mtk_hdmi_phy_ops);
> -	if (IS_ERR(phy)) {
> -		dev_err(dev, "Failed to create HDMI PHY\n");
> -		return PTR_ERR(phy);
> -	}
> -	phy_set_drvdata(phy, hdmi_phy);
> -
> -	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> -	if (IS_ERR(phy_provider))
> -		return PTR_ERR(phy_provider);
> -
> -	hdmi_phy->dev = dev;
> -	return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
> -				   hdmi_phy->pll);
> -}
> -
> -static int mtk_hdmi_phy_remove(struct platform_device *pdev)
> -{
> -	return 0;
> -}
> -
> -static const struct of_device_id mtk_hdmi_phy_match[] = {
> -	{ .compatible = "mediatek,mt8173-hdmi-phy", },
> -	{},
> -};
> -
> -struct platform_driver mtk_hdmi_phy_driver = {
> -	.probe = mtk_hdmi_phy_probe,
> -	.remove = mtk_hdmi_phy_remove,
> -	.driver = {
> -		.name = "mediatek-hdmi-phy",
> -		.of_match_table = mtk_hdmi_phy_match,
> -	},
> +struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = {
> +	.tz_enabled = true,
> +	.hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
> +	.hdmi_phy_dev_ops = &mtk_hdmi_phy_dev_ops,
>  };
>  
>  MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");


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[PATCH v2 07/13] drm/mediatek: separae hdmi phy to different file

[CK Hu]

Hi, Bibby:

On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> Different IC has different phy setting of HDMI.
> This patch separaes the phy hardware relate part for mt8173.
> 
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/Makefile              |  15 +--
>  drivers/gpu/drm/mediatek/mtk_hdmi.c            |  30 +++--
>  drivers/gpu/drm/mediatek/mtk_hdmi.h            |  26 +++++
>  drivers/gpu/drm/mediatek/mtk_hdmi_phy.c        | 154 +++++++++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 129 ++-------------------
>  5 files changed, 216 insertions(+), 138 deletions(-)
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> 
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index ce83c396a742..7f947979d68f 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -1,4 +1,12 @@
>  # SPDX-License-Identifier: GPL-2.0
> +mediatek-drm-hdmi-objs := mtk_cec.o \
> +			  mtk_hdmi.o \
> +			  mtk_hdmi_ddc.o \
> +			  mtk_mt8173_hdmi_phy.o \
> +			  mtk_hdmi_phy.o
> +
> +obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
> +

It looks like you just want to add mtk_hdmi_phy.o, I think you need not
to move mediatek-drm-hdmi-objs.

>  mediatek-drm-y := mtk_disp_color.o \
>  		  mtk_disp_ovl.o \
>  		  mtk_disp_rdma.o \
> @@ -14,10 +22,3 @@ mediatek-drm-y := mtk_disp_color.o \
>  		  mtk_dpi.o
>  
>  obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> -
> -mediatek-drm-hdmi-objs := mtk_cec.o \
> -			  mtk_hdmi.o \
> -			  mtk_hdmi_ddc.o \
> -			  mtk_mt8173_hdmi_phy.o
> -
> -obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index 2d45d1dd9554..7c022f3f53ec 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -233,6 +233,7 @@ static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
>  static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
>  {
>  	struct arm_smccc_res res;
> +	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(hdmi->phy);
>  
>  	/*
>  	 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI
> @@ -240,8 +241,13 @@ static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
>  	 * The ARM trusted firmware provides an API for the HDMI driver to set
>  	 * this control bit to enable HDMI output in supervisor mode.
>  	 */
> -	arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, 0x80000000,
> -		      0, 0, 0, 0, 0, &res);
> +	if (hdmi_phy->conf && hdmi_phy->conf->tz_enabled)
> +		arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904,
> +			      0x80000000, 0, 0, 0, 0, 0, &res);
> +	else
> +		regmap_update_bits(hdmi->sys_regmap,
> +				   hdmi->sys_offset + HDMI_SYS_CFG20,
> +				   0x80008005, enable ? 0x80000005 : 0x8000);

I think this should be moved to 'drm/mediatek: add hdmi driver for
MT2701 and MT7623'. If you change the variable name to tz_disabled, you
could modify this in just one patch.

>  
>  	regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
>  			   HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
> @@ -1437,6 +1443,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
>  	struct platform_device *cec_pdev;
>  	struct regmap *regmap;
>  	struct resource *mem;
> +	const char *phy_name;
>  	int ret;
>  
>  	ret = mtk_hdmi_get_all_clk(hdmi, np);
> @@ -1445,6 +1452,18 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
>  		return ret;
>  	}
>  
> +	ret = of_property_read_string(np, "phy-names", &phy_name);
> +	if (ret < 0) {
> +		dev_err(dev, "Failed to read phy-names: %d\n", ret);
> +		return ret;
> +	}
> +	hdmi->phy = devm_phy_get(dev, phy_name);
> +	if (IS_ERR(hdmi->phy)) {
> +		ret = PTR_ERR(hdmi->phy);
> +		dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
> +		return ret;
> +	}
> +

I think this part is not related to 'separate hdmi phy to different
file' and I don't know why you do this? If you really need this,
separate this to an independent patch and describe why you do this.

Regards,
CK

>  	/* The CEC module handles HDMI hotplug detection */
>  	cec_np = of_find_compatible_node(np->parent, NULL,
>  					 "mediatek,mt8173-cec");
> @@ -1677,13 +1696,6 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev)
>  	if (ret)
>  		return ret;
>  
> -	hdmi->phy = devm_phy_get(dev, "hdmi");
> -	if (IS_ERR(hdmi->phy)) {
> -		ret = PTR_ERR(hdmi->phy);
> -		dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
> -		return ret;
> -	}
> -
>  	platform_set_drvdata(pdev, hdmi);
>  
>  	ret = mtk_hdmi_output_init(hdmi);
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.h b/drivers/gpu/drm/mediatek/mtk_hdmi.h
> index 6371b3de1ff6..a350a6c9271f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.h
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.h
> @@ -13,11 +13,37 @@
>   */
>  #ifndef _MTK_HDMI_CTRL_H
>  #define _MTK_HDMI_CTRL_H
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +
> +struct mtk_hdmi_phy_conf {
> +	bool tz_enabled;
> +	const struct clk_ops *hdmi_phy_clk_ops;
> +	const struct phy_ops *hdmi_phy_dev_ops;
> +};
> +
> +struct mtk_hdmi_phy {
> +	void __iomem *regs;
> +	struct device *dev;
> +	struct mtk_hdmi_phy_conf *conf;
> +	struct clk *pll;
> +	struct clk_hw pll_hw;
> +	unsigned long pll_rate;
> +	unsigned char drv_imp_clk;
> +	unsigned char drv_imp_d2;
> +	unsigned char drv_imp_d1;
> +	unsigned char drv_imp_d0;
> +	unsigned int ibias;
> +	unsigned int ibias_up;
> +};
>  
>  struct platform_driver;
>  
>  extern struct platform_driver mtk_cec_driver;
>  extern struct platform_driver mtk_hdmi_ddc_driver;
>  extern struct platform_driver mtk_hdmi_phy_driver;
> +extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
>  
>  #endif /* _MTK_HDMI_CTRL_H */
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> new file mode 100644
> index 000000000000..82ed73575e04
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> @@ -0,0 +1,154 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Jie Qiu <jie.qiu@mediatek.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/of.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include "mtk_hdmi.h"
> +
> +static void mtk_hdmi_phy_clk_get_ops(struct mtk_hdmi_phy *hdmi_phy,
> +				     const struct clk_ops **ops)
> +{
> +	if (hdmi_phy && hdmi_phy->conf && hdmi_phy->conf->hdmi_phy_clk_ops)
> +		*ops = hdmi_phy->conf->hdmi_phy_clk_ops;
> +	else
> +		dev_err(hdmi_phy->dev, "Failed to get clk ops of phy\n");
> +}
> +
> +static const struct phy_ops *
> +mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy)
> +{
> +	if (hdmi_phy && hdmi_phy->conf && hdmi_phy->conf->hdmi_phy_dev_ops)
> +		return hdmi_phy->conf->hdmi_phy_dev_ops;
> +	dev_err(hdmi_phy->dev, "Failed to get dev ops of phy\n");
> +		return NULL;
> +}
> +
> +static int mtk_hdmi_phy_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct mtk_hdmi_phy *hdmi_phy;
> +	struct resource *mem;
> +	struct clk *ref_clk;
> +	const char *ref_clk_name;
> +	struct clk_init_data clk_init = {
> +		.num_parents = 1,
> +		.parent_names = (const char * const *)&ref_clk_name,
> +		.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
> +	};
> +
> +	struct phy *phy;
> +	struct phy_provider *phy_provider;
> +	int ret;
> +
> +	hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
> +	if (!hdmi_phy)
> +		return -ENOMEM;
> +
> +	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	hdmi_phy->regs = devm_ioremap_resource(dev, mem);
> +	if (IS_ERR(hdmi_phy->regs)) {
> +		ret = PTR_ERR(hdmi_phy->regs);
> +		dev_err(dev, "Failed to get memory resource: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ref_clk = devm_clk_get(dev, "pll_ref");
> +	if (IS_ERR(ref_clk)) {
> +		ret = PTR_ERR(ref_clk);
> +		dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
> +			ret);
> +		return ret;
> +	}
> +	ref_clk_name = __clk_get_name(ref_clk);
> +
> +	ret = of_property_read_string(dev->of_node, "clock-output-names",
> +				      &clk_init.name);
> +	if (ret < 0) {
> +		dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
> +		return ret;
> +	}
> +
> +	hdmi_phy->dev = dev;
> +	hdmi_phy->conf =
> +		(struct mtk_hdmi_phy_conf *)of_device_get_match_data(dev);
> +	mtk_hdmi_phy_clk_get_ops(hdmi_phy, &clk_init.ops);
> +	hdmi_phy->pll_hw.init = &clk_init;
> +	hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
> +	if (IS_ERR(hdmi_phy->pll)) {
> +		ret = PTR_ERR(hdmi_phy->pll);
> +		dev_err(dev, "Failed to register PLL: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
> +				   &hdmi_phy->ibias);
> +	if (ret < 0) {
> +		dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
> +				   &hdmi_phy->ibias_up);
> +	if (ret < 0) {
> +		dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
> +		return ret;
> +	}
> +
> +	dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
> +	hdmi_phy->drv_imp_clk = 0x30;
> +	hdmi_phy->drv_imp_d2 = 0x30;
> +	hdmi_phy->drv_imp_d1 = 0x30;
> +	hdmi_phy->drv_imp_d0 = 0x30;
> +
> +	phy = devm_phy_create(dev, NULL, mtk_hdmi_phy_dev_get_ops(hdmi_phy));
> +	if (IS_ERR(phy)) {
> +		dev_err(dev, "Failed to create HDMI PHY\n");
> +		return PTR_ERR(phy);
> +	}
> +	phy_set_drvdata(phy, hdmi_phy);
> +
> +	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +	if (IS_ERR(phy_provider)) {
> +		dev_err(dev, "Failed to register HDMI PHY\n");
> +		return PTR_ERR(phy_provider);
> +	}
> +
> +	return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
> +				   hdmi_phy->pll);
> +}
> +
> +static int mtk_hdmi_phy_remove(struct platform_device *pdev)
> +{
> +	return 0;
> +}
> +
> +static const struct of_device_id mtk_hdmi_phy_match[] = {
> +	{ .compatible = "mediatek,mt8173-hdmi-phy",
> +	  .data = &mtk_hdmi_phy_8173_conf,
> +	},
> +	{},
> +};
> +
> +struct platform_driver mtk_hdmi_phy_driver = {
> +	.probe = mtk_hdmi_phy_probe,
> +	.remove = mtk_hdmi_phy_remove,
> +	.driver = {
> +		.name = "mediatek-hdmi-phy",
> +		.of_match_table = mtk_hdmi_phy_match,
> +	},
> +};
> +
> +MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> index 51cb9cfb6646..1a35fdd405d8 100644
> --- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> +++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> @@ -21,6 +21,7 @@
>  #include <linux/phy/phy.h>
>  #include <linux/platform_device.h>
>  #include <linux/types.h>
> +#include "mtk_hdmi.h"
>  
>  #define HDMI_CON0		0x00
>  #define RG_HDMITX_PLL_EN		BIT(31)
> @@ -123,20 +124,6 @@
>  #define RGS_HDMITX_5T1_EDG		(0xf << 4)
>  #define RGS_HDMITX_PLUG_TST		BIT(0)
>  
> -struct mtk_hdmi_phy {
> -	void __iomem *regs;
> -	struct device *dev;
> -	struct clk *pll;
> -	struct clk_hw pll_hw;
> -	unsigned long pll_rate;
> -	u8 drv_imp_clk;
> -	u8 drv_imp_d2;
> -	u8 drv_imp_d1;
> -	u8 drv_imp_d0;
> -	u32 ibias;
> -	u32 ibias_up;
> -};
> -
>  static const u8 PREDIV[3][4] = {
>  	{0x0, 0x0, 0x0, 0x0},	/* 27Mhz */
>  	{0x1, 0x1, 0x1, 0x1},	/* 74Mhz */
> @@ -367,7 +354,7 @@ static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
>  	return hdmi_phy->pll_rate;
>  }
>  
> -static const struct clk_ops mtk_hdmi_pll_ops = {
> +static const struct clk_ops mtk_hdmi_phy_pll_ops = {
>  	.prepare = mtk_hdmi_pll_prepare,
>  	.unprepare = mtk_hdmi_pll_unprepare,
>  	.set_rate = mtk_hdmi_pll_set_rate,
> @@ -414,118 +401,16 @@ static int mtk_hdmi_phy_power_off(struct phy *phy)
>  	return 0;
>  }
>  
> -static const struct phy_ops mtk_hdmi_phy_ops = {
> +static const struct phy_ops mtk_hdmi_phy_dev_ops = {
>  	.power_on = mtk_hdmi_phy_power_on,
>  	.power_off = mtk_hdmi_phy_power_off,
>  	.owner = THIS_MODULE,
>  };
>  
> -static int mtk_hdmi_phy_probe(struct platform_device *pdev)
> -{
> -	struct device *dev = &pdev->dev;
> -	struct mtk_hdmi_phy *hdmi_phy;
> -	struct resource *mem;
> -	struct clk *ref_clk;
> -	const char *ref_clk_name;
> -	struct clk_init_data clk_init = {
> -		.ops = &mtk_hdmi_pll_ops,
> -		.num_parents = 1,
> -		.parent_names = (const char * const *)&ref_clk_name,
> -		.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
> -	};
> -	struct phy *phy;
> -	struct phy_provider *phy_provider;
> -	int ret;
> -
> -	hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
> -	if (!hdmi_phy)
> -		return -ENOMEM;
> -
> -	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	hdmi_phy->regs = devm_ioremap_resource(dev, mem);
> -	if (IS_ERR(hdmi_phy->regs)) {
> -		ret = PTR_ERR(hdmi_phy->regs);
> -		dev_err(dev, "Failed to get memory resource: %d\n", ret);
> -		return ret;
> -	}
> -
> -	ref_clk = devm_clk_get(dev, "pll_ref");
> -	if (IS_ERR(ref_clk)) {
> -		ret = PTR_ERR(ref_clk);
> -		dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
> -			ret);
> -		return ret;
> -	}
> -	ref_clk_name = __clk_get_name(ref_clk);
> -
> -	ret = of_property_read_string(dev->of_node, "clock-output-names",
> -				      &clk_init.name);
> -	if (ret < 0) {
> -		dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
> -		return ret;
> -	}
> -
> -	hdmi_phy->pll_hw.init = &clk_init;
> -	hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
> -	if (IS_ERR(hdmi_phy->pll)) {
> -		ret = PTR_ERR(hdmi_phy->pll);
> -		dev_err(dev, "Failed to register PLL: %d\n", ret);
> -		return ret;
> -	}
> -
> -	ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
> -				   &hdmi_phy->ibias);
> -	if (ret < 0) {
> -		dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
> -		return ret;
> -	}
> -
> -	ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
> -				   &hdmi_phy->ibias_up);
> -	if (ret < 0) {
> -		dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
> -		return ret;
> -	}
> -
> -	dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
> -	hdmi_phy->drv_imp_clk = 0x30;
> -	hdmi_phy->drv_imp_d2 = 0x30;
> -	hdmi_phy->drv_imp_d1 = 0x30;
> -	hdmi_phy->drv_imp_d0 = 0x30;
> -
> -	phy = devm_phy_create(dev, NULL, &mtk_hdmi_phy_ops);
> -	if (IS_ERR(phy)) {
> -		dev_err(dev, "Failed to create HDMI PHY\n");
> -		return PTR_ERR(phy);
> -	}
> -	phy_set_drvdata(phy, hdmi_phy);
> -
> -	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> -	if (IS_ERR(phy_provider))
> -		return PTR_ERR(phy_provider);
> -
> -	hdmi_phy->dev = dev;
> -	return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
> -				   hdmi_phy->pll);
> -}
> -
> -static int mtk_hdmi_phy_remove(struct platform_device *pdev)
> -{
> -	return 0;
> -}
> -
> -static const struct of_device_id mtk_hdmi_phy_match[] = {
> -	{ .compatible = "mediatek,mt8173-hdmi-phy", },
> -	{},
> -};
> -
> -struct platform_driver mtk_hdmi_phy_driver = {
> -	.probe = mtk_hdmi_phy_probe,
> -	.remove = mtk_hdmi_phy_remove,
> -	.driver = {
> -		.name = "mediatek-hdmi-phy",
> -		.of_match_table = mtk_hdmi_phy_match,
> -	},
> +struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = {
> +	.tz_enabled = true,
> +	.hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
> +	.hdmi_phy_dev_ops = &mtk_hdmi_phy_dev_ops,
>  };
>  
>  MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");

Re: [PATCH v2 13/13] drm/mediatek: config component output by device node port

[Bibby Hsieh]

Hi, CK,

Thanks for the review comment.
I will add the description in the binding document in v4.

I want to send the other changes in v3 first.

Thanks.

Bibby


On Thu, 2018-09-06 at 14:03 +0800, CK Hu wrote:
> Hi, Bibby:
> 
> On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> > We can select output component by decive node port.
> > Main path default output component is DSI.
> > External path default output component is DPI.
> > 
> > Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c | 37 ++++++++++++++++++++++++++++++----
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.h |  4 ++--
> >  2 files changed, 35 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index d961112fa2f5..a477fb878c06 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -21,7 +21,9 @@
> >  #include <drm/drm_of.h>
> >  #include <linux/component.h>
> >  #include <linux/iommu.h>
> > +#include <linux/of.h>
> >  #include <linux/of_address.h>
> > +#include <linux/of_graph.h>
> >  #include <linux/of_platform.h>
> >  #include <linux/pm_runtime.h>
> >  
> > @@ -133,7 +135,7 @@ static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
> >  	.atomic_commit = mtk_atomic_commit,
> >  };
> >  
> > -static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
> > +static enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
> >  	DDP_COMPONENT_OVL0,
> >  	DDP_COMPONENT_RDMA0,
> >  	DDP_COMPONENT_COLOR0,
> > @@ -141,7 +143,7 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
> >  	DDP_COMPONENT_DSI0,
> >  };
> >  
> > -static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
> > +static enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
> >  	DDP_COMPONENT_RDMA1,
> >  	DDP_COMPONENT_DPI0,
> >  };
> > @@ -172,7 +174,7 @@ static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = {
> >  	DDP_COMPONENT_PWM2,
> >  };
> >  
> > -static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
> > +static enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
> >  	DDP_COMPONENT_OVL0,
> >  	DDP_COMPONENT_COLOR0,
> >  	DDP_COMPONENT_AAL0,
> > @@ -183,7 +185,7 @@ static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
> >  	DDP_COMPONENT_PWM0,
> >  };
> >  
> > -static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
> > +static enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
> >  	DDP_COMPONENT_OVL1,
> >  	DDP_COMPONENT_COLOR1,
> >  	DDP_COMPONENT_GAMMA,
> > @@ -472,6 +474,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
> >  
> >  	/* Iterate over sibling DISP function blocks */
> >  	for_each_child_of_node(dev->of_node->parent, node) {
> > +		struct device_node *port, *ep, *remote;
> >  		const struct of_device_id *of_id;
> >  		enum mtk_ddp_comp_type comp_type;
> >  		int comp_id;
> > @@ -531,6 +534,32 @@ static int mtk_drm_probe(struct platform_device *pdev)
> >  
> >  			private->ddp_comp[comp_id] = comp;
> >  		}
> > +
> > +		if (comp_type != MTK_DSI && comp_type != MTK_DPI) {
> > +			port = of_graph_get_port_by_id(node, 0);
> > +			if (!port)
> > +				continue;
> > +			ep = of_get_child_by_name(port, "endpoint");
> > +			of_node_put(port);
> > +			if (!ep)
> > +				continue;
> > +			remote = of_graph_get_remote_port_parent(ep);
> > +			of_node_put(ep);
> > +			if (!remote)
> > +				continue;
> > +			of_id = of_match_node(mtk_ddp_comp_dt_ids, remote);
> > +			if (!of_id)
> > +				continue;
> > +			comp_type = (enum mtk_ddp_comp_type)of_id->data;
> > +			for (i = 0; i < private->data->main_len - 1; i++)
> > +				if (private->data->main_path[i] == comp_id)
> > +					private->data->main_path[i + 1] =
> > +					mtk_ddp_comp_get_id(node, comp_type);
> > +			for (i = 0; i < private->data->ext_len - 1; i++)
> > +				if (private->data->ext_path[i] == comp_id)
> > +					private->data->ext_path[i + 1] =
> > +					mtk_ddp_comp_get_id(node, comp_type);
> > +		}
> 
> I think you should add description in binding document
> (Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt)
> for this. After the binding document is fully reviewed, we could start
> to review this patch.
> 
> Regards,
> CK
> 
> >  	}
> >  
> >  	if (!private->mutex_node) {
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index ecc00ca3221d..256a3ff2e66e 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -29,9 +29,9 @@ struct drm_property;
> >  struct regmap;
> >  
> >  struct mtk_mmsys_driver_data {
> > -	const enum mtk_ddp_comp_id *main_path;
> > +	enum mtk_ddp_comp_id *main_path;
> >  	unsigned int main_len;
> > -	const enum mtk_ddp_comp_id *ext_path;
> > +	enum mtk_ddp_comp_id *ext_path;
> >  	unsigned int ext_len;
> >  	const enum mtk_ddp_comp_id *third_path;
> >  	unsigned int third_len;
> 
> 

-- 
Bibby

Re: [PATCH v2 13/13] drm/mediatek: config component output by device node port

[Bibby Hsieh]

Hi, CK,

Thanks for the review comment.
I will add the description in the binding document in v4.

I want to send the other changes in v3 first.

Thanks.

Bibby


On Thu, 2018-09-06 at 14:03 +0800, CK Hu wrote:
> Hi, Bibby:
> 
> On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> > We can select output component by decive node port.
> > Main path default output component is DSI.
> > External path default output component is DPI.
> > 
> > Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c | 37 ++++++++++++++++++++++++++++++----
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.h |  4 ++--
> >  2 files changed, 35 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index d961112fa2f5..a477fb878c06 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -21,7 +21,9 @@
> >  #include <drm/drm_of.h>
> >  #include <linux/component.h>
> >  #include <linux/iommu.h>
> > +#include <linux/of.h>
> >  #include <linux/of_address.h>
> > +#include <linux/of_graph.h>
> >  #include <linux/of_platform.h>
> >  #include <linux/pm_runtime.h>
> >  
> > @@ -133,7 +135,7 @@ static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
> >  	.atomic_commit = mtk_atomic_commit,
> >  };
> >  
> > -static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
> > +static enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
> >  	DDP_COMPONENT_OVL0,
> >  	DDP_COMPONENT_RDMA0,
> >  	DDP_COMPONENT_COLOR0,
> > @@ -141,7 +143,7 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
> >  	DDP_COMPONENT_DSI0,
> >  };
> >  
> > -static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
> > +static enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
> >  	DDP_COMPONENT_RDMA1,
> >  	DDP_COMPONENT_DPI0,
> >  };
> > @@ -172,7 +174,7 @@ static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = {
> >  	DDP_COMPONENT_PWM2,
> >  };
> >  
> > -static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
> > +static enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
> >  	DDP_COMPONENT_OVL0,
> >  	DDP_COMPONENT_COLOR0,
> >  	DDP_COMPONENT_AAL0,
> > @@ -183,7 +185,7 @@ static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
> >  	DDP_COMPONENT_PWM0,
> >  };
> >  
> > -static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
> > +static enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
> >  	DDP_COMPONENT_OVL1,
> >  	DDP_COMPONENT_COLOR1,
> >  	DDP_COMPONENT_GAMMA,
> > @@ -472,6 +474,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
> >  
> >  	/* Iterate over sibling DISP function blocks */
> >  	for_each_child_of_node(dev->of_node->parent, node) {
> > +		struct device_node *port, *ep, *remote;
> >  		const struct of_device_id *of_id;
> >  		enum mtk_ddp_comp_type comp_type;
> >  		int comp_id;
> > @@ -531,6 +534,32 @@ static int mtk_drm_probe(struct platform_device *pdev)
> >  
> >  			private->ddp_comp[comp_id] = comp;
> >  		}
> > +
> > +		if (comp_type != MTK_DSI && comp_type != MTK_DPI) {
> > +			port = of_graph_get_port_by_id(node, 0);
> > +			if (!port)
> > +				continue;
> > +			ep = of_get_child_by_name(port, "endpoint");
> > +			of_node_put(port);
> > +			if (!ep)
> > +				continue;
> > +			remote = of_graph_get_remote_port_parent(ep);
> > +			of_node_put(ep);
> > +			if (!remote)
> > +				continue;
> > +			of_id = of_match_node(mtk_ddp_comp_dt_ids, remote);
> > +			if (!of_id)
> > +				continue;
> > +			comp_type = (enum mtk_ddp_comp_type)of_id->data;
> > +			for (i = 0; i < private->data->main_len - 1; i++)
> > +				if (private->data->main_path[i] == comp_id)
> > +					private->data->main_path[i + 1] =
> > +					mtk_ddp_comp_get_id(node, comp_type);
> > +			for (i = 0; i < private->data->ext_len - 1; i++)
> > +				if (private->data->ext_path[i] == comp_id)
> > +					private->data->ext_path[i + 1] =
> > +					mtk_ddp_comp_get_id(node, comp_type);
> > +		}
> 
> I think you should add description in binding document
> (Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt)
> for this. After the binding document is fully reviewed, we could start
> to review this patch.
> 
> Regards,
> CK
> 
> >  	}
> >  
> >  	if (!private->mutex_node) {
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index ecc00ca3221d..256a3ff2e66e 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -29,9 +29,9 @@ struct drm_property;
> >  struct regmap;
> >  
> >  struct mtk_mmsys_driver_data {
> > -	const enum mtk_ddp_comp_id *main_path;
> > +	enum mtk_ddp_comp_id *main_path;
> >  	unsigned int main_len;
> > -	const enum mtk_ddp_comp_id *ext_path;
> > +	enum mtk_ddp_comp_id *ext_path;
> >  	unsigned int ext_len;
> >  	const enum mtk_ddp_comp_id *third_path;
> >  	unsigned int third_len;
> 
> 

-- 
Bibby

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[PATCH v2 13/13] drm/mediatek: config component output by device node port

[Bibby Hsieh]

Hi, CK,

Thanks for the review comment.
I will add the description in the binding document in v4.

I want to send the other changes in v3 first.

Thanks.

Bibby


On Thu, 2018-09-06 at 14:03 +0800, CK Hu wrote:
> Hi, Bibby:
> 
> On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> > We can select output component by decive node port.
> > Main path default output component is DSI.
> > External path default output component is DPI.
> > 
> > Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c | 37 ++++++++++++++++++++++++++++++----
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.h |  4 ++--
> >  2 files changed, 35 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index d961112fa2f5..a477fb878c06 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -21,7 +21,9 @@
> >  #include <drm/drm_of.h>
> >  #include <linux/component.h>
> >  #include <linux/iommu.h>
> > +#include <linux/of.h>
> >  #include <linux/of_address.h>
> > +#include <linux/of_graph.h>
> >  #include <linux/of_platform.h>
> >  #include <linux/pm_runtime.h>
> >  
> > @@ -133,7 +135,7 @@ static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
> >  	.atomic_commit = mtk_atomic_commit,
> >  };
> >  
> > -static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
> > +static enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
> >  	DDP_COMPONENT_OVL0,
> >  	DDP_COMPONENT_RDMA0,
> >  	DDP_COMPONENT_COLOR0,
> > @@ -141,7 +143,7 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
> >  	DDP_COMPONENT_DSI0,
> >  };
> >  
> > -static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
> > +static enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
> >  	DDP_COMPONENT_RDMA1,
> >  	DDP_COMPONENT_DPI0,
> >  };
> > @@ -172,7 +174,7 @@ static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = {
> >  	DDP_COMPONENT_PWM2,
> >  };
> >  
> > -static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
> > +static enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
> >  	DDP_COMPONENT_OVL0,
> >  	DDP_COMPONENT_COLOR0,
> >  	DDP_COMPONENT_AAL0,
> > @@ -183,7 +185,7 @@ static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
> >  	DDP_COMPONENT_PWM0,
> >  };
> >  
> > -static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
> > +static enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
> >  	DDP_COMPONENT_OVL1,
> >  	DDP_COMPONENT_COLOR1,
> >  	DDP_COMPONENT_GAMMA,
> > @@ -472,6 +474,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
> >  
> >  	/* Iterate over sibling DISP function blocks */
> >  	for_each_child_of_node(dev->of_node->parent, node) {
> > +		struct device_node *port, *ep, *remote;
> >  		const struct of_device_id *of_id;
> >  		enum mtk_ddp_comp_type comp_type;
> >  		int comp_id;
> > @@ -531,6 +534,32 @@ static int mtk_drm_probe(struct platform_device *pdev)
> >  
> >  			private->ddp_comp[comp_id] = comp;
> >  		}
> > +
> > +		if (comp_type != MTK_DSI && comp_type != MTK_DPI) {
> > +			port = of_graph_get_port_by_id(node, 0);
> > +			if (!port)
> > +				continue;
> > +			ep = of_get_child_by_name(port, "endpoint");
> > +			of_node_put(port);
> > +			if (!ep)
> > +				continue;
> > +			remote = of_graph_get_remote_port_parent(ep);
> > +			of_node_put(ep);
> > +			if (!remote)
> > +				continue;
> > +			of_id = of_match_node(mtk_ddp_comp_dt_ids, remote);
> > +			if (!of_id)
> > +				continue;
> > +			comp_type = (enum mtk_ddp_comp_type)of_id->data;
> > +			for (i = 0; i < private->data->main_len - 1; i++)
> > +				if (private->data->main_path[i] == comp_id)
> > +					private->data->main_path[i + 1] =
> > +					mtk_ddp_comp_get_id(node, comp_type);
> > +			for (i = 0; i < private->data->ext_len - 1; i++)
> > +				if (private->data->ext_path[i] == comp_id)
> > +					private->data->ext_path[i + 1] =
> > +					mtk_ddp_comp_get_id(node, comp_type);
> > +		}
> 
> I think you should add description in binding document
> (Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt)
> for this. After the binding document is fully reviewed, we could start
> to review this patch.
> 
> Regards,
> CK
> 
> >  	}
> >  
> >  	if (!private->mutex_node) {
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index ecc00ca3221d..256a3ff2e66e 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -29,9 +29,9 @@ struct drm_property;
> >  struct regmap;
> >  
> >  struct mtk_mmsys_driver_data {
> > -	const enum mtk_ddp_comp_id *main_path;
> > +	enum mtk_ddp_comp_id *main_path;
> >  	unsigned int main_len;
> > -	const enum mtk_ddp_comp_id *ext_path;
> > +	enum mtk_ddp_comp_id *ext_path;
> >  	unsigned int ext_len;
> >  	const enum mtk_ddp_comp_id *third_path;
> >  	unsigned int third_len;
> 
> 

-- 
Bibby