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From: Bin Meng <bmeng.cn@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [RESEND PATCH v2 09/15] riscv: Remove CSR read/write defines in encoding.h
Date: Mon, 10 Sep 2018 21:54:48 -0700	[thread overview]
Message-ID: <1536641694-4200-10-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1536641694-4200-1-git-send-email-bmeng.cn@gmail.com>

There is no reason to keep two versions of CSR read/write defines
in encoding.h. We already have one set of defines in csr.h, which
is from Linux kernel, and let's drop the one in encoding.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

Changes in v2:
- new patch to remove CSR read/write defines in encoding.h

 arch/riscv/include/asm/encoding.h | 50 ++++-----------------------------------
 1 file changed, 4 insertions(+), 46 deletions(-)

diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h
index f237a72..9ea50ce 100644
--- a/arch/riscv/include/asm/encoding.h
+++ b/arch/riscv/include/asm/encoding.h
@@ -128,6 +128,7 @@
 	((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
 
 #ifdef __riscv
+
 #ifdef CONFIG_64BIT
 # define MSTATUS_SD MSTATUS64_SD
 # define SSTATUS_SD SSTATUS64_SD
@@ -141,53 +142,10 @@
 # define MCAUSE_INT MCAUSE32_INT
 # define MCAUSE_CAUSE MCAUSE32_CAUSE
 #endif
+
 #define RISCV_PGSHIFT 12
 #define RISCV_PGSIZE BIT(RISCV_PGSHIFT)
 
-#ifndef __ASSEMBLER__
-
-#ifdef __GNUC__
-
-#define read_csr(reg) ({ unsigned long __tmp; \
-	asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
-	__tmp; })
-
-#define write_csr(reg, _val) ({ \
-typeof(_val) (val) = (_val); \
-if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
-	asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
-else \
-	asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
-
-#define swap_csr(reg, _val) ({ unsigned long __tmp; \
-typeof(_val) (val) = (_val); \
-if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
-	asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
-else \
-	asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
-	__tmp; })
-
-#define set_csr(reg, _bit) ({ unsigned long __tmp; \
-typeof(_bit) (bit) = (_bit); \
-if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
-	asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
-else \
-	asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
-	__tmp; })
-
-#define clear_csr(reg, _bit) ({ unsigned long __tmp; \
-typeof(_bit) (bit) = (_bit); \
-if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
-	asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
-else \
-	asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
-	__tmp; })
-
-#define rdtime() read_csr(time)
-#define rdcycle() read_csr(cycle)
-#define rdinstret() read_csr(instret)
+#endif /* __riscv */
 
-#endif
-#endif
-#endif
-#endif
+#endif /* RISCV_CSR_ENCODING_H */
-- 
2.7.4

  parent reply	other threads:[~2018-09-11  4:54 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-11  4:54 [U-Boot] [RESEND PATCH v2 00/15] riscv: Add QEMU virt board support Bin Meng
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 01/15] riscv: kconfig: Normalize architecture name spelling Bin Meng
2018-09-16 20:43   ` Auer, Lukas
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA2F93D39@ATCPCS16.andestech.com>
2018-09-20  3:15     ` Rick Chen
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 02/15] riscv: Remove setup.h Bin Meng
2018-09-16 20:44   ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 03/15] riscv: bootm: Correct the 1st kernel argument to hart id Bin Meng
2018-09-16 20:45   ` Auer, Lukas
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA2F93D4E@ATCPCS16.andestech.com>
2018-09-20  3:17     ` Rick Chen
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 04/15] riscv: Remove mach type Bin Meng
2018-09-16 20:46   ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 05/15] riscv: Move the linker script to the CPU root directory Bin Meng
2018-09-16 20:47   ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 06/15] riscv: Fix coding style issues in the linker script Bin Meng
2018-09-16 20:49   ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 07/15] riscv: Explicitly pass -march and -mabi to the compiler Bin Meng
2018-09-16 20:51   ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 08/15] riscv: Add a helper routine to print CPU information Bin Meng
2018-09-16 20:54   ` Auer, Lukas
2018-09-17  4:55     ` Bin Meng
2018-09-17 21:59       ` Auer, Lukas
2018-09-18  8:53         ` Bin Meng
2018-09-18 10:53           ` Auer, Lukas
2018-09-11  4:54 ` Bin Meng [this message]
2018-09-16 20:55   ` [U-Boot] [RESEND PATCH v2 09/15] riscv: Remove CSR read/write defines in encoding.h Auer, Lukas
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA2F93D8B@ATCPCS16.andestech.com>
2018-09-20  3:20     ` Rick Chen
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 10/15] riscv: bootm: Pass mhartid CSR value to kernel Bin Meng
2018-09-16 20:55   ` Auer, Lukas
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA2F93D92@ATCPCS16.andestech.com>
2018-09-20  3:22     ` Rick Chen
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 11/15] riscv: Make start.S available for all targets Bin Meng
2018-09-16 20:56   ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 12/15] riscv: ae350: Clean up mixed tabs and spaces in the dts Bin Meng
2018-09-16 20:57   ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 13/15] riscv: kconfig: Select DM and OF_CONTROL Bin Meng
2018-09-16 20:58   ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 14/15] riscv: Add QEMU virt board support Bin Meng
2018-09-16 21:02   ` Auer, Lukas
2018-09-17  5:18     ` Bin Meng
2018-09-17 21:54       ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 15/15] riscv: Move do_reset() to a common place Bin Meng
2018-09-16 21:09   ` Auer, Lukas
2018-09-17  5:02     ` Bin Meng
2018-09-17 22:01       ` Auer, Lukas
2018-09-18  8:50         ` Bin Meng
2018-09-18 10:54           ` Auer, Lukas
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA2F93DD7@ATCPCS16.andestech.com>
2018-09-20  3:26     ` Rick Chen
2018-09-16 10:57 ` [U-Boot] [RESEND PATCH v2 00/15] riscv: Add QEMU virt board support Bin Meng
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA2F93D22@ATCPCS16.andestech.com>
2018-09-20  3:00     ` Rick Chen
2018-09-20  3:21       ` Bin Meng

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