All of lore.kernel.org
 help / color / mirror / Atom feed
From: Rick Chen <rickchen36@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [RESEND PATCH v2 00/15] riscv: Add QEMU virt board support
Date: Thu, 20 Sep 2018 11:00:22 +0800	[thread overview]
Message-ID: <CAN5B=e+CpHNOPG9cNLhFj9WLjsYG-fZYQga50jBa4OfBNFJ5EA@mail.gmail.com> (raw)
In-Reply-To: <752D002CFF5D0F4FA35C0100F1D73F3FA2F93D22@ATCPCS16.andestech.com>

 > Hi Rick,
 >
 > On Tue, Sep 11, 2018 at 12:50 PM Bin Meng <bmeng.cn@gmail.com> wrote:
 > >
 > > This series adds QEMU RISC-V 'virt' board target support, with the
 > > hope of helping people easily test U-Boot on RISC-V.
 > >
 > > Some existing RISC-V codes have been changed to make it easily to
 > > support new targets. Some spotted coding style issues are fixed.
 > >
 > > This series is available at u-boot-x86/riscv-working for testing.
 > >
 > > Resend v2 to rebase on top of v2018.09 release with Tom's tree on
 > > github, as the git.denx.de is still out of sync ...
 > >
 > > Changes in v2:
 > > - Change Linux kernel entry parameters' type to support 32/64 bit
 > > - new patch to remove CSR read/write defines in encoding.h
 > > - new patch to pass mhartid CSR value to kernel
 > > - new patch to move do_reset() to a common place
 >
 > Any comments for the v2?

Hi Bin

Sorry for late response!

I have reviewed the v2 patch sets, it looks fine.
And also verify the riscv-linux booting feature on ax25-ae350 board
via bootm command.
The verification is OK. :)

B.R

Rick


 >
 > Regards,
 > Bin

  parent reply	other threads:[~2018-09-20  3:00 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-11  4:54 [U-Boot] [RESEND PATCH v2 00/15] riscv: Add QEMU virt board support Bin Meng
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 01/15] riscv: kconfig: Normalize architecture name spelling Bin Meng
2018-09-16 20:43   ` Auer, Lukas
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA2F93D39@ATCPCS16.andestech.com>
2018-09-20  3:15     ` Rick Chen
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 02/15] riscv: Remove setup.h Bin Meng
2018-09-16 20:44   ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 03/15] riscv: bootm: Correct the 1st kernel argument to hart id Bin Meng
2018-09-16 20:45   ` Auer, Lukas
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA2F93D4E@ATCPCS16.andestech.com>
2018-09-20  3:17     ` Rick Chen
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 04/15] riscv: Remove mach type Bin Meng
2018-09-16 20:46   ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 05/15] riscv: Move the linker script to the CPU root directory Bin Meng
2018-09-16 20:47   ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 06/15] riscv: Fix coding style issues in the linker script Bin Meng
2018-09-16 20:49   ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 07/15] riscv: Explicitly pass -march and -mabi to the compiler Bin Meng
2018-09-16 20:51   ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 08/15] riscv: Add a helper routine to print CPU information Bin Meng
2018-09-16 20:54   ` Auer, Lukas
2018-09-17  4:55     ` Bin Meng
2018-09-17 21:59       ` Auer, Lukas
2018-09-18  8:53         ` Bin Meng
2018-09-18 10:53           ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 09/15] riscv: Remove CSR read/write defines in encoding.h Bin Meng
2018-09-16 20:55   ` Auer, Lukas
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA2F93D8B@ATCPCS16.andestech.com>
2018-09-20  3:20     ` Rick Chen
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 10/15] riscv: bootm: Pass mhartid CSR value to kernel Bin Meng
2018-09-16 20:55   ` Auer, Lukas
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA2F93D92@ATCPCS16.andestech.com>
2018-09-20  3:22     ` Rick Chen
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 11/15] riscv: Make start.S available for all targets Bin Meng
2018-09-16 20:56   ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 12/15] riscv: ae350: Clean up mixed tabs and spaces in the dts Bin Meng
2018-09-16 20:57   ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 13/15] riscv: kconfig: Select DM and OF_CONTROL Bin Meng
2018-09-16 20:58   ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 14/15] riscv: Add QEMU virt board support Bin Meng
2018-09-16 21:02   ` Auer, Lukas
2018-09-17  5:18     ` Bin Meng
2018-09-17 21:54       ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 15/15] riscv: Move do_reset() to a common place Bin Meng
2018-09-16 21:09   ` Auer, Lukas
2018-09-17  5:02     ` Bin Meng
2018-09-17 22:01       ` Auer, Lukas
2018-09-18  8:50         ` Bin Meng
2018-09-18 10:54           ` Auer, Lukas
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA2F93DD7@ATCPCS16.andestech.com>
2018-09-20  3:26     ` Rick Chen
2018-09-16 10:57 ` [U-Boot] [RESEND PATCH v2 00/15] riscv: Add QEMU virt board support Bin Meng
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA2F93D22@ATCPCS16.andestech.com>
2018-09-20  3:00     ` Rick Chen [this message]
2018-09-20  3:21       ` Bin Meng

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to='CAN5B=e+CpHNOPG9cNLhFj9WLjsYG-fZYQga50jBa4OfBNFJ5EA@mail.gmail.com' \
    --to=rickchen36@gmail.com \
    --cc=u-boot@lists.denx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.