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From: Bin Meng <bmeng.cn@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [RESEND PATCH v2 12/15] riscv: ae350: Clean up mixed tabs and spaces in the dts
Date: Mon, 10 Sep 2018 21:54:51 -0700	[thread overview]
Message-ID: <1536641694-4200-13-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1536641694-4200-1-git-send-email-bmeng.cn@gmail.com>

There are quite a lot of mixed tabs and spaces in the ae350.dts.
Clean them up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 arch/riscv/dts/ae350.dts | 177 ++++++++++++++++++++++++-----------------------
 1 file changed, 90 insertions(+), 87 deletions(-)

diff --git a/arch/riscv/dts/ae350.dts b/arch/riscv/dts/ae350.dts
index 2927e41..4717ae8 100644
--- a/arch/riscv/dts/ae350.dts
+++ b/arch/riscv/dts/ae350.dts
@@ -1,144 +1,147 @@
 /dts-v1/;
 
 / {
-  #address-cells = <2>;
-  #size-cells = <2>;
-  compatible = "andestech,ax25";
-  model = "andestech,ax25";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	compatible = "andestech,ax25";
+	model = "andestech,ax25";
 
 	aliases {
 		uart0 = &serial0;
 		spi0 = &spi;
-	} ;
+	};
 
 	chosen {
 		bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7";
 		stdout-path = "uart0:38400n8";
-  };
-
-  cpus {
-    #address-cells = <1>;
-    #size-cells = <0>;
-    timebase-frequency = <10000000>;
-    CPU0: cpu at 0 {
-      device_type = "cpu";
-      reg = <0>;
-      status = "okay";
-      compatible = "riscv";
-      riscv,isa = "rv64imafdc";
-      mmu-type = "riscv,sv39";
-      clock-frequency = <60000000>;
-      CPU0_intc: interrupt-controller {
-        #interrupt-cells = <1>;
-        interrupt-controller;
-        compatible = "riscv,cpu-intc";
-      };
-    };
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <10000000>;
+
+		CPU0: cpu at 0 {
+			device_type = "cpu";
+			reg = <0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdc";
+			mmu-type = "riscv,sv39";
+			clock-frequency = <60000000>;
+
+			CPU0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
 	};
 
 	memory at 0 {
 		device_type = "memory";
-    reg = <0x0 0x00000000 0x0 0x40000000>;
+		reg = <0x0 0x00000000 0x0 0x40000000>;
 	};
 
-  soc {
-    #address-cells = <2>;
-    #size-cells = <2>;
-    compatible = "andestech,riscv-ae350-soc";
-    ranges;
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "andestech,riscv-ae350-soc";
+		ranges;
 	};
 
-  plmt0 at e6000000 {
-    compatible = "riscv,plmt0";
-    interrupts-extended = <&CPU0_intc 7>;
-    reg = <0x0 0xe6000000 0x0 0x100000>;
-		};
+	plmt0 at e6000000 {
+		compatible = "riscv,plmt0";
+		interrupts-extended = <&CPU0_intc 7>;
+		reg = <0x0 0xe6000000 0x0 0x100000>;
+	};
 
-  plic0: interrupt-controller at e4000000 {
-    compatible = "riscv,plic0";
-    #address-cells = <2>;
-    #interrupt-cells = <2>;
-    interrupt-controller;
-    reg = <0x0 0xe4000000 0x0 0x2000000>;
-    riscv,ndev=<31>;
-    interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
+	plic0: interrupt-controller at e4000000 {
+		compatible = "riscv,plic0";
+		#address-cells = <2>;
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		reg = <0x0 0xe4000000 0x0 0x2000000>;
+		riscv,ndev=<31>;
+		interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
 	};
 
-  plic1: interrupt-controller at e6400000 {
-    compatible = "riscv,plic1";
-    #address-cells = <2>;
-    #interrupt-cells = <2>;
+	plic1: interrupt-controller at e6400000 {
+		compatible = "riscv,plic1";
+		#address-cells = <2>;
+		#interrupt-cells = <2>;
 		interrupt-controller;
-    reg = <0x0 0xe6400000 0x0 0x400000>;
-    riscv,ndev=<1>;
-    interrupts-extended = <&CPU0_intc 3>;
-  };
+		reg = <0x0 0xe6400000 0x0 0x400000>;
+		riscv,ndev=<1>;
+		interrupts-extended = <&CPU0_intc 3>;
+	};
 
-  spiclk: virt_100mhz {
-    #clock-cells = <0>;
-    compatible = "fixed-clock";
-    clock-frequency = <100000000>;
-  };
+	spiclk: virt_100mhz {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <100000000>;
+	};
 
-  timer0: timer at f0400000 {
-    compatible = "andestech,atcpit100";
-    reg = <0x0 0xf0400000 0x0 0x1000>;
-    clock-frequency = <40000000>;
-    interrupts = <3 4>;
-    interrupt-parent = <&plic0>;
+	timer0: timer at f0400000 {
+		compatible = "andestech,atcpit100";
+		reg = <0x0 0xf0400000 0x0 0x1000>;
+		clock-frequency = <40000000>;
+		interrupts = <3 4>;
+		interrupt-parent = <&plic0>;
 	};
 
 	serial0: serial at f0300000 {
 		compatible = "andestech,uart16550", "ns16550a";
-    reg = <0x0 0xf0300000 0x0 0x1000>;
-    interrupts = <9 4>;
+		reg = <0x0 0xf0300000 0x0 0x1000>;
+		interrupts = <9 4>;
 		clock-frequency = <19660800>;
 		reg-shift = <2>;
 		reg-offset = <32>;
 		no-loopback-test = <1>;
-    interrupt-parent = <&plic0>;
+		interrupt-parent = <&plic0>;
 	};
 
 	mac0: mac at e0100000 {
 		compatible = "andestech,atmac100";
-    reg = <0x0 0xe0100000 0x0 0x1000>;
-    interrupts = <19 4>;
-    interrupt-parent = <&plic0>;
+		reg = <0x0 0xe0100000 0x0 0x1000>;
+		interrupts = <19 4>;
+		interrupt-parent = <&plic0>;
 	};
 
 	mmc0: mmc at f0e00000 {
-    compatible = "andestech,atfsdc010";
+		compatible = "andestech,atfsdc010";
 		max-frequency = <100000000>;
-    clock-freq-min-max = <400000 100000000>;
+		clock-freq-min-max = <400000 100000000>;
 		fifo-depth = <0x10>;
-    reg = <0x0 0xf0e00000 0x0 0x1000>;
-    interrupts = <18 4>;
+		reg = <0x0 0xf0e00000 0x0 0x1000>;
+		interrupts = <18 4>;
 		cap-sd-highspeed;
-    interrupt-parent = <&plic0>;
+		interrupt-parent = <&plic0>;
 	};
 
-  smc0: smc at e0400000 {
-    compatible = "andestech,atfsmc020";
-    reg = <0x0 0xe0400000 0x0 0x1000>;
-  };
+	smc0: smc at e0400000 {
+		compatible = "andestech,atfsmc020";
+		reg = <0x0 0xe0400000 0x0 0x1000>;
+	};
 
-  nor at 0,0 {
-    compatible = "cfi-flash";
-    reg = <0x0 0x88000000 0x0 0x1000>;
-    bank-width = <2>;
-    device-width = <1>;
-  };
+	nor at 0,0 {
+		compatible = "cfi-flash";
+		reg = <0x0 0x88000000 0x0 0x1000>;
+		bank-width = <2>;
+		device-width = <1>;
+	};
 
 	spi: spi at f0b00000 {
 		compatible = "andestech,atcspi200";
-    reg = <0x0 0xf0b00000 0x0 0x1000>;
+		reg = <0x0 0xf0b00000 0x0 0x1000>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		num-cs = <1>;
 		clocks = <&spiclk>;
 		interrupts = <3 4>;
-    interrupt-parent = <&plic0>;
-			flash at 0 {
+		interrupt-parent = <&plic0>;
+
+		flash at 0 {
 			compatible = "spi-flash";
 			spi-max-frequency = <50000000>;
 			reg = <0>;
-- 
2.7.4

  parent reply	other threads:[~2018-09-11  4:54 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-11  4:54 [U-Boot] [RESEND PATCH v2 00/15] riscv: Add QEMU virt board support Bin Meng
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 01/15] riscv: kconfig: Normalize architecture name spelling Bin Meng
2018-09-16 20:43   ` Auer, Lukas
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA2F93D39@ATCPCS16.andestech.com>
2018-09-20  3:15     ` Rick Chen
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 02/15] riscv: Remove setup.h Bin Meng
2018-09-16 20:44   ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 03/15] riscv: bootm: Correct the 1st kernel argument to hart id Bin Meng
2018-09-16 20:45   ` Auer, Lukas
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA2F93D4E@ATCPCS16.andestech.com>
2018-09-20  3:17     ` Rick Chen
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 04/15] riscv: Remove mach type Bin Meng
2018-09-16 20:46   ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 05/15] riscv: Move the linker script to the CPU root directory Bin Meng
2018-09-16 20:47   ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 06/15] riscv: Fix coding style issues in the linker script Bin Meng
2018-09-16 20:49   ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 07/15] riscv: Explicitly pass -march and -mabi to the compiler Bin Meng
2018-09-16 20:51   ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 08/15] riscv: Add a helper routine to print CPU information Bin Meng
2018-09-16 20:54   ` Auer, Lukas
2018-09-17  4:55     ` Bin Meng
2018-09-17 21:59       ` Auer, Lukas
2018-09-18  8:53         ` Bin Meng
2018-09-18 10:53           ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 09/15] riscv: Remove CSR read/write defines in encoding.h Bin Meng
2018-09-16 20:55   ` Auer, Lukas
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA2F93D8B@ATCPCS16.andestech.com>
2018-09-20  3:20     ` Rick Chen
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 10/15] riscv: bootm: Pass mhartid CSR value to kernel Bin Meng
2018-09-16 20:55   ` Auer, Lukas
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA2F93D92@ATCPCS16.andestech.com>
2018-09-20  3:22     ` Rick Chen
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 11/15] riscv: Make start.S available for all targets Bin Meng
2018-09-16 20:56   ` Auer, Lukas
2018-09-11  4:54 ` Bin Meng [this message]
2018-09-16 20:57   ` [U-Boot] [RESEND PATCH v2 12/15] riscv: ae350: Clean up mixed tabs and spaces in the dts Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 13/15] riscv: kconfig: Select DM and OF_CONTROL Bin Meng
2018-09-16 20:58   ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 14/15] riscv: Add QEMU virt board support Bin Meng
2018-09-16 21:02   ` Auer, Lukas
2018-09-17  5:18     ` Bin Meng
2018-09-17 21:54       ` Auer, Lukas
2018-09-11  4:54 ` [U-Boot] [RESEND PATCH v2 15/15] riscv: Move do_reset() to a common place Bin Meng
2018-09-16 21:09   ` Auer, Lukas
2018-09-17  5:02     ` Bin Meng
2018-09-17 22:01       ` Auer, Lukas
2018-09-18  8:50         ` Bin Meng
2018-09-18 10:54           ` Auer, Lukas
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA2F93DD7@ATCPCS16.andestech.com>
2018-09-20  3:26     ` Rick Chen
2018-09-16 10:57 ` [U-Boot] [RESEND PATCH v2 00/15] riscv: Add QEMU virt board support Bin Meng
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA2F93D22@ATCPCS16.andestech.com>
2018-09-20  3:00     ` Rick Chen
2018-09-20  3:21       ` Bin Meng

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