From: Mike Looijmans <mike.looijmans@topic.nl> To: linux-fpga@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, michal.simek@xilinx.com, mdf@kernel.org, atull@kernel.org, git@xilinx.com, Mike Looijmans <mike.looijmans@topic.nl> Subject: [PATCH v2] zynq-fpga: Only route PR via PCAP when required Date: Wed, 24 Oct 2018 09:53:03 +0200 [thread overview] Message-ID: <1540367583-5413-1-git-send-email-mike.looijmans@topic.nl> (raw) In-Reply-To: <1540276279-2903-1-git-send-email-mike.looijmans@topic.nl> The Xilinx Zynq FPGA driver takes ownership of the PR interface, making it impossible to use the ICAP interface for partial reconfiguration. This patch changes the driver to only activate PR over PCAP while the device is actively being accessed by the driver for programming. This allows both PCAP and ICAP interfaces to be used for PR. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Reviewed-by: Moritz Fischer <mdf@kernel.org> --- v2: Move the register setting in between the clock enable/disable drivers/fpga/zynq-fpga.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c index 3110e00..ff3a427 100644 --- a/drivers/fpga/zynq-fpga.c +++ b/drivers/fpga/zynq-fpga.c @@ -501,6 +501,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, if (err) return err; + /* Release 'PR' control back to the ICAP */ + zynq_fpga_write(priv, CTRL_OFFSET, + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); + err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status, intr_status & IXR_PCFG_DONE_MASK, INIT_POLL_DELAY, -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: mike.looijmans@topic.nl (Mike Looijmans) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2] zynq-fpga: Only route PR via PCAP when required Date: Wed, 24 Oct 2018 09:53:03 +0200 [thread overview] Message-ID: <1540367583-5413-1-git-send-email-mike.looijmans@topic.nl> (raw) In-Reply-To: <1540276279-2903-1-git-send-email-mike.looijmans@topic.nl> The Xilinx Zynq FPGA driver takes ownership of the PR interface, making it impossible to use the ICAP interface for partial reconfiguration. This patch changes the driver to only activate PR over PCAP while the device is actively being accessed by the driver for programming. This allows both PCAP and ICAP interfaces to be used for PR. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Reviewed-by: Moritz Fischer <mdf@kernel.org> --- v2: Move the register setting in between the clock enable/disable drivers/fpga/zynq-fpga.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c index 3110e00..ff3a427 100644 --- a/drivers/fpga/zynq-fpga.c +++ b/drivers/fpga/zynq-fpga.c @@ -501,6 +501,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, if (err) return err; + /* Release 'PR' control back to the ICAP */ + zynq_fpga_write(priv, CTRL_OFFSET, + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); + err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status, intr_status & IXR_PCFG_DONE_MASK, INIT_POLL_DELAY, -- 1.9.1
next prev parent reply other threads:[~2018-10-24 7:53 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-10-23 6:31 [PATCH] zynq-fpga: Only route PR via PCAP when required Mike Looijmans 2018-10-23 6:31 ` Mike Looijmans 2018-10-23 9:01 ` Moritz Fischer 2018-10-23 9:01 ` Moritz Fischer 2018-10-23 10:53 ` Mike Looijmans 2018-10-23 10:53 ` Mike Looijmans 2018-10-23 10:53 ` Mike Looijmans 2018-10-23 11:04 ` Moritz Fischer 2018-10-23 11:04 ` Moritz Fischer 2018-10-23 11:04 ` Moritz Fischer 2018-10-26 7:54 ` Michal Simek 2018-10-26 7:54 ` Michal Simek 2018-10-26 7:54 ` Michal Simek 2018-10-26 17:04 ` Moritz Fischer 2018-10-26 17:04 ` Moritz Fischer 2018-10-24 7:53 ` Mike Looijmans [this message] 2018-10-24 7:53 ` [PATCH v2] " Mike Looijmans 2018-11-01 18:33 ` Alan Tull 2018-11-01 18:33 ` Alan Tull 2018-11-01 18:33 ` Alan Tull
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