From: Julien Thierry <julien.thierry@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, daniel.thompson@linaro.org, joel@joelfernandes.org, marc.zyngier@arm.com, christoffer.dall@arm.com, james.morse@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, mark.rutland@arm.com, Julien Thierry <julien.thierry@arm.com>, Ard Biesheuvel <ard.biesheuvel@linaro.org>, Oleg Nesterov <oleg@redhat.com> Subject: [PATCH v10 12/25] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking Date: Thu, 31 Jan 2019 14:58:50 +0000 [thread overview] Message-ID: <1548946743-38979-13-git-send-email-julien.thierry@arm.com> (raw) In-Reply-To: <1548946743-38979-1-git-send-email-julien.thierry@arm.com> Instead disabling interrupts by setting the PSR.I bit, use a priority higher than the one used for interrupts to mask them via PMR. When using PMR to disable interrupts, the value of PMR will be used instead of PSR.[DAIF] for the irqflags. Signed-off-by: Julien Thierry <julien.thierry@arm.com> Suggested-by: Daniel Thompson <daniel.thompson@linaro.org> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Oleg Nesterov <oleg@redhat.com> --- arch/arm64/include/asm/efi.h | 11 +++++ arch/arm64/include/asm/irqflags.h | 100 +++++++++++++++++++++++++++----------- 2 files changed, 83 insertions(+), 28 deletions(-) diff --git a/arch/arm64/include/asm/efi.h b/arch/arm64/include/asm/efi.h index 7ed3208..c9e9a69 100644 --- a/arch/arm64/include/asm/efi.h +++ b/arch/arm64/include/asm/efi.h @@ -44,6 +44,17 @@ #define ARCH_EFI_IRQ_FLAGS_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT) +/* + * Even when Linux uses IRQ priorities for IRQ disabling, EFI does not. + * And EFI shouldn't really play around with priority masking as it is not aware + * which priorities the OS has assigned to its interrupts. + */ +#define arch_efi_save_flags(state_flags) \ + ((void)((state_flags) = read_sysreg(daif))) + +#define arch_efi_restore_flags(state_flags) write_sysreg(state_flags, daif) + + /* arch specific definitions used by the stub code */ /* diff --git a/arch/arm64/include/asm/irqflags.h b/arch/arm64/include/asm/irqflags.h index 24692ed..d4597b2 100644 --- a/arch/arm64/include/asm/irqflags.h +++ b/arch/arm64/include/asm/irqflags.h @@ -18,7 +18,9 @@ #ifdef __KERNEL__ +#include <asm/alternative.h> #include <asm/ptrace.h> +#include <asm/sysreg.h> /* * Aarch64 has flags for masking: Debug, Asynchronous (serror), Interrupts and @@ -36,33 +38,27 @@ /* * CPU interrupt mask handling. */ -static inline unsigned long arch_local_irq_save(void) -{ - unsigned long flags; - asm volatile( - "mrs %0, daif // arch_local_irq_save\n" - "msr daifset, #2" - : "=r" (flags) - : - : "memory"); - return flags; -} - static inline void arch_local_irq_enable(void) { - asm volatile( - "msr daifclr, #2 // arch_local_irq_enable" - : + asm volatile(ALTERNATIVE( + "msr daifclr, #2 // arch_local_irq_enable\n" + "nop", + "msr_s " __stringify(SYS_ICC_PMR_EL1) ",%0\n" + "dsb sy", + ARM64_HAS_IRQ_PRIO_MASKING) : + : "r" (GIC_PRIO_IRQON) : "memory"); } static inline void arch_local_irq_disable(void) { - asm volatile( - "msr daifset, #2 // arch_local_irq_disable" - : + asm volatile(ALTERNATIVE( + "msr daifset, #2 // arch_local_irq_disable", + "msr_s " __stringify(SYS_ICC_PMR_EL1) ", %0", + ARM64_HAS_IRQ_PRIO_MASKING) : + : "r" (GIC_PRIO_IRQOFF) : "memory"); } @@ -71,12 +67,44 @@ static inline void arch_local_irq_disable(void) */ static inline unsigned long arch_local_save_flags(void) { + unsigned long daif_bits; unsigned long flags; - asm volatile( - "mrs %0, daif // arch_local_save_flags" - : "=r" (flags) - : + + daif_bits = read_sysreg(daif); + + /* + * The asm is logically equivalent to: + * + * if (system_uses_irq_prio_masking()) + * flags = (daif_bits & PSR_I_BIT) ? + * GIC_PRIO_IRQOFF : + * read_sysreg_s(SYS_ICC_PMR_EL1); + * else + * flags = daif_bits; + */ + asm volatile(ALTERNATIVE( + "mov %0, %1\n" + "nop\n" + "nop", + "mrs_s %0, " __stringify(SYS_ICC_PMR_EL1) "\n" + "ands %1, %1, " __stringify(PSR_I_BIT) "\n" + "csel %0, %0, %2, eq", + ARM64_HAS_IRQ_PRIO_MASKING) + : "=&r" (flags), "+r" (daif_bits) + : "r" (GIC_PRIO_IRQOFF) : "memory"); + + return flags; +} + +static inline unsigned long arch_local_irq_save(void) +{ + unsigned long flags; + + flags = arch_local_save_flags(); + + arch_local_irq_disable(); + return flags; } @@ -85,16 +113,32 @@ static inline unsigned long arch_local_save_flags(void) */ static inline void arch_local_irq_restore(unsigned long flags) { - asm volatile( - "msr daif, %0 // arch_local_irq_restore" - : - : "r" (flags) - : "memory"); + asm volatile(ALTERNATIVE( + "msr daif, %0\n" + "nop", + "msr_s " __stringify(SYS_ICC_PMR_EL1) ", %0\n" + "dsb sy", + ARM64_HAS_IRQ_PRIO_MASKING) + : "+r" (flags) + : + : "memory"); } static inline int arch_irqs_disabled_flags(unsigned long flags) { - return flags & PSR_I_BIT; + int res; + + asm volatile(ALTERNATIVE( + "and %w0, %w1, #" __stringify(PSR_I_BIT) "\n" + "nop", + "cmp %w1, #" __stringify(GIC_PRIO_IRQOFF) "\n" + "cset %w0, ls", + ARM64_HAS_IRQ_PRIO_MASKING) + : "=&r" (res) + : "r" ((int) flags) + : "memory"); + + return res; } #endif #endif -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: Julien Thierry <julien.thierry@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: mark.rutland@arm.com, daniel.thompson@linaro.org, Julien Thierry <julien.thierry@arm.com>, marc.zyngier@arm.com, catalin.marinas@arm.com, Ard Biesheuvel <ard.biesheuvel@linaro.org>, will.deacon@arm.com, linux-kernel@vger.kernel.org, christoffer.dall@arm.com, james.morse@arm.com, Oleg Nesterov <oleg@redhat.com>, joel@joelfernandes.org Subject: [PATCH v10 12/25] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking Date: Thu, 31 Jan 2019 14:58:50 +0000 [thread overview] Message-ID: <1548946743-38979-13-git-send-email-julien.thierry@arm.com> (raw) In-Reply-To: <1548946743-38979-1-git-send-email-julien.thierry@arm.com> Instead disabling interrupts by setting the PSR.I bit, use a priority higher than the one used for interrupts to mask them via PMR. When using PMR to disable interrupts, the value of PMR will be used instead of PSR.[DAIF] for the irqflags. Signed-off-by: Julien Thierry <julien.thierry@arm.com> Suggested-by: Daniel Thompson <daniel.thompson@linaro.org> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Oleg Nesterov <oleg@redhat.com> --- arch/arm64/include/asm/efi.h | 11 +++++ arch/arm64/include/asm/irqflags.h | 100 +++++++++++++++++++++++++++----------- 2 files changed, 83 insertions(+), 28 deletions(-) diff --git a/arch/arm64/include/asm/efi.h b/arch/arm64/include/asm/efi.h index 7ed3208..c9e9a69 100644 --- a/arch/arm64/include/asm/efi.h +++ b/arch/arm64/include/asm/efi.h @@ -44,6 +44,17 @@ #define ARCH_EFI_IRQ_FLAGS_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT) +/* + * Even when Linux uses IRQ priorities for IRQ disabling, EFI does not. + * And EFI shouldn't really play around with priority masking as it is not aware + * which priorities the OS has assigned to its interrupts. + */ +#define arch_efi_save_flags(state_flags) \ + ((void)((state_flags) = read_sysreg(daif))) + +#define arch_efi_restore_flags(state_flags) write_sysreg(state_flags, daif) + + /* arch specific definitions used by the stub code */ /* diff --git a/arch/arm64/include/asm/irqflags.h b/arch/arm64/include/asm/irqflags.h index 24692ed..d4597b2 100644 --- a/arch/arm64/include/asm/irqflags.h +++ b/arch/arm64/include/asm/irqflags.h @@ -18,7 +18,9 @@ #ifdef __KERNEL__ +#include <asm/alternative.h> #include <asm/ptrace.h> +#include <asm/sysreg.h> /* * Aarch64 has flags for masking: Debug, Asynchronous (serror), Interrupts and @@ -36,33 +38,27 @@ /* * CPU interrupt mask handling. */ -static inline unsigned long arch_local_irq_save(void) -{ - unsigned long flags; - asm volatile( - "mrs %0, daif // arch_local_irq_save\n" - "msr daifset, #2" - : "=r" (flags) - : - : "memory"); - return flags; -} - static inline void arch_local_irq_enable(void) { - asm volatile( - "msr daifclr, #2 // arch_local_irq_enable" - : + asm volatile(ALTERNATIVE( + "msr daifclr, #2 // arch_local_irq_enable\n" + "nop", + "msr_s " __stringify(SYS_ICC_PMR_EL1) ",%0\n" + "dsb sy", + ARM64_HAS_IRQ_PRIO_MASKING) : + : "r" (GIC_PRIO_IRQON) : "memory"); } static inline void arch_local_irq_disable(void) { - asm volatile( - "msr daifset, #2 // arch_local_irq_disable" - : + asm volatile(ALTERNATIVE( + "msr daifset, #2 // arch_local_irq_disable", + "msr_s " __stringify(SYS_ICC_PMR_EL1) ", %0", + ARM64_HAS_IRQ_PRIO_MASKING) : + : "r" (GIC_PRIO_IRQOFF) : "memory"); } @@ -71,12 +67,44 @@ static inline void arch_local_irq_disable(void) */ static inline unsigned long arch_local_save_flags(void) { + unsigned long daif_bits; unsigned long flags; - asm volatile( - "mrs %0, daif // arch_local_save_flags" - : "=r" (flags) - : + + daif_bits = read_sysreg(daif); + + /* + * The asm is logically equivalent to: + * + * if (system_uses_irq_prio_masking()) + * flags = (daif_bits & PSR_I_BIT) ? + * GIC_PRIO_IRQOFF : + * read_sysreg_s(SYS_ICC_PMR_EL1); + * else + * flags = daif_bits; + */ + asm volatile(ALTERNATIVE( + "mov %0, %1\n" + "nop\n" + "nop", + "mrs_s %0, " __stringify(SYS_ICC_PMR_EL1) "\n" + "ands %1, %1, " __stringify(PSR_I_BIT) "\n" + "csel %0, %0, %2, eq", + ARM64_HAS_IRQ_PRIO_MASKING) + : "=&r" (flags), "+r" (daif_bits) + : "r" (GIC_PRIO_IRQOFF) : "memory"); + + return flags; +} + +static inline unsigned long arch_local_irq_save(void) +{ + unsigned long flags; + + flags = arch_local_save_flags(); + + arch_local_irq_disable(); + return flags; } @@ -85,16 +113,32 @@ static inline unsigned long arch_local_save_flags(void) */ static inline void arch_local_irq_restore(unsigned long flags) { - asm volatile( - "msr daif, %0 // arch_local_irq_restore" - : - : "r" (flags) - : "memory"); + asm volatile(ALTERNATIVE( + "msr daif, %0\n" + "nop", + "msr_s " __stringify(SYS_ICC_PMR_EL1) ", %0\n" + "dsb sy", + ARM64_HAS_IRQ_PRIO_MASKING) + : "+r" (flags) + : + : "memory"); } static inline int arch_irqs_disabled_flags(unsigned long flags) { - return flags & PSR_I_BIT; + int res; + + asm volatile(ALTERNATIVE( + "and %w0, %w1, #" __stringify(PSR_I_BIT) "\n" + "nop", + "cmp %w1, #" __stringify(GIC_PRIO_IRQOFF) "\n" + "cset %w0, ls", + ARM64_HAS_IRQ_PRIO_MASKING) + : "=&r" (res) + : "r" ((int) flags) + : "memory"); + + return res; } #endif #endif -- 1.9.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-01-31 14:59 UTC|newest] Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-01-31 14:58 [PATCH v10 00/25] arm64: provide pseudo NMI with GICv3 Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 01/25] arm64: Fix HCR.TGE status for NMI contexts Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-02-02 14:38 ` Sasha Levin 2019-02-02 14:38 ` Sasha Levin 2019-01-31 14:58 ` [PATCH v10 02/25] arm64: Remove unused daif related functions/macros Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 03/25] arm64: cpufeature: Set SYSREG_GIC_CPUIF as a boot system feature Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 04/25] arm64: cpufeature: Add cpufeature for IRQ priority masking Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 05/25] arm/arm64: gic-v3: Add PMR and RPR accessors Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 06/25] irqchip/gic-v3: Switch to PMR masking before calling IRQ handler Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 07/25] arm64: ptrace: Provide definitions for PMR values Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 08/25] arm64: Make PMR part of task context Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 09/25] arm64: Unmask PMR before going idle Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 10/25] arm64: kvm: Unmask PMR before entering guest Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 11/25] efi: Let architectures decide the flags that should be saved/restored Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` Julien Thierry [this message] 2019-01-31 14:58 ` [PATCH v10 12/25] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking Julien Thierry 2019-02-08 4:35 ` Nathan Chancellor 2019-02-08 4:35 ` Nathan Chancellor 2019-02-08 9:36 ` Julien Thierry 2019-02-08 9:36 ` Julien Thierry 2019-02-08 16:00 ` Nathan Chancellor 2019-02-08 16:00 ` Nathan Chancellor 2019-02-08 16:16 ` Catalin Marinas 2019-02-08 16:16 ` Catalin Marinas 2019-01-31 14:58 ` [PATCH v10 13/25] arm64: daifflags: Include PMR in daifflags restore operations Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 14/25] arm64: alternative: Allow alternative status checking per cpufeature Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 15/25] arm64: alternative: Apply alternatives early in boot process Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 16/25] irqchip/gic-v3: Factor group0 detection into functions Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 17/25] arm64: Switch to PMR masking when starting CPUs Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 18/25] arm64: gic-v3: Implement arch support for priority masking Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 19/25] irqchip/gic-v3: Detect if GIC can support pseudo-NMIs Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 20/25] irqchip/gic-v3: Handle pseudo-NMIs Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 21/25] irqchip/gic-v3: Allow interrupts to be set as pseudo-NMI Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:59 ` [PATCH v10 22/25] arm64: Handle serror in NMI context Julien Thierry 2019-01-31 14:59 ` Julien Thierry 2019-01-31 14:59 ` [PATCH v10 23/25] arm64: Skip preemption when exiting an NMI Julien Thierry 2019-01-31 14:59 ` Julien Thierry 2019-01-31 14:59 ` [PATCH v10 24/25] arm64: Skip irqflags tracing for NMI in IRQs disabled context Julien Thierry 2019-01-31 14:59 ` Julien Thierry 2019-01-31 14:59 ` [PATCH v10 25/25] arm64: Enable the support of pseudo-NMIs Julien Thierry 2019-01-31 14:59 ` Julien Thierry 2019-02-06 10:27 ` [PATCH v10 00/25] arm64: provide pseudo NMI with GICv3 Catalin Marinas 2019-02-06 10:27 ` Catalin Marinas 2019-02-07 14:21 ` Daniel Thompson 2019-02-07 14:21 ` Daniel Thompson
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