From: Julien Thierry <julien.thierry@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, daniel.thompson@linaro.org, joel@joelfernandes.org, marc.zyngier@arm.com, christoffer.dall@arm.com, james.morse@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, mark.rutland@arm.com, Julien Thierry <julien.thierry@arm.com> Subject: [PATCH v10 17/25] arm64: Switch to PMR masking when starting CPUs Date: Thu, 31 Jan 2019 14:58:55 +0000 [thread overview] Message-ID: <1548946743-38979-18-git-send-email-julien.thierry@arm.com> (raw) In-Reply-To: <1548946743-38979-1-git-send-email-julien.thierry@arm.com> Once the boot CPU has been prepared or a new secondary CPU has been brought up, use ICC_PMR_EL1 to mask interrupts on that CPU and clear PSR.I bit. Since ICC_PMR_EL1 is initialized at CPU bringup, avoid overwriting it in the GICv3 driver. Signed-off-by: Julien Thierry <julien.thierry@arm.com> Suggested-by: Daniel Thompson <daniel.thompson@linaro.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> --- arch/arm64/kernel/smp.c | 26 ++++++++++++++++++++++++++ drivers/irqchip/irq-gic-v3.c | 8 +++++++- 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index a944edd..824de70 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -35,6 +35,7 @@ #include <linux/smp.h> #include <linux/seq_file.h> #include <linux/irq.h> +#include <linux/irqchip/arm-gic-v3.h> #include <linux/percpu.h> #include <linux/clockchips.h> #include <linux/completion.h> @@ -180,6 +181,24 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle) return ret; } +static void init_gic_priority_masking(void) +{ + u32 cpuflags; + + if (WARN_ON(!gic_enable_sre())) + return; + + cpuflags = read_sysreg(daif); + + WARN_ON(!(cpuflags & PSR_I_BIT)); + + gic_write_pmr(GIC_PRIO_IRQOFF); + + /* We can only unmask PSR.I if we can take aborts */ + if (!(cpuflags & PSR_A_BIT)) + write_sysreg(cpuflags & ~PSR_I_BIT, daif); +} + /* * This is the secondary CPU boot entry. We're using this CPUs * idle thread stack, but a set of temporary page tables. @@ -206,6 +225,9 @@ asmlinkage notrace void secondary_start_kernel(void) */ cpu_uninstall_idmap(); + if (system_uses_irq_prio_masking()) + init_gic_priority_masking(); + preempt_disable(); trace_hardirqs_off(); @@ -426,6 +448,10 @@ void __init smp_prepare_boot_cpu(void) * and/or scheduling is enabled. */ apply_boot_alternatives(); + + /* Conditionally switch to GIC PMR for interrupt masking */ + if (system_uses_irq_prio_masking()) + init_gic_priority_masking(); } static u64 __init of_get_cpu_mpidr(struct device_node *dn) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index da547e0..5a703ae 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -415,6 +415,9 @@ static u32 gic_get_pribits(void) static bool gic_has_group0(void) { u32 val; + u32 old_pmr; + + old_pmr = gic_read_pmr(); /* * Let's find out if Group0 is under control of EL3 or not by @@ -430,6 +433,8 @@ static bool gic_has_group0(void) gic_write_pmr(BIT(8 - gic_get_pribits())); val = gic_read_pmr(); + gic_write_pmr(old_pmr); + return val != 0; } @@ -591,7 +596,8 @@ static void gic_cpu_sys_reg_init(void) group0 = gic_has_group0(); /* Set priority mask register */ - write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1); + if (!gic_prio_masking_enabled()) + write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1); /* * Some firmwares hand over to the kernel with the BPR changed from -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: Julien Thierry <julien.thierry@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: mark.rutland@arm.com, daniel.thompson@linaro.org, Julien Thierry <julien.thierry@arm.com>, marc.zyngier@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, christoffer.dall@arm.com, james.morse@arm.com, joel@joelfernandes.org Subject: [PATCH v10 17/25] arm64: Switch to PMR masking when starting CPUs Date: Thu, 31 Jan 2019 14:58:55 +0000 [thread overview] Message-ID: <1548946743-38979-18-git-send-email-julien.thierry@arm.com> (raw) In-Reply-To: <1548946743-38979-1-git-send-email-julien.thierry@arm.com> Once the boot CPU has been prepared or a new secondary CPU has been brought up, use ICC_PMR_EL1 to mask interrupts on that CPU and clear PSR.I bit. Since ICC_PMR_EL1 is initialized at CPU bringup, avoid overwriting it in the GICv3 driver. Signed-off-by: Julien Thierry <julien.thierry@arm.com> Suggested-by: Daniel Thompson <daniel.thompson@linaro.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> --- arch/arm64/kernel/smp.c | 26 ++++++++++++++++++++++++++ drivers/irqchip/irq-gic-v3.c | 8 +++++++- 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index a944edd..824de70 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -35,6 +35,7 @@ #include <linux/smp.h> #include <linux/seq_file.h> #include <linux/irq.h> +#include <linux/irqchip/arm-gic-v3.h> #include <linux/percpu.h> #include <linux/clockchips.h> #include <linux/completion.h> @@ -180,6 +181,24 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle) return ret; } +static void init_gic_priority_masking(void) +{ + u32 cpuflags; + + if (WARN_ON(!gic_enable_sre())) + return; + + cpuflags = read_sysreg(daif); + + WARN_ON(!(cpuflags & PSR_I_BIT)); + + gic_write_pmr(GIC_PRIO_IRQOFF); + + /* We can only unmask PSR.I if we can take aborts */ + if (!(cpuflags & PSR_A_BIT)) + write_sysreg(cpuflags & ~PSR_I_BIT, daif); +} + /* * This is the secondary CPU boot entry. We're using this CPUs * idle thread stack, but a set of temporary page tables. @@ -206,6 +225,9 @@ asmlinkage notrace void secondary_start_kernel(void) */ cpu_uninstall_idmap(); + if (system_uses_irq_prio_masking()) + init_gic_priority_masking(); + preempt_disable(); trace_hardirqs_off(); @@ -426,6 +448,10 @@ void __init smp_prepare_boot_cpu(void) * and/or scheduling is enabled. */ apply_boot_alternatives(); + + /* Conditionally switch to GIC PMR for interrupt masking */ + if (system_uses_irq_prio_masking()) + init_gic_priority_masking(); } static u64 __init of_get_cpu_mpidr(struct device_node *dn) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index da547e0..5a703ae 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -415,6 +415,9 @@ static u32 gic_get_pribits(void) static bool gic_has_group0(void) { u32 val; + u32 old_pmr; + + old_pmr = gic_read_pmr(); /* * Let's find out if Group0 is under control of EL3 or not by @@ -430,6 +433,8 @@ static bool gic_has_group0(void) gic_write_pmr(BIT(8 - gic_get_pribits())); val = gic_read_pmr(); + gic_write_pmr(old_pmr); + return val != 0; } @@ -591,7 +596,8 @@ static void gic_cpu_sys_reg_init(void) group0 = gic_has_group0(); /* Set priority mask register */ - write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1); + if (!gic_prio_masking_enabled()) + write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1); /* * Some firmwares hand over to the kernel with the BPR changed from -- 1.9.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-01-31 15:00 UTC|newest] Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-01-31 14:58 [PATCH v10 00/25] arm64: provide pseudo NMI with GICv3 Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 01/25] arm64: Fix HCR.TGE status for NMI contexts Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-02-02 14:38 ` Sasha Levin 2019-02-02 14:38 ` Sasha Levin 2019-01-31 14:58 ` [PATCH v10 02/25] arm64: Remove unused daif related functions/macros Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 03/25] arm64: cpufeature: Set SYSREG_GIC_CPUIF as a boot system feature Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 04/25] arm64: cpufeature: Add cpufeature for IRQ priority masking Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 05/25] arm/arm64: gic-v3: Add PMR and RPR accessors Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 06/25] irqchip/gic-v3: Switch to PMR masking before calling IRQ handler Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 07/25] arm64: ptrace: Provide definitions for PMR values Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 08/25] arm64: Make PMR part of task context Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 09/25] arm64: Unmask PMR before going idle Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 10/25] arm64: kvm: Unmask PMR before entering guest Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 11/25] efi: Let architectures decide the flags that should be saved/restored Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 12/25] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-02-08 4:35 ` Nathan Chancellor 2019-02-08 4:35 ` Nathan Chancellor 2019-02-08 9:36 ` Julien Thierry 2019-02-08 9:36 ` Julien Thierry 2019-02-08 16:00 ` Nathan Chancellor 2019-02-08 16:00 ` Nathan Chancellor 2019-02-08 16:16 ` Catalin Marinas 2019-02-08 16:16 ` Catalin Marinas 2019-01-31 14:58 ` [PATCH v10 13/25] arm64: daifflags: Include PMR in daifflags restore operations Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 14/25] arm64: alternative: Allow alternative status checking per cpufeature Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 15/25] arm64: alternative: Apply alternatives early in boot process Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 16/25] irqchip/gic-v3: Factor group0 detection into functions Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` Julien Thierry [this message] 2019-01-31 14:58 ` [PATCH v10 17/25] arm64: Switch to PMR masking when starting CPUs Julien Thierry 2019-01-31 14:58 ` [PATCH v10 18/25] arm64: gic-v3: Implement arch support for priority masking Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 19/25] irqchip/gic-v3: Detect if GIC can support pseudo-NMIs Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 20/25] irqchip/gic-v3: Handle pseudo-NMIs Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:58 ` [PATCH v10 21/25] irqchip/gic-v3: Allow interrupts to be set as pseudo-NMI Julien Thierry 2019-01-31 14:58 ` Julien Thierry 2019-01-31 14:59 ` [PATCH v10 22/25] arm64: Handle serror in NMI context Julien Thierry 2019-01-31 14:59 ` Julien Thierry 2019-01-31 14:59 ` [PATCH v10 23/25] arm64: Skip preemption when exiting an NMI Julien Thierry 2019-01-31 14:59 ` Julien Thierry 2019-01-31 14:59 ` [PATCH v10 24/25] arm64: Skip irqflags tracing for NMI in IRQs disabled context Julien Thierry 2019-01-31 14:59 ` Julien Thierry 2019-01-31 14:59 ` [PATCH v10 25/25] arm64: Enable the support of pseudo-NMIs Julien Thierry 2019-01-31 14:59 ` Julien Thierry 2019-02-06 10:27 ` [PATCH v10 00/25] arm64: provide pseudo NMI with GICv3 Catalin Marinas 2019-02-06 10:27 ` Catalin Marinas 2019-02-07 14:21 ` Daniel Thompson 2019-02-07 14:21 ` Daniel Thompson
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