[PATCH v3 0/3] Support 64 bpp half float formats

[PATCH v3 0/3] Support 64 bpp half float formats

[Kevin Strasser]

This series defines new formats and adds implementation to the i915 driver.
Since posting v1 I have removed the pixel normalize property, as it's not needed
for basic functionality. Also, I have been working on adding support to
userspace, but we can't land any patches until drm_fourcc.h has been updated
here.

I have submitted a series to Mesa to make use of the RGBA ordered formats:
  https://patchwork.freedesktop.org/series/54759/

My igt branch is reworked to drop usage of pixel normalize and includes use
of f16c intrinsics to speed up conversion:
  https://gitlab.freedesktop.org/strassek/igt-gpu-tools/commits/fp16

I also have a libdrm branch with fp16 coverage added to modetest:
  https://gitlab.freedesktop.org/strassek/drm/commits/fp16

To serve as a smoke test of the whole stack I have a modified version of
kmscube:
  https://gitlab.freedesktop.org/strassek/kmscube/commits/fp16

Kevin Strasser (3):
  drm/fourcc: Add 64 bpp half float formats
  drm/i915: Refactor icl_is_hdr_plane
  drm/i915/icl: Implement half float formats

 drivers/gpu/drm/drm_fourcc.c         |  4 ++
 drivers/gpu/drm/i915/intel_atomic.c  |  4 +-
 drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++-
 drivers/gpu/drm/i915/intel_drv.h     |  7 ++--
 drivers/gpu/drm/i915/intel_sprite.c  | 73 +++++++++++++++++++++++++++++++-----
 include/uapi/drm/drm_fourcc.h        | 11 ++++++
 6 files changed, 111 insertions(+), 15 deletions(-)

-- 
2.7.4

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[PATCH v3 1/3] drm/fourcc: Add 64 bpp half float formats

[Kevin Strasser]

Add 64 bpp 16:16:16:16 half float pixel formats. Each 16 bit component is
formatted in IEEE-754 half-precision float (binary16) 1:5:10
MSb-sign:exponent:fraction form.

This patch attempts to address the feedback provided when 2 of these
formats were previosly proposed:
  https://patchwork.kernel.org/patch/10072545/

v2:
- Fixed cpp (Ville)
- Added detail pixel formatting (Ville)
- Ordered formats in header (Ville)

Cc: Tina Zhang <tina.zhang@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/drm_fourcc.c  |  4 ++++
 include/uapi/drm/drm_fourcc.h | 11 +++++++++++
 2 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index d90ee03..c866452 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -198,6 +198,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
 		{ .format = DRM_FORMAT_ABGR8888,	.depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
 		{ .format = DRM_FORMAT_RGBA8888,	.depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
 		{ .format = DRM_FORMAT_BGRA8888,	.depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
+		{ .format = DRM_FORMAT_XRGB16161616F,	.depth = 48, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
+		{ .format = DRM_FORMAT_XBGR16161616F,	.depth = 48, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
+		{ .format = DRM_FORMAT_ARGB16161616F,	.depth = 64, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
+		{ .format = DRM_FORMAT_ABGR16161616F,	.depth = 64, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
 		{ .format = DRM_FORMAT_RGB888_A8,	.depth = 32, .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
 		{ .format = DRM_FORMAT_BGR888_A8,	.depth = 32, .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
 		{ .format = DRM_FORMAT_XRGB8888_A8,	.depth = 32, .num_planes = 2, .cpp = { 4, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 93a341d..d323c73 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -144,6 +144,17 @@ extern "C" {
 #define DRM_FORMAT_RGBA1010102	fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
 #define DRM_FORMAT_BGRA1010102	fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
 
+/*
+ * Floating point 64bpp RGB
+ * IEEE 754-2008 binary16 half-precision float
+ * [15:0] sign:exponent:mantissa 1:5:10
+ */
+#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
+#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
+
+#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
+#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
+
 /* packed YCbCr */
 #define DRM_FORMAT_YUYV		fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
 #define DRM_FORMAT_YVYU		fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
-- 
2.7.4

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[PATCH v3 2/3] drm/i915: Refactor icl_is_hdr_plane

[Kevin Strasser]

Change the api in order to enable callers that can't supply a valid
intel_plane pointer, as would be the case prior to calling
drm_universal_plane_init.

Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
---
 drivers/gpu/drm/i915/intel_atomic.c  | 4 +++-
 drivers/gpu/drm/i915/intel_display.c | 5 +++--
 drivers/gpu/drm/i915/intel_drv.h     | 7 ++++---
 drivers/gpu/drm/i915/intel_sprite.c  | 6 +++---
 4 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index 16263ad..7f824fd 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -210,6 +210,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
 				      int *scaler_id)
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
+	struct intel_plane *intel_plane;
 	int j;
 	u32 mode;
 
@@ -232,10 +233,11 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
 	if (plane_state && plane_state->base.fb &&
 	    plane_state->base.fb->format->is_yuv &&
 	    plane_state->base.fb->format->num_planes > 1) {
+		intel_plane = to_intel_plane(plane_state->base.plane);
 		if (IS_GEN(dev_priv, 9) &&
 		    !IS_GEMINILAKE(dev_priv)) {
 			mode = SKL_PS_SCALER_MODE_NV12;
-		} else if (icl_is_hdr_plane(to_intel_plane(plane_state->base.plane))) {
+		} else if (icl_is_hdr_plane(dev_priv, intel_plane->id)) {
 			/*
 			 * On gen11+'s HDR planes we only use the scaler for
 			 * scaling. They have a dedicated chroma upsampler, so
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4d5ec92..2d9639d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3726,7 +3726,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
 	plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
 	plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
 
-	if (fb->format->is_yuv && !icl_is_hdr_plane(plane)) {
+	if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
 		if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
 			plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
 		else
@@ -5052,13 +5052,14 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 {
 	struct intel_plane *intel_plane =
 		to_intel_plane(plane_state->base.plane);
+	struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
 	struct drm_framebuffer *fb = plane_state->base.fb;
 	int ret;
 	bool force_detach = !fb || !plane_state->base.visible;
 	bool need_scaler = false;
 
 	/* Pre-gen11 and SDR planes always need a scaler for planar formats. */
-	if (!icl_is_hdr_plane(intel_plane) &&
+	if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
 	    fb && fb->format->format == DRM_FORMAT_NV12)
 		need_scaler = true;
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 90ba543..154901f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2313,12 +2313,13 @@ static inline bool icl_is_nv12_y_plane(enum plane_id id)
 	return false;
 }
 
-static inline bool icl_is_hdr_plane(struct intel_plane *plane)
+static inline bool icl_is_hdr_plane(struct drm_i915_private *dev_priv,
+				    enum plane_id id)
 {
-	if (INTEL_GEN(to_i915(plane->base.dev)) < 11)
+	if (INTEL_GEN(dev_priv) < 11)
 		return false;
 
-	return plane->id < PLANE_SPRITE2;
+	return id < PLANE_SPRITE2;
 }
 
 /* intel_tv.c */
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index cd42e81..10b37e8 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -336,7 +336,7 @@ skl_program_scaler(struct intel_plane *plane,
 
 	/* TODO: handle sub-pixel coordinates */
 	if (plane_state->base.fb->format->format == DRM_FORMAT_NV12 &&
-	    !icl_is_hdr_plane(plane)) {
+	    !icl_is_hdr_plane(dev_priv, plane->id)) {
 		y_hphase = skl_scaler_calc_phase(1, hscale, false);
 		y_vphase = skl_scaler_calc_phase(1, vscale, false);
 
@@ -511,7 +511,7 @@ skl_program_plane(struct intel_plane *plane,
 	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
 		      (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
 
-	if (icl_is_hdr_plane(plane)) {
+	if (icl_is_hdr_plane(dev_priv, plane_id)) {
 		u32 cus_ctl = 0;
 
 		if (linked) {
@@ -536,7 +536,7 @@ skl_program_plane(struct intel_plane *plane,
 		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
 			      plane_state->color_ctl);
 
-	if (fb->format->is_yuv && icl_is_hdr_plane(plane))
+	if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
 		icl_program_input_csc(plane, crtc_state, plane_state);
 
 	skl_write_plane_wm(plane, crtc_state);
-- 
2.7.4

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Re: [PATCH v3 2/3] drm/i915: Refactor icl_is_hdr_plane

[Ville Syrjälä]

On Tue, Feb 05, 2019 at 07:29:21PM -0800, Kevin Strasser wrote:
> Change the api in order to enable callers that can't supply a valid
> intel_plane pointer, as would be the case prior to calling
> drm_universal_plane_init.
> 
> Cc: Uma Shankar <uma.shankar@intel.com>
> Cc: Shashank Sharma <shashank.sharma@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: David Airlie <airlied@linux.ie>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_atomic.c  | 4 +++-
>  drivers/gpu/drm/i915/intel_display.c | 5 +++--
>  drivers/gpu/drm/i915/intel_drv.h     | 7 ++++---
>  drivers/gpu/drm/i915/intel_sprite.c  | 6 +++---
>  4 files changed, 13 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
> index 16263ad..7f824fd 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -210,6 +210,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
>  				      int *scaler_id)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> +	struct intel_plane *intel_plane;

s/intel_plane/plane/ here please. I'm trying to make our variable
naming to be more consistent. Still ways to go as we can see from
the later hunks, but at least new code should use consistent names.

Also the declaration can be moved into the if block itself.

>  	int j;
>  	u32 mode;
>  
> @@ -232,10 +233,11 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
>  	if (plane_state && plane_state->base.fb &&
>  	    plane_state->base.fb->format->is_yuv &&
>  	    plane_state->base.fb->format->num_planes > 1) {
> +		intel_plane = to_intel_plane(plane_state->base.plane);
>  		if (IS_GEN(dev_priv, 9) &&
>  		    !IS_GEMINILAKE(dev_priv)) {
>  			mode = SKL_PS_SCALER_MODE_NV12;
> -		} else if (icl_is_hdr_plane(to_intel_plane(plane_state->base.plane))) {
> +		} else if (icl_is_hdr_plane(dev_priv, intel_plane->id)) {
>  			/*
>  			 * On gen11+'s HDR planes we only use the scaler for
>  			 * scaling. They have a dedicated chroma upsampler, so
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4d5ec92..2d9639d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3726,7 +3726,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
>  	plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
>  	plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
>  
> -	if (fb->format->is_yuv && !icl_is_hdr_plane(plane)) {
> +	if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
>  		if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
>  			plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
>  		else
> @@ -5052,13 +5052,14 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
>  {
>  	struct intel_plane *intel_plane =
>  		to_intel_plane(plane_state->base.plane);
> +	struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
>  	struct drm_framebuffer *fb = plane_state->base.fb;
>  	int ret;
>  	bool force_detach = !fb || !plane_state->base.visible;
>  	bool need_scaler = false;
>  
>  	/* Pre-gen11 and SDR planes always need a scaler for planar formats. */
> -	if (!icl_is_hdr_plane(intel_plane) &&
> +	if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
>  	    fb && fb->format->format == DRM_FORMAT_NV12)
>  		need_scaler = true;
>  
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 90ba543..154901f 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -2313,12 +2313,13 @@ static inline bool icl_is_nv12_y_plane(enum plane_id id)
>  	return false;
>  }
>  
> -static inline bool icl_is_hdr_plane(struct intel_plane *plane)
> +static inline bool icl_is_hdr_plane(struct drm_i915_private *dev_priv,
> +				    enum plane_id id)

s/id/plane_id/ please. Again, going for consistency.

With those this is
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  {
> -	if (INTEL_GEN(to_i915(plane->base.dev)) < 11)
> +	if (INTEL_GEN(dev_priv) < 11)
>  		return false;
>  
> -	return plane->id < PLANE_SPRITE2;
> +	return id < PLANE_SPRITE2;
>  }
>  
>  /* intel_tv.c */
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index cd42e81..10b37e8 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -336,7 +336,7 @@ skl_program_scaler(struct intel_plane *plane,
>  
>  	/* TODO: handle sub-pixel coordinates */
>  	if (plane_state->base.fb->format->format == DRM_FORMAT_NV12 &&
> -	    !icl_is_hdr_plane(plane)) {
> +	    !icl_is_hdr_plane(dev_priv, plane->id)) {
>  		y_hphase = skl_scaler_calc_phase(1, hscale, false);
>  		y_vphase = skl_scaler_calc_phase(1, vscale, false);
>  
> @@ -511,7 +511,7 @@ skl_program_plane(struct intel_plane *plane,
>  	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
>  		      (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
>  
> -	if (icl_is_hdr_plane(plane)) {
> +	if (icl_is_hdr_plane(dev_priv, plane_id)) {
>  		u32 cus_ctl = 0;
>  
>  		if (linked) {
> @@ -536,7 +536,7 @@ skl_program_plane(struct intel_plane *plane,
>  		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
>  			      plane_state->color_ctl);
>  
> -	if (fb->format->is_yuv && icl_is_hdr_plane(plane))
> +	if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
>  		icl_program_input_csc(plane, crtc_state, plane_state);
>  
>  	skl_write_plane_wm(plane, crtc_state);
> -- 
> 2.7.4

-- 
Ville Syrjälä
Intel
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[PATCH v3 3/3] drm/i915/icl: Implement half float formats

[Kevin Strasser]

64 bpp half float formats are supported on hdr planes only and are subject
to the following restrictions:
  * 90/270 rotation not supported
  * Yf Tiling not supported
  * Frame Buffer Compression not supported
  * Color Keying not supported

v2:
- Drop handling pixel normalize register
- Don't use icl_is_hdr_plane too early

v3:
- Use refactored icl_is_hdr_plane (Ville)
- Use u32 instead of uint32_t (Ville)

Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 22 ++++++++++++
 drivers/gpu/drm/i915/intel_sprite.c  | 67 ++++++++++++++++++++++++++++++++----
 2 files changed, 83 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2d9639d..1124502 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2668,6 +2668,18 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
 		return DRM_FORMAT_RGB565;
 	case PLANE_CTL_FORMAT_NV12:
 		return DRM_FORMAT_NV12;
+	case PLANE_CTL_FORMAT_XRGB_16161616F:
+		if (rgb_order) {
+			if (alpha)
+				return DRM_FORMAT_ABGR16161616F;
+			else
+				return DRM_FORMAT_XBGR16161616F;
+		} else {
+			if (alpha)
+				return DRM_FORMAT_ARGB16161616F;
+			else
+				return DRM_FORMAT_XRGB16161616F;
+		}
 	default:
 	case PLANE_CTL_FORMAT_XRGB_8888:
 		if (rgb_order) {
@@ -3566,6 +3578,12 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
 		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
 	case DRM_FORMAT_NV12:
 		return PLANE_CTL_FORMAT_NV12;
+	case DRM_FORMAT_XBGR16161616F:
+	case DRM_FORMAT_ABGR16161616F:
+		return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
+	case DRM_FORMAT_XRGB16161616F:
+	case DRM_FORMAT_ARGB16161616F:
+		return PLANE_CTL_FORMAT_XRGB_16161616F;
 	default:
 		MISSING_CASE(pixel_format);
 	}
@@ -5097,6 +5115,10 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
 	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_XBGR16161616F:
+	case DRM_FORMAT_ABGR16161616F:
+	case DRM_FORMAT_XRGB16161616F:
+	case DRM_FORMAT_ARGB16161616F:
 		break;
 	default:
 		DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 10b37e8..55ee677 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1450,8 +1450,6 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 		/*
 		 * 90/270 is not allowed with RGB64 16:16:16:16 and
 		 * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards.
-		 * TBD: Add RGB64 case once its added in supported format
-		 * list.
 		 */
 		switch (fb->format->format) {
 		case DRM_FORMAT_RGB565:
@@ -1459,6 +1457,10 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 				break;
 			/* fall through */
 		case DRM_FORMAT_C8:
+		case DRM_FORMAT_XRGB16161616F:
+		case DRM_FORMAT_XBGR16161616F:
+		case DRM_FORMAT_ARGB16161616F:
+		case DRM_FORMAT_ABGR16161616F:
 			DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
 				      drm_get_format_name(fb->format->format,
 							  &format_name));
@@ -1774,6 +1776,45 @@ static const u32 skl_planar_formats[] = {
 	DRM_FORMAT_NV12,
 };
 
+static const u32 icl_hdr_plane_formats[] = {
+	DRM_FORMAT_C8,
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_XRGB2101010,
+	DRM_FORMAT_XBGR2101010,
+	DRM_FORMAT_XRGB16161616F,
+	DRM_FORMAT_XBGR16161616F,
+	DRM_FORMAT_ARGB16161616F,
+	DRM_FORMAT_ABGR16161616F,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+};
+
+static const u32 icl_hdr_planar_formats[] = {
+	DRM_FORMAT_C8,
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_XRGB2101010,
+	DRM_FORMAT_XBGR2101010,
+	DRM_FORMAT_XRGB16161616F,
+	DRM_FORMAT_XBGR16161616F,
+	DRM_FORMAT_ARGB16161616F,
+	DRM_FORMAT_ABGR16161616F,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+	DRM_FORMAT_NV12,
+};
+
 static const u64 skl_plane_format_modifiers_noccs[] = {
 	I915_FORMAT_MOD_Yf_TILED,
 	I915_FORMAT_MOD_Y_TILED,
@@ -1917,6 +1958,10 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
 			return true;
 		/* fall through */
 	case DRM_FORMAT_C8:
+	case DRM_FORMAT_XBGR16161616F:
+	case DRM_FORMAT_ABGR16161616F:
+	case DRM_FORMAT_XRGB16161616F:
+	case DRM_FORMAT_ARGB16161616F:
 		if (modifier == DRM_FORMAT_MOD_LINEAR ||
 		    modifier == I915_FORMAT_MOD_X_TILED ||
 		    modifier == I915_FORMAT_MOD_Y_TILED)
@@ -2053,11 +2098,21 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 		plane->update_slave = icl_update_slave;
 
 	if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
-		formats = skl_planar_formats;
-		num_formats = ARRAY_SIZE(skl_planar_formats);
+		if (icl_is_hdr_plane(dev_priv, plane_id)) {
+			formats = icl_hdr_planar_formats;
+			num_formats = ARRAY_SIZE(icl_hdr_planar_formats);
+		} else {
+			formats = skl_planar_formats;
+			num_formats = ARRAY_SIZE(skl_planar_formats);
+		}
 	} else {
-		formats = skl_plane_formats;
-		num_formats = ARRAY_SIZE(skl_plane_formats);
+		if (icl_is_hdr_plane(dev_priv, plane_id)) {
+			formats = icl_hdr_plane_formats;
+			num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
+		} else {
+			formats = skl_plane_formats;
+			num_formats = ARRAY_SIZE(skl_plane_formats);
+		}
 	}
 
 	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
-- 
2.7.4

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Re: [PATCH v3 3/3] drm/i915/icl: Implement half float formats

[Ville Syrjälä]

On Tue, Feb 05, 2019 at 07:29:22PM -0800, Kevin Strasser wrote:
> 64 bpp half float formats are supported on hdr planes only and are subject
> to the following restrictions:
>   * 90/270 rotation not supported
>   * Yf Tiling not supported
>   * Frame Buffer Compression not supported
>   * Color Keying not supported
> 
> v2:
> - Drop handling pixel normalize register
> - Don't use icl_is_hdr_plane too early
> 
> v3:
> - Use refactored icl_is_hdr_plane (Ville)
> - Use u32 instead of uint32_t (Ville)
> 
> Cc: Uma Shankar <uma.shankar@intel.com>
> Cc: Shashank Sharma <shashank.sharma@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: David Airlie <airlied@linux.ie>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 22 ++++++++++++
>  drivers/gpu/drm/i915/intel_sprite.c  | 67 ++++++++++++++++++++++++++++++++----
>  2 files changed, 83 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2d9639d..1124502 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2668,6 +2668,18 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
>  		return DRM_FORMAT_RGB565;
>  	case PLANE_CTL_FORMAT_NV12:
>  		return DRM_FORMAT_NV12;
> +	case PLANE_CTL_FORMAT_XRGB_16161616F:
> +		if (rgb_order) {
> +			if (alpha)
> +				return DRM_FORMAT_ABGR16161616F;
> +			else
> +				return DRM_FORMAT_XBGR16161616F;
> +		} else {
> +			if (alpha)
> +				return DRM_FORMAT_ARGB16161616F;
> +			else
> +				return DRM_FORMAT_XRGB16161616F;
> +		}
>  	default:
>  	case PLANE_CTL_FORMAT_XRGB_8888:
>  		if (rgb_order) {
> @@ -3566,6 +3578,12 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
>  		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
>  	case DRM_FORMAT_NV12:
>  		return PLANE_CTL_FORMAT_NV12;
> +	case DRM_FORMAT_XBGR16161616F:
> +	case DRM_FORMAT_ABGR16161616F:
> +		return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
> +	case DRM_FORMAT_XRGB16161616F:
> +	case DRM_FORMAT_ARGB16161616F:
> +		return PLANE_CTL_FORMAT_XRGB_16161616F;
>  	default:
>  		MISSING_CASE(pixel_format);
>  	}
> @@ -5097,6 +5115,10 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
>  	case DRM_FORMAT_UYVY:
>  	case DRM_FORMAT_VYUY:
>  	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_XBGR16161616F:
> +	case DRM_FORMAT_ABGR16161616F:
> +	case DRM_FORMAT_XRGB16161616F:
> +	case DRM_FORMAT_ARGB16161616F:
>  		break;
>  	default:
>  		DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 10b37e8..55ee677 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1450,8 +1450,6 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
>  		/*
>  		 * 90/270 is not allowed with RGB64 16:16:16:16 and
>  		 * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards.
> -		 * TBD: Add RGB64 case once its added in supported format
> -		 * list.
>  		 */
>  		switch (fb->format->format) {
>  		case DRM_FORMAT_RGB565:
> @@ -1459,6 +1457,10 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
>  				break;
>  			/* fall through */
>  		case DRM_FORMAT_C8:
> +		case DRM_FORMAT_XRGB16161616F:
> +		case DRM_FORMAT_XBGR16161616F:
> +		case DRM_FORMAT_ARGB16161616F:
> +		case DRM_FORMAT_ABGR16161616F:
>  			DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
>  				      drm_get_format_name(fb->format->format,
>  							  &format_name));
> @@ -1774,6 +1776,45 @@ static const u32 skl_planar_formats[] = {
>  	DRM_FORMAT_NV12,
>  };
>  
> +static const u32 icl_hdr_plane_formats[] = {
> +	DRM_FORMAT_C8,
> +	DRM_FORMAT_RGB565,
> +	DRM_FORMAT_XRGB8888,
> +	DRM_FORMAT_XBGR8888,
> +	DRM_FORMAT_ARGB8888,
> +	DRM_FORMAT_ABGR8888,
> +	DRM_FORMAT_XRGB2101010,
> +	DRM_FORMAT_XBGR2101010,
> +	DRM_FORMAT_XRGB16161616F,
> +	DRM_FORMAT_XBGR16161616F,
> +	DRM_FORMAT_ARGB16161616F,
> +	DRM_FORMAT_ABGR16161616F,
> +	DRM_FORMAT_YUYV,
> +	DRM_FORMAT_YVYU,
> +	DRM_FORMAT_UYVY,
> +	DRM_FORMAT_VYUY,
> +};
> +
> +static const u32 icl_hdr_planar_formats[] = {
> +	DRM_FORMAT_C8,
> +	DRM_FORMAT_RGB565,
> +	DRM_FORMAT_XRGB8888,
> +	DRM_FORMAT_XBGR8888,
> +	DRM_FORMAT_ARGB8888,
> +	DRM_FORMAT_ABGR8888,
> +	DRM_FORMAT_XRGB2101010,
> +	DRM_FORMAT_XBGR2101010,
> +	DRM_FORMAT_XRGB16161616F,
> +	DRM_FORMAT_XBGR16161616F,
> +	DRM_FORMAT_ARGB16161616F,
> +	DRM_FORMAT_ABGR16161616F,
> +	DRM_FORMAT_YUYV,
> +	DRM_FORMAT_YVYU,
> +	DRM_FORMAT_UYVY,
> +	DRM_FORMAT_VYUY,
> +	DRM_FORMAT_NV12,
> +};
> +
>  static const u64 skl_plane_format_modifiers_noccs[] = {
>  	I915_FORMAT_MOD_Yf_TILED,
>  	I915_FORMAT_MOD_Y_TILED,
> @@ -1917,6 +1958,10 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
>  			return true;
>  		/* fall through */
>  	case DRM_FORMAT_C8:
> +	case DRM_FORMAT_XBGR16161616F:
> +	case DRM_FORMAT_ABGR16161616F:
> +	case DRM_FORMAT_XRGB16161616F:
> +	case DRM_FORMAT_ARGB16161616F:
>  		if (modifier == DRM_FORMAT_MOD_LINEAR ||
>  		    modifier == I915_FORMAT_MOD_X_TILED ||
>  		    modifier == I915_FORMAT_MOD_Y_TILED)
> @@ -2053,11 +2098,21 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
>  		plane->update_slave = icl_update_slave;
>  
>  	if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
> -		formats = skl_planar_formats;
> -		num_formats = ARRAY_SIZE(skl_planar_formats);
> +		if (icl_is_hdr_plane(dev_priv, plane_id)) {
> +			formats = icl_hdr_planar_formats;
> +			num_formats = ARRAY_SIZE(icl_hdr_planar_formats);
> +		} else {
> +			formats = skl_planar_formats;
> +			num_formats = ARRAY_SIZE(skl_planar_formats);
> +		}
>  	} else {
> -		formats = skl_plane_formats;
> -		num_formats = ARRAY_SIZE(skl_plane_formats);
> +		if (icl_is_hdr_plane(dev_priv, plane_id)) {
> +			formats = icl_hdr_plane_formats;
> +			num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
> +		} else {
> +			formats = skl_plane_formats;
> +			num_formats = ARRAY_SIZE(skl_plane_formats);
> +		}
>  	}
>  
>  	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
> -- 
> 2.7.4

-- 
Ville Syrjälä
Intel
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✗ Fi.CI.CHECKPATCH: warning for Support 64 bpp half float formats (rev4)

[Patchwork]

== Series Details ==

Series: Support 64 bpp half float formats (rev4)
URL   : https://patchwork.freedesktop.org/series/53212/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
c9d4f9ecb2a6 drm/fourcc: Add 64 bpp half float formats
-:40: WARNING:LONG_LINE: line over 100 characters
#40: FILE: drivers/gpu/drm/drm_fourcc.c:201:
+		{ .format = DRM_FORMAT_XRGB16161616F,	.depth = 48, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },

-:41: WARNING:LONG_LINE: line over 100 characters
#41: FILE: drivers/gpu/drm/drm_fourcc.c:202:
+		{ .format = DRM_FORMAT_XBGR16161616F,	.depth = 48, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },

-:42: WARNING:LONG_LINE: line over 100 characters
#42: FILE: drivers/gpu/drm/drm_fourcc.c:203:
+		{ .format = DRM_FORMAT_ARGB16161616F,	.depth = 64, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

-:43: WARNING:LONG_LINE: line over 100 characters
#43: FILE: drivers/gpu/drm/drm_fourcc.c:204:
+		{ .format = DRM_FORMAT_ABGR16161616F,	.depth = 64, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

-:60: WARNING:LONG_LINE_COMMENT: line over 100 characters
#60: FILE: include/uapi/drm/drm_fourcc.h:152:
+#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */

-:61: WARNING:LONG_LINE_COMMENT: line over 100 characters
#61: FILE: include/uapi/drm/drm_fourcc.h:153:
+#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */

-:63: WARNING:LONG_LINE_COMMENT: line over 100 characters
#63: FILE: include/uapi/drm/drm_fourcc.h:155:
+#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */

-:64: WARNING:LONG_LINE_COMMENT: line over 100 characters
#64: FILE: include/uapi/drm/drm_fourcc.h:156:
+#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */

total: 0 errors, 8 warnings, 0 checks, 27 lines checked
9f98b0e8b48a drm/i915: Refactor icl_is_hdr_plane
432b489f9add drm/i915/icl: Implement half float formats

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✓ Fi.CI.BAT: success for Support 64 bpp half float formats (rev4)

[Patchwork]

== Series Details ==

Series: Support 64 bpp half float formats (rev4)
URL   : https://patchwork.freedesktop.org/series/53212/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5547 -> Patchwork_12151
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/53212/revisions/4/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_12151:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@runner@aborted}:
    - {fi-icl-u3}:        NOTRUN -> FAIL

  
Known issues
------------

  Here are the changes found in Patchwork_12151 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-blb-e6850:       PASS -> INCOMPLETE [fdo#107718]

  
#### Possible fixes ####

  * igt@i915_module_load@reload-with-fault-injection:
    - fi-kbl-7567u:       DMESG-WARN [fdo#105602] / [fdo#108529] -> PASS +1

  * igt@kms_busy@basic-flip-a:
    - fi-gdg-551:         FAIL [fdo#103182] -> PASS

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-kbl-7567u:       DMESG-FAIL [fdo#105079] -> PASS

  * igt@kms_flip@basic-flip-vs-modeset:
    - fi-skl-6700hq:      DMESG-WARN [fdo#105998] -> PASS +1

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
    - fi-byt-clapper:     FAIL [fdo#103191] / [fdo#107362] -> PASS

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
    - fi-kbl-7567u:       {SKIP} [fdo#109271] -> PASS +33

  * igt@pm_rpm@module-reload:
    - fi-kbl-7567u:       DMESG-WARN [fdo#108529] -> PASS

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#105998]: https://bugs.freedesktop.org/show_bug.cgi?id=105998
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271


Participating hosts (49 -> 46)
------------------------------

  Missing    (3): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 


Build changes
-------------

    * Linux: CI_DRM_5547 -> Patchwork_12151

  CI_DRM_5547: 8bc7857a02a3c7cf88b5d683edf8cc947e140c46 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4812: 592b854fead32c2b0dac7198edfb9a6bffd66932 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12151: 432b489f9addbe9613e29a4e8d851d82f6465e69 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

432b489f9add drm/i915/icl: Implement half float formats
9f98b0e8b48a drm/i915: Refactor icl_is_hdr_plane
c9d4f9ecb2a6 drm/fourcc: Add 64 bpp half float formats

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12151/
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✓ Fi.CI.IGT: success for Support 64 bpp half float formats (rev4)

[Patchwork]

== Series Details ==

Series: Support 64 bpp half float formats (rev4)
URL   : https://patchwork.freedesktop.org/series/53212/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5547_full -> Patchwork_12151_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_12151_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@reset-stress:
    - shard-apl:          PASS -> INCOMPLETE [fdo#103927]

  * igt@kms_cursor_crc@cursor-size-change:
    - shard-glk:          PASS -> FAIL [fdo#103232] +1

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff:
    - shard-glk:          PASS -> FAIL [fdo#103167]

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
    - shard-apl:          PASS -> FAIL [fdo#103166] +2

  * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
    - shard-kbl:          PASS -> DMESG-FAIL [fdo#105763]

  * igt@kms_setmode@basic:
    - shard-apl:          PASS -> FAIL [fdo#99912]
    - shard-kbl:          PASS -> FAIL [fdo#99912]

  
#### Possible fixes ####

  * igt@gem_fence_thrash@bo-write-verify-threaded-x:
    - shard-glk:          INCOMPLETE [fdo#103359] / [k.org#198133] -> PASS

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
    - shard-glk:          DMESG-WARN [fdo#107956] -> PASS

  * igt@kms_color@pipe-a-ctm-max:
    - shard-apl:          FAIL [fdo#108147] -> PASS

  * igt@kms_cursor_crc@cursor-128x42-sliding:
    - shard-apl:          FAIL [fdo#103232] -> PASS +1

  * igt@kms_cursor_crc@cursor-256x256-suspend:
    - shard-apl:          FAIL [fdo#103191] / [fdo#103232] -> PASS

  * igt@kms_cursor_crc@cursor-64x21-onscreen:
    - shard-glk:          FAIL [fdo#103232] -> PASS +1

  * igt@kms_cursor_crc@cursor-alpha-opaque:
    - shard-apl:          FAIL [fdo#109350] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-apl:          FAIL [fdo#103167] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
    - shard-glk:          FAIL [fdo#103167] -> PASS +2

  * igt@kms_plane@pixel-format-pipe-a-planes:
    - shard-apl:          FAIL [fdo#103166] -> PASS +1

  * igt@kms_plane@pixel-format-pipe-b-planes:
    - shard-glk:          FAIL [fdo#103166] -> PASS +1

  * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
    - shard-apl:          FAIL [fdo#108948] -> PASS

  * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
    - shard-apl:          FAIL [fdo#108145] -> PASS

  * igt@pm_rpm@system-suspend:
    - shard-kbl:          INCOMPLETE [fdo#103665] / [fdo#107807] -> PASS

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
  [fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109350]: https://bugs.freedesktop.org/show_bug.cgi?id=109350
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (6 -> 4)
------------------------------

  Missing    (2): shard-skl shard-iclb 


Build changes
-------------

    * Linux: CI_DRM_5547 -> Patchwork_12151

  CI_DRM_5547: 8bc7857a02a3c7cf88b5d683edf8cc947e140c46 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4812: 592b854fead32c2b0dac7198edfb9a6bffd66932 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12151: 432b489f9addbe9613e29a4e8d851d82f6465e69 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12151/
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