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From: <Claudiu.Beznea@microchip.com>
To: <thierry.reding@gmail.com>, <robh+dt@kernel.org>,
	<mark.rutland@arm.com>, <Nicolas.Ferre@microchip.com>,
	<alexandre.belloni@bootlin.com>,
	<Ludovic.Desroches@microchip.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
	<linux-pwm@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <Claudiu.Beznea@microchip.com>
Subject: [PATCH v2 3/4] pwm: atmel: add support for SAM9X60's PWM controller
Date: Tue, 19 Feb 2019 10:09:00 +0000	[thread overview]
Message-ID: <1550570914-26391-4-git-send-email-claudiu.beznea@microchip.com> (raw)
In-Reply-To: <1550570914-26391-1-git-send-email-claudiu.beznea@microchip.com>

From: Claudiu Beznea <claudiu.beznea@microchip.com>

Add support for SAM9X60's PWM controller.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 drivers/pwm/pwm-atmel.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c
index 647d063562db..229cedb02770 100644
--- a/drivers/pwm/pwm-atmel.c
+++ b/drivers/pwm/pwm-atmel.c
@@ -52,6 +52,8 @@
 
 /* Only the LSB 16 bits are significant. */
 #define PWM_MAXV1_PRD		0xFFFF
+/* All 32 bits are significant. */
+#define PWM_MAXV2_PRD		0xFFFFFFFF
 #define PRD_MAXV1_PRES		10
 
 struct atmel_pwm_registers {
@@ -311,6 +313,20 @@ static const struct atmel_pwm_data atmel_pwm_data_v2 = {
 	},
 };
 
+static const struct atmel_pwm_data atmel_pwm_data_v3 = {
+	.regs = {
+		.period		= PWMV1_CPRD,
+		.period_upd	= PWMV1_CUPD,
+		.duty		= PWMV1_CDTY,
+		.duty_upd	= PWMV1_CUPD,
+	},
+	.cfg = {
+		/* 32 bits to keep period and duty. */
+		.max_period	= PWM_MAXV2_PRD,
+		.max_pres	= PRD_MAXV1_PRES,
+	},
+};
+
 static const struct platform_device_id atmel_pwm_devtypes[] = {
 	{
 		.name = "at91sam9rl-pwm",
@@ -335,6 +351,9 @@ static const struct of_device_id atmel_pwm_dt_ids[] = {
 		.compatible = "atmel,sama5d2-pwm",
 		.data = &atmel_pwm_data_v2,
 	}, {
+		.compatible = "microchip,sam9x60-pwm",
+		.data = &atmel_pwm_data_v3,
+	}, {
 		/* sentinel */
 	},
 };
-- 
2.7.4


WARNING: multiple messages have this Message-ID (diff)
From: <Claudiu.Beznea@microchip.com>
To: thierry.reding@gmail.com, robh+dt@kernel.org,
	mark.rutland@arm.com, Nicolas.Ferre@microchip.com,
	alexandre.belloni@bootlin.com, Ludovic.Desroches@microchip.com
Cc: linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	Claudiu.Beznea@microchip.com
Subject: [PATCH v2 3/4] pwm: atmel: add support for SAM9X60's PWM controller
Date: Tue, 19 Feb 2019 10:09:00 +0000	[thread overview]
Message-ID: <1550570914-26391-4-git-send-email-claudiu.beznea@microchip.com> (raw)
In-Reply-To: <1550570914-26391-1-git-send-email-claudiu.beznea@microchip.com>

From: Claudiu Beznea <claudiu.beznea@microchip.com>

Add support for SAM9X60's PWM controller.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 drivers/pwm/pwm-atmel.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c
index 647d063562db..229cedb02770 100644
--- a/drivers/pwm/pwm-atmel.c
+++ b/drivers/pwm/pwm-atmel.c
@@ -52,6 +52,8 @@
 
 /* Only the LSB 16 bits are significant. */
 #define PWM_MAXV1_PRD		0xFFFF
+/* All 32 bits are significant. */
+#define PWM_MAXV2_PRD		0xFFFFFFFF
 #define PRD_MAXV1_PRES		10
 
 struct atmel_pwm_registers {
@@ -311,6 +313,20 @@ static const struct atmel_pwm_data atmel_pwm_data_v2 = {
 	},
 };
 
+static const struct atmel_pwm_data atmel_pwm_data_v3 = {
+	.regs = {
+		.period		= PWMV1_CPRD,
+		.period_upd	= PWMV1_CUPD,
+		.duty		= PWMV1_CDTY,
+		.duty_upd	= PWMV1_CUPD,
+	},
+	.cfg = {
+		/* 32 bits to keep period and duty. */
+		.max_period	= PWM_MAXV2_PRD,
+		.max_pres	= PRD_MAXV1_PRES,
+	},
+};
+
 static const struct platform_device_id atmel_pwm_devtypes[] = {
 	{
 		.name = "at91sam9rl-pwm",
@@ -335,6 +351,9 @@ static const struct of_device_id atmel_pwm_dt_ids[] = {
 		.compatible = "atmel,sama5d2-pwm",
 		.data = &atmel_pwm_data_v2,
 	}, {
+		.compatible = "microchip,sam9x60-pwm",
+		.data = &atmel_pwm_data_v3,
+	}, {
 		/* sentinel */
 	},
 };
-- 
2.7.4

WARNING: multiple messages have this Message-ID (diff)
From: <Claudiu.Beznea@microchip.com>
To: <thierry.reding@gmail.com>, <robh+dt@kernel.org>,
	<mark.rutland@arm.com>,  <Nicolas.Ferre@microchip.com>,
	<alexandre.belloni@bootlin.com>,
	<Ludovic.Desroches@microchip.com>
Cc: linux-pwm@vger.kernel.org, Claudiu.Beznea@microchip.com,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org
Subject: [PATCH v2 3/4] pwm: atmel: add support for SAM9X60's PWM controller
Date: Tue, 19 Feb 2019 10:09:00 +0000	[thread overview]
Message-ID: <1550570914-26391-4-git-send-email-claudiu.beznea@microchip.com> (raw)
In-Reply-To: <1550570914-26391-1-git-send-email-claudiu.beznea@microchip.com>

From: Claudiu Beznea <claudiu.beznea@microchip.com>

Add support for SAM9X60's PWM controller.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 drivers/pwm/pwm-atmel.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c
index 647d063562db..229cedb02770 100644
--- a/drivers/pwm/pwm-atmel.c
+++ b/drivers/pwm/pwm-atmel.c
@@ -52,6 +52,8 @@
 
 /* Only the LSB 16 bits are significant. */
 #define PWM_MAXV1_PRD		0xFFFF
+/* All 32 bits are significant. */
+#define PWM_MAXV2_PRD		0xFFFFFFFF
 #define PRD_MAXV1_PRES		10
 
 struct atmel_pwm_registers {
@@ -311,6 +313,20 @@ static const struct atmel_pwm_data atmel_pwm_data_v2 = {
 	},
 };
 
+static const struct atmel_pwm_data atmel_pwm_data_v3 = {
+	.regs = {
+		.period		= PWMV1_CPRD,
+		.period_upd	= PWMV1_CUPD,
+		.duty		= PWMV1_CDTY,
+		.duty_upd	= PWMV1_CUPD,
+	},
+	.cfg = {
+		/* 32 bits to keep period and duty. */
+		.max_period	= PWM_MAXV2_PRD,
+		.max_pres	= PRD_MAXV1_PRES,
+	},
+};
+
 static const struct platform_device_id atmel_pwm_devtypes[] = {
 	{
 		.name = "at91sam9rl-pwm",
@@ -335,6 +351,9 @@ static const struct of_device_id atmel_pwm_dt_ids[] = {
 		.compatible = "atmel,sama5d2-pwm",
 		.data = &atmel_pwm_data_v2,
 	}, {
+		.compatible = "microchip,sam9x60-pwm",
+		.data = &atmel_pwm_data_v3,
+	}, {
 		/* sentinel */
 	},
 };
-- 
2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2019-02-19 10:09 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-19 10:08 [PATCH v2 0/4] add support for the new SAM9X60's PWM controller Claudiu.Beznea
2019-02-19 10:08 ` Claudiu.Beznea
2019-02-19 10:08 ` Claudiu.Beznea
2019-02-19 10:08 ` [PATCH v2 1/4] pwm: atmel: add struct atmel_pwm_data Claudiu.Beznea
2019-02-19 10:08   ` Claudiu.Beznea
2019-02-19 10:08   ` Claudiu.Beznea
2019-02-21 20:13   ` Uwe Kleine-König
2019-02-21 20:13     ` Uwe Kleine-König
2019-02-19 10:08 ` [PATCH v2 2/4] pwm: atmel: add support for controllers with 32 bit counters Claudiu.Beznea
2019-02-19 10:08   ` Claudiu.Beznea
2019-02-19 10:08   ` Claudiu.Beznea
2019-02-21 20:42   ` Uwe Kleine-König
2019-02-21 20:42     ` Uwe Kleine-König
2019-02-22  9:10     ` Claudiu.Beznea
2019-02-22  9:10       ` Claudiu.Beznea
2019-02-22  9:10       ` Claudiu.Beznea
2019-02-19 10:09 ` Claudiu.Beznea [this message]
2019-02-19 10:09   ` [PATCH v2 3/4] pwm: atmel: add support for SAM9X60's PWM controller Claudiu.Beznea
2019-02-19 10:09   ` Claudiu.Beznea
2019-02-21 20:45   ` Uwe Kleine-König
2019-02-21 20:45     ` Uwe Kleine-König
2019-02-22  9:07     ` Claudiu.Beznea
2019-02-22  9:07       ` Claudiu.Beznea
2019-02-22  9:07       ` Claudiu.Beznea
2019-02-22  9:27       ` Uwe Kleine-König
2019-02-22  9:27         ` Uwe Kleine-König
2019-02-22  9:27         ` Uwe Kleine-König
2019-02-19 10:09 ` [PATCH v2 4/4] pwm: atmel: add PWM binding for SAM9X60 Claudiu.Beznea
2019-02-19 10:09   ` Claudiu.Beznea
2019-02-19 10:09   ` Claudiu.Beznea

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