[PATCH 1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads

[PATCH 1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads

[Michał Winiarski]

We assumed that the default preemption granularity is fine for ICL.
Unfortunately, it turns out that some drivers don't support mid-thread
preemption for compute workloads.
If a workload that doesn't support mid-thread preemption gets mid-thread
preempted, we're going to observe a GPU hang.
While I'm here, let's also update the "workaround" naming.

Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Anuj Phogat <anuj.phogat@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
---
 drivers/gpu/drm/i915/intel_workarounds.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 743cf5b00155..a19e1c0052a7 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -555,6 +555,11 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine)
 			   GEN10_CACHE_MODE_SS,
 			   0, /* write-only, so skip validation */
 			   _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE));
+
+	/* WaDisableGPGPUMidThreadPreemption:icl */
+	WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
+			    GEN9_PREEMPT_GPGPU_LEVEL_MASK,
+			    GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
 }
 
 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
@@ -1170,8 +1175,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 				    GEN7_DISABLE_SAMPLER_PREFETCH);
 	}
 
-	if (IS_GEN(i915, 9) || IS_CANNONLAKE(i915)) {
-		/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl */
+	if (IS_GEN_RANGE(i915, 9, 11)) {
+		/* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl */
 		wa_masked_en(wal,
 			     GEN7_FF_SLICE_CS_CHICKEN1,
 			     GEN9_FFSC_PERCTX_PREEMPT_CTRL);
-- 
2.20.1

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[PATCH 2/2] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD

[Michał Winiarski]

There are still some cases where userspace needs to change the
preemption granularity for compute workloads. Let's whitelist the
per-ctx granularity control register to allow it.

Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Anuj Phogat <anuj.phogat@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
---
 drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index a19e1c0052a7..1aa167415096 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -1057,6 +1057,9 @@ static void icl_whitelist_build(struct i915_wa_list *w)
 
 	/* WaAllowUMDToModifySamplerMode:icl */
 	whitelist_reg(w, GEN10_SAMPLER_MODE);
+
+	/* WaEnablePreemptionGranularityControlByUMD:icl */
+	whitelist_reg(w, GEN8_CS_CHICKEN1);
 }
 
 void intel_engine_init_whitelist(struct intel_engine_cs *engine)
-- 
2.20.1

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Re: [PATCH 2/2] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD

[Chris Wilson]

Quoting Michał Winiarski (2019-02-27 15:51:09)
> There are still some cases where userspace needs to change the
> preemption granularity for compute workloads. Let's whitelist the
> per-ctx granularity control register to allow it.

Just wondering aloud if this should a single patch; change the default
and allow userspace to opt-in in a single switch.
-Chris
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Re: [PATCH 2/2] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD

[Chris Wilson]

Quoting Michał Winiarski (2019-02-27 15:51:09)
> There are still some cases where userspace needs to change the
> preemption granularity for compute workloads. Let's whitelist the
> per-ctx granularity control register to allow it.
> 
> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Anuj Phogat <anuj.phogat@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index a19e1c0052a7..1aa167415096 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -1057,6 +1057,9 @@ static void icl_whitelist_build(struct i915_wa_list *w)
>  
>         /* WaAllowUMDToModifySamplerMode:icl */
>         whitelist_reg(w, GEN10_SAMPLER_MODE);
> +
> +       /* WaEnablePreemptionGranularityControlByUMD:icl */
> +       whitelist_reg(w, GEN8_CS_CHICKEN1);

Whilst you are here, I have a task to add a quick little test to check
to make sure that "userspace" can actually write to the whitelisted
register. Or at least review the selftest and fill in a few gaps.
-Chris
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✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads
URL   : https://patchwork.freedesktop.org/series/57300/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5666 -> Patchwork_12315
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/57300/revisions/1/

Known issues
------------

  Here are the changes found in Patchwork_12315 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-blb-e6850:       PASS -> INCOMPLETE [fdo#107718]

  * igt@i915_selftest@live_contexts:
    - fi-icl-u2:          NOTRUN -> DMESG-FAIL [fdo#108569]

  * igt@i915_selftest@live_requests:
    - fi-icl-u3:          PASS -> DMESG-FAIL [fdo#109644]

  
#### Possible fixes ####

  * igt@i915_selftest@live_requests:
    - fi-icl-u2:          INCOMPLETE [fdo#109644] -> PASS

  
#### Warnings ####

  * igt@prime_vgem@basic-fence-flip:
    - fi-gdg-551:         FAIL [fdo#103182] -> DMESG-FAIL [fdo#103182]

  
  [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#109644]: https://bugs.freedesktop.org/show_bug.cgi?id=109644


Participating hosts (44 -> 39)
------------------------------

  Missing    (5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 


Build changes
-------------

    * Linux: CI_DRM_5666 -> Patchwork_12315

  CI_DRM_5666: 358ab8acaabef3cef2a7ce9e5dd7c4196a0c30fc @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4860: b79007f9c575a538a63ce9301a890ed9e1a45f35 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12315: 02a1ad846725b72884ede07b5f946a9c00b6b4a1 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

02a1ad846725 drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD
4f4bb7bd5f22 drm/i915/icl: Default to Thread Group preemption for compute workloads

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12315/
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✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads
URL   : https://patchwork.freedesktop.org/series/57300/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5666_full -> Patchwork_12315_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_12315_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_12315_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_12315_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_universal_plane@disable-primary-vs-flip-pipe-c:
    - shard-apl:          PASS -> DMESG-WARN

  
Known issues
------------

  Here are the changes found in Patchwork_12315_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_bad_reloc@negative-reloc-bsd2:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109276] +7

  * igt@gem_exec_params@no-vebox:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109283]

  * igt@gem_pwrite@huge-gtt-forwards:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109290]

  * igt@gem_softpin@noreloc-s3:
    - shard-skl:          PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]

  * igt@i915_pm_rpm@dpms-lpsp:
    - shard-iclb:         PASS -> INCOMPLETE [fdo#108840]

  * igt@i915_pm_rpm@dpms-non-lpsp:
    - shard-skl:          NOTRUN -> INCOMPLETE [fdo#107807]

  * igt@i915_pm_rpm@gem-idle:
    - shard-iclb:         PASS -> DMESG-WARN [fdo#107724] +5

  * igt@i915_pm_rpm@system-suspend-execbuf:
    - shard-iclb:         PASS -> INCOMPLETE [fdo#107713] / [fdo#108840]

  * igt@i915_query@query-topology-known-pci-ids:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109303]

  * igt@kms_busy@extended-modeset-hang-newfb-render-b:
    - shard-skl:          PASS -> DMESG-WARN [fdo#107956]

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
    - shard-hsw:          PASS -> DMESG-WARN [fdo#107956]

  * igt@kms_busy@extended-modeset-hang-oldfb-render-d:
    - shard-skl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +4

  * igt@kms_busy@extended-modeset-hang-oldfb-render-e:
    - shard-kbl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +4

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
    - shard-iclb:         NOTRUN -> DMESG-WARN [fdo#107956]
    - shard-apl:          PASS -> DMESG-WARN [fdo#107956]

  * igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
    - shard-glk:          PASS -> FAIL [fdo#108145]
    - shard-iclb:         NOTRUN -> FAIL [fdo#107725] +1

  * igt@kms_ccs@pipe-c-missing-ccs-buffer:
    - shard-apl:          NOTRUN -> SKIP [fdo#109271] +21

  * igt@kms_chamelium@hdmi-edid-read:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109284] +1

  * igt@kms_color@pipe-c-legacy-gamma:
    - shard-apl:          PASS -> FAIL [fdo#104782] +1

  * igt@kms_concurrent@pipe-f:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109278] +1

  * igt@kms_cursor_crc@cursor-128x128-dpms:
    - shard-iclb:         NOTRUN -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-128x128-random:
    - shard-apl:          PASS -> FAIL [fdo#103232] +1

  * igt@kms_cursor_crc@cursor-256x85-sliding:
    - shard-apl:          NOTRUN -> FAIL [fdo#103232] +1

  * igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109274] +1

  * igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-ytiled:
    - shard-skl:          PASS -> FAIL [fdo#103184]

  * igt@kms_flip@dpms-vs-vblank-race:
    - shard-glk:          PASS -> FAIL [fdo#103060]

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-apl:          PASS -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
    - shard-glk:          PASS -> FAIL [fdo#103167] +1

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack:
    - shard-iclb:         PASS -> FAIL [fdo#103167] +2

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109280] +8

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc:
    - shard-kbl:          NOTRUN -> SKIP [fdo#109271] +59

  * igt@kms_invalid_dotclock:
    - shard-skl:          NOTRUN -> SKIP [fdo#109271] +53

  * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
    - shard-skl:          NOTRUN -> FAIL [fdo#108145] +1

  * igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
    - shard-kbl:          NOTRUN -> FAIL [fdo#108145] / [fdo#108590]

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
    - shard-kbl:          NOTRUN -> FAIL [fdo#108145]

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
    - shard-iclb:         PASS -> FAIL [fdo#103166]

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
    - shard-apl:          PASS -> FAIL [fdo#103166]

  * igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
    - shard-glk:          PASS -> FAIL [fdo#103166] +1

  * igt@kms_psr@psr2_primary_mmap_cpu:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109441] +1

  * igt@prime_udl:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109291] +1

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-apl:          INCOMPLETE [fdo#103927] -> PASS

  * igt@gem_exec_suspend@basic-s3:
    - shard-iclb:         INCOMPLETE [fdo#107713] -> PASS

  * igt@i915_pm_rpm@basic-rte:
    - shard-iclb:         DMESG-WARN [fdo#107724] -> PASS +4

  * igt@kms_cursor_crc@cursor-128x42-random:
    - shard-apl:          FAIL [fdo#103232] -> PASS

  * igt@kms_cursor_crc@cursor-size-change:
    - shard-glk:          FAIL [fdo#103232] -> PASS

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-glk:          FAIL [fdo#104873] -> PASS

  * igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-ytiled:
    - shard-glk:          FAIL [fdo#103184] -> PASS
    - shard-iclb:         FAIL [fdo#103184] -> PASS

  * igt@kms_flip@flip-vs-suspend:
    - shard-skl:          INCOMPLETE [fdo#107773] / [fdo#109507] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
    - shard-apl:          FAIL [fdo#103167] -> PASS +2

  * igt@kms_frontbuffer_tracking@fbc-1p-rte:
    - shard-apl:          FAIL [fdo#103167] / [fdo#105682] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite:
    - shard-glk:          FAIL [fdo#103167] -> PASS +1

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt:
    - shard-iclb:         FAIL [fdo#103167] -> PASS +3

  * igt@kms_frontbuffer_tracking@fbcpsr-tilingchange:
    - shard-iclb:         FAIL -> PASS +7

  * igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
    - shard-apl:          FAIL [fdo#108948] -> PASS

  * igt@kms_plane@plane-position-covered-pipe-b-planes:
    - shard-glk:          FAIL [fdo#103166] -> PASS

  * igt@kms_plane_multiple@atomic-pipe-c-tiling-none:
    - shard-iclb:         FAIL [fdo#103166] -> PASS +1

  * igt@kms_psr@sprite_blt:
    - shard-iclb:         FAIL [fdo#107383] -> PASS

  * igt@kms_sysfs_edid_timing:
    - shard-iclb:         FAIL [fdo#100047] -> PASS

  * igt@tools_test@tools_test:
    - shard-hsw:          SKIP [fdo#109271] -> PASS
    - shard-kbl:          SKIP [fdo#109271] -> PASS

  
#### Warnings ####

  * igt@i915_pm_rpm@gem-execbuf-stress-pc8:
    - shard-skl:          SKIP [fdo#109271] -> INCOMPLETE [fdo#107807]

  * igt@kms_cursor_crc@cursor-256x256-suspend:
    - shard-iclb:         INCOMPLETE [fdo#107713] -> FAIL [fdo#103232]

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
  [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
  [fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
  [fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
  [fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725
  [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108590]: https://bugs.freedesktop.org/show_bug.cgi?id=108590
  [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
  [fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109290]: https://bugs.freedesktop.org/show_bug.cgi?id=109290
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507


Participating hosts (7 -> 7)
------------------------------

  No changes in participating hosts


Build changes
-------------

    * Linux: CI_DRM_5666 -> Patchwork_12315

  CI_DRM_5666: 358ab8acaabef3cef2a7ce9e5dd7c4196a0c30fc @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4860: b79007f9c575a538a63ce9301a890ed9e1a45f35 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12315: 02a1ad846725b72884ede07b5f946a9c00b6b4a1 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12315/
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Re: [PATCH 1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads

[Anuj Phogat]

Tested both the patches with drm-tip kernel. Fixes multiple gpu hangs
in vulkan cts and piglit. I will do more thorough testing with updated
version of these patches based on review.



On Wed, Feb 27, 2019 at 7:52 AM Michał Winiarski
<michal.winiarski@intel.com> wrote:
>
> We assumed that the default preemption granularity is fine for ICL.
> Unfortunately, it turns out that some drivers don't support mid-thread
> preemption for compute workloads.
> If a workload that doesn't support mid-thread preemption gets mid-thread
> preempted, we're going to observe a GPU hang.
> While I'm here, let's also update the "workaround" naming.
>
> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Anuj Phogat <anuj.phogat@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_workarounds.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 743cf5b00155..a19e1c0052a7 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -555,6 +555,11 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine)
>                            GEN10_CACHE_MODE_SS,
>                            0, /* write-only, so skip validation */
>                            _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE));
> +
> +       /* WaDisableGPGPUMidThreadPreemption:icl */
> +       WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
> +                           GEN9_PREEMPT_GPGPU_LEVEL_MASK,
> +                           GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
>  }
>
>  void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
> @@ -1170,8 +1175,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>                                     GEN7_DISABLE_SAMPLER_PREFETCH);
>         }
>
> -       if (IS_GEN(i915, 9) || IS_CANNONLAKE(i915)) {
> -               /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl */
> +       if (IS_GEN_RANGE(i915, 9, 11)) {
> +               /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl */
>                 wa_masked_en(wal,
>                              GEN7_FF_SLICE_CS_CHICKEN1,
>                              GEN9_FFSC_PERCTX_PREEMPT_CTRL);
> --
> 2.20.1
>
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> Intel-gfx@lists.freedesktop.org
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Re: [PATCH 1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads

[Rodrigo Vivi]

On Wed, Feb 27, 2019 at 04:51:08PM +0100, Michał Winiarski wrote:
> We assumed that the default preemption granularity is fine for ICL.
> Unfortunately, it turns out that some drivers don't support mid-thread
> preemption for compute workloads.
> If a workload that doesn't support mid-thread preemption gets mid-thread
> preempted, we're going to observe a GPU hang.
> While I'm here, let's also update the "workaround" naming.
> 
> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Anuj Phogat <anuj.phogat@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_workarounds.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 743cf5b00155..a19e1c0052a7 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -555,6 +555,11 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine)
>  			   GEN10_CACHE_MODE_SS,
>  			   0, /* write-only, so skip validation */
>  			   _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE));
> +
> +	/* WaDisableGPGPUMidThreadPreemption:icl */

Could you please give me some internal pointers to this WA?
I couldn't find it on bspec nor on wadb.

> +	WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
> +			    GEN9_PREEMPT_GPGPU_LEVEL_MASK,
> +			    GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
>  }
>  
>  void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
> @@ -1170,8 +1175,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  				    GEN7_DISABLE_SAMPLER_PREFETCH);
>  	}
>  
> -	if (IS_GEN(i915, 9) || IS_CANNONLAKE(i915)) {
> -		/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl */

Please don't remove the old name that is still part of old
references. If we have a new name for ICL+ please keep both
here on the comments.


> +	if (IS_GEN_RANGE(i915, 9, 11)) {
> +		/* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl */

also please give me a pointer to this...

Thanks,
Rodrigo.

>  		wa_masked_en(wal,
>  			     GEN7_FF_SLICE_CS_CHICKEN1,
>  			     GEN9_FFSC_PERCTX_PREEMPT_CTRL);
> -- 
> 2.20.1
> 
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH 1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads

[Rodrigo Vivi]

On Thu, Feb 28, 2019 at 11:02:54AM -0800, Rodrigo Vivi wrote:
> On Wed, Feb 27, 2019 at 04:51:08PM +0100, Michał Winiarski wrote:
> > We assumed that the default preemption granularity is fine for ICL.
> > Unfortunately, it turns out that some drivers don't support mid-thread
> > preemption for compute workloads.
> > If a workload that doesn't support mid-thread preemption gets mid-thread
> > preempted, we're going to observe a GPU hang.
> > While I'm here, let's also update the "workaround" naming.
> > 
> > Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> > Cc: Anuj Phogat <anuj.phogat@intel.com>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_workarounds.c | 9 +++++++--
> >  1 file changed, 7 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> > index 743cf5b00155..a19e1c0052a7 100644
> > --- a/drivers/gpu/drm/i915/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> > @@ -555,6 +555,11 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine)
> >  			   GEN10_CACHE_MODE_SS,
> >  			   0, /* write-only, so skip validation */
> >  			   _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE));
> > +
> > +	/* WaDisableGPGPUMidThreadPreemption:icl */
> 
> Could you please give me some internal pointers to this WA?
> I couldn't find it on bspec nor on wadb.
> 
> > +	WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
> > +			    GEN9_PREEMPT_GPGPU_LEVEL_MASK,
> > +			    GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
> >  }
> >  
> >  void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
> > @@ -1170,8 +1175,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> >  				    GEN7_DISABLE_SAMPLER_PREFETCH);
> >  	}
> >  
> > -	if (IS_GEN(i915, 9) || IS_CANNONLAKE(i915)) {
> > -		/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl */
> 
> Please don't remove the old name that is still part of old
> references. If we have a new name for ICL+ please keep both
> here on the comments.

I'm sorry for my delayed response on irc, I hope you that answer
came in time to avoid your rework.

I just noticed that this name for gen9/10 platforsm is already inside
gen9_whitelist_build() and that on next patch you re-introduce the icl
one...

Also thanks for all the explanations. I checked bits with spec
and everything makes sense now, so:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

(What I' wondering now is that how this behaviour can change with GuC...
I heard some media folks were using i915 directly and facing some
strange gpu hangs but no gpu hang when using guc submission...)

> 
> 
> > +	if (IS_GEN_RANGE(i915, 9, 11)) {
> > +		/* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl */
> 
> also please give me a pointer to this...
> 
> Thanks,
> Rodrigo.
> 
> >  		wa_masked_en(wal,
> >  			     GEN7_FF_SLICE_CS_CHICKEN1,
> >  			     GEN9_FFSC_PERCTX_PREEMPT_CTRL);
> > -- 
> > 2.20.1
> > 
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> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH 1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads

[Chris Wilson]

Quoting Rodrigo Vivi (2019-02-28 22:32:35)
> On Thu, Feb 28, 2019 at 11:02:54AM -0800, Rodrigo Vivi wrote:
> (What I' wondering now is that how this behaviour can change with GuC...
> I heard some media folks were using i915 directly and facing some
> strange gpu hangs but no gpu hang when using guc submission...)

Which probably means no preemption is occurring...
-Chris
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Re: [PATCH 2/2] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD

[Chris Wilson]

Quoting Michał Winiarski (2019-03-05 12:48:27)
> There are still some cases where userspace needs to change the
> preemption granularity for compute workloads. Let's whitelist the
> per-ctx granularity control register to allow it.
> 
> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Anuj Phogat <anuj.phogat@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>

Trusting that since it was context saved on earlier gen, it remains so.
(One more selftest to write.)

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [PATCH 2/2] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD

[Rafael Antognolli]

On Tue, Mar 05, 2019 at 01:48:27PM +0100, Michał Winiarski wrote:
> There are still some cases where userspace needs to change the
> preemption granularity for compute workloads. Let's whitelist the
> per-ctx granularity control register to allow it.

We are not planning to enable it just yet but would be good to easily
enable it in the future.

Acked-by: Rafael Antognolli <rafael.antognolli@intel.com>

> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Anuj Phogat <anuj.phogat@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 2fba33509f4e..582f554e53f4 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -1053,6 +1053,9 @@ static void icl_whitelist_build(struct i915_wa_list *w)
>  
>  	/* WaAllowUMDToModifySamplerMode:icl */
>  	whitelist_reg(w, GEN10_SAMPLER_MODE);
> +
> +	/* WaEnablePreemptionGranularityControlByUMD:icl */
> +	whitelist_reg(w, GEN8_CS_CHICKEN1);
>  }
>  
>  void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> -- 
> 2.20.1
> 
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[PATCH 2/2] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD

[Michał Winiarski]

There are still some cases where userspace needs to change the
preemption granularity for compute workloads. Let's whitelist the
per-ctx granularity control register to allow it.

Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Anuj Phogat <anuj.phogat@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 2fba33509f4e..582f554e53f4 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -1053,6 +1053,9 @@ static void icl_whitelist_build(struct i915_wa_list *w)
 
 	/* WaAllowUMDToModifySamplerMode:icl */
 	whitelist_reg(w, GEN10_SAMPLER_MODE);
+
+	/* WaEnablePreemptionGranularityControlByUMD:icl */
+	whitelist_reg(w, GEN8_CS_CHICKEN1);
 }
 
 void intel_engine_init_whitelist(struct intel_engine_cs *engine)
-- 
2.20.1

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