* [PATCH 1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads
@ 2019-03-05 12:48 Michał Winiarski
2019-03-05 12:48 ` [PATCH 2/2] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD Michał Winiarski
` (4 more replies)
0 siblings, 5 replies; 14+ messages in thread
From: Michał Winiarski @ 2019-03-05 12:48 UTC (permalink / raw)
To: intel-gfx; +Cc: Anuj Phogat
We assumed that the default preemption granularity is fine for ICL.
Unfortunately, it turns out that some drivers don't support mid-thread
preemption for compute workloads.
If a workload that doesn't support mid-thread preemption gets mid-thread
preempted, we're going to observe a GPU hang.
While I'm here, let's also update the "workaround" naming.
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Anuj Phogat <anuj.phogat@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Tested-by: Anuj Phogat <anuj.phogat@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_workarounds.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 89b4007d5200..2fba33509f4e 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -555,6 +555,11 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine)
GEN10_CACHE_MODE_SS,
0, /* write-only, so skip validation */
_MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE));
+
+ /* WaDisableGPGPUMidThreadPreemption:icl */
+ WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
+ GEN9_PREEMPT_GPGPU_LEVEL_MASK,
+ GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
}
void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
@@ -1162,8 +1167,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN7_DISABLE_SAMPLER_PREFETCH);
}
- if (IS_GEN(i915, 9) || IS_CANNONLAKE(i915)) {
- /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl */
+ if (IS_GEN_RANGE(i915, 9, 11)) {
+ /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl */
wa_masked_en(wal,
GEN7_FF_SLICE_CS_CHICKEN1,
GEN9_FFSC_PERCTX_PREEMPT_CTRL);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/2] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD
2019-03-05 12:48 [PATCH 1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads Michał Winiarski
@ 2019-03-05 12:48 ` Michał Winiarski
2019-03-05 17:31 ` Rafael Antognolli
2019-03-05 18:41 ` Chris Wilson
2019-03-05 13:45 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads Patchwork
` (3 subsequent siblings)
4 siblings, 2 replies; 14+ messages in thread
From: Michał Winiarski @ 2019-03-05 12:48 UTC (permalink / raw)
To: intel-gfx; +Cc: Anuj Phogat
There are still some cases where userspace needs to change the
preemption granularity for compute workloads. Let's whitelist the
per-ctx granularity control register to allow it.
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Anuj Phogat <anuj.phogat@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 2fba33509f4e..582f554e53f4 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -1053,6 +1053,9 @@ static void icl_whitelist_build(struct i915_wa_list *w)
/* WaAllowUMDToModifySamplerMode:icl */
whitelist_reg(w, GEN10_SAMPLER_MODE);
+
+ /* WaEnablePreemptionGranularityControlByUMD:icl */
+ whitelist_reg(w, GEN8_CS_CHICKEN1);
}
void intel_engine_init_whitelist(struct intel_engine_cs *engine)
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads
2019-03-05 12:48 [PATCH 1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads Michał Winiarski
2019-03-05 12:48 ` [PATCH 2/2] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD Michał Winiarski
@ 2019-03-05 13:45 ` Patchwork
2019-03-05 14:48 ` ✓ Fi.CI.IGT: " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2019-03-05 13:45 UTC (permalink / raw)
To: Michał Winiarski; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads
URL : https://patchwork.freedesktop.org/series/57576/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5703 -> Patchwork_12368
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/57576/revisions/1/mbox/
Known issues
------------
Here are the changes found in Patchwork_12368 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@read_all_entries:
- fi-kbl-7567u: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602]
* igt@gem_exec_suspend@basic-s3:
- fi-kbl-7567u: PASS -> DMESG-WARN [fdo#103558] / [fdo#105079] / [fdo#105602]
* igt@i915_module_load@reload-with-fault-injection:
- fi-kbl-7567u: PASS -> DMESG-WARN [fdo#105602] / [fdo#108529] +1
* igt@i915_pm_rpm@module-reload:
- fi-kbl-7567u: PASS -> DMESG-WARN [fdo#108529]
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: PASS -> DMESG-FAIL [fdo#105079]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
- fi-kbl-7567u: PASS -> SKIP [fdo#109271] +33
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@kms_psr@cursor_plane_move:
- fi-skl-6260u: NOTRUN -> SKIP [fdo#109271] +37
#### Possible fixes ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-byt-j1900: SKIP [fdo#109271] -> PASS
* igt@i915_pm_rpm@basic-rte:
- fi-byt-j1900: FAIL [fdo#108800] -> PASS
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: FAIL [fdo#108511] -> PASS
* igt@i915_selftest@live_execlists:
- fi-apl-guc: INCOMPLETE [fdo#103927] / [fdo#109720] -> PASS
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: FAIL [fdo#103182] -> PASS
* igt@kms_busy@basic-flip-c:
- fi-skl-6770hq: SKIP [fdo#109271] / [fdo#109278] -> PASS +2
* igt@kms_flip@basic-flip-vs-dpms:
- fi-skl-6770hq: SKIP [fdo#109271] -> PASS +33
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
Participating hosts (46 -> 42)
------------------------------
Additional (2): fi-icl-y fi-skl-6260u
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_5703 -> Patchwork_12368
CI_DRM_5703: 453da75010eb2a0806e75490b86d24beb6fa76a7 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4870: ed944b45563c694dc6373bc48dc83b8ba7edb19f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12368: 9efdc3519652a7f7f48fe2ff6039f6212ace487d @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9efdc3519652 drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD
73817c7ea7b8 drm/i915/icl: Default to Thread Group preemption for compute workloads
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12368/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads
2019-03-05 12:48 [PATCH 1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads Michał Winiarski
2019-03-05 12:48 ` [PATCH 2/2] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD Michał Winiarski
2019-03-05 13:45 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads Patchwork
@ 2019-03-05 14:48 ` Patchwork
2019-03-05 17:30 ` [PATCH 1/2] " Rafael Antognolli
2019-03-05 17:37 ` Anuj Phogat
4 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2019-03-05 14:48 UTC (permalink / raw)
To: Michał Winiarski; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads
URL : https://patchwork.freedesktop.org/series/57576/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5703_full -> Patchwork_12368_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_12368_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@read_all_entries_display_off:
- shard-skl: PASS -> INCOMPLETE [fdo#104108]
* igt@gem_ctx_param@invalid-param-set:
- shard-skl: NOTRUN -> FAIL [fdo#109674]
* igt@i915_pm_rpm@gem-execbuf:
- shard-skl: PASS -> INCOMPLETE [fdo#107803] / [fdo#107807]
* igt@i915_pm_rpm@system-suspend:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] / [fdo#107807]
* igt@i915_pm_rpm@system-suspend-modeset:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#104108] / [fdo#107773] / [fdo#107807]
* igt@kms_atomic_transition@3x-modeset-transitions:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2
* igt@kms_atomic_transition@5x-modeset-transitions-fencing:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-apl: NOTRUN -> DMESG-WARN [fdo#107956] +1
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-oldfb-render-f:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +9
* igt@kms_chv_cursor_fail@pipe-a-64x64-top-edge:
- shard-skl: PASS -> FAIL [fdo#104671]
* igt@kms_cursor_crc@cursor-128x128-offscreen:
- shard-skl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x21-random:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled:
- shard-skl: NOTRUN -> FAIL [fdo#103184]
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-xtiled:
- shard-skl: PASS -> FAIL [fdo#103184]
* igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +100
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-render:
- shard-skl: NOTRUN -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt:
- shard-skl: NOTRUN -> FAIL [fdo#105682] +1
* igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +14
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +113
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +25
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-pwrite:
- shard-skl: PASS -> FAIL [fdo#103167] +2
* igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
- shard-apl: PASS -> FAIL [fdo#108948]
* igt@kms_plane@pixel-format-pipe-c-planes:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#106885]
* igt@kms_plane@plane-position-covered-pipe-b-planes:
- shard-glk: PASS -> FAIL [fdo#103166]
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +1
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- shard-apl: PASS -> FAIL [fdo#103166] +3
* igt@kms_setmode@basic:
- shard-hsw: PASS -> FAIL [fdo#99912]
- shard-kbl: PASS -> FAIL [fdo#99912]
* igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm:
- shard-apl: PASS -> FAIL [fdo#104894]
* igt@kms_vblank@pipe-c-ts-continuation-modeset:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +10
#### Possible fixes ####
* igt@gem_ctx_isolation@vecs0-s3:
- shard-kbl: INCOMPLETE [fdo#103665] -> PASS
* igt@i915_suspend@debugfs-reader:
- shard-skl: INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS
* igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
- shard-skl: FAIL [fdo#107815] / [fdo#108228] / [fdo#108470] -> PASS
- shard-apl: FAIL [fdo#109660] -> PASS
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
- shard-skl: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_color@pipe-a-degamma:
- shard-apl: FAIL [fdo#104782] / [fdo#108145] -> PASS
* igt@kms_cursor_crc@cursor-128x128-sliding:
- shard-skl: FAIL [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-256x256-random:
- shard-apl: FAIL [fdo#103232] -> PASS +4
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-xtiled:
- shard-skl: FAIL [fdo#103184] -> PASS
* igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled:
- shard-glk: FAIL [fdo#107791] -> PASS
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: INCOMPLETE [fdo#109507] -> PASS
* igt@kms_flip_tiling@flip-to-yf-tiled:
- shard-skl: FAIL [fdo#107931] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt:
- shard-glk: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-rte:
- shard-apl: FAIL [fdo#103167] / [fdo#105682] -> PASS
* igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
- shard-kbl: DMESG-WARN [fdo#103558] / [fdo#105602] -> PASS +7
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: FAIL [fdo#107815] -> PASS +1
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- shard-glk: FAIL [fdo#103166] -> PASS +2
* igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
- shard-apl: FAIL [fdo#103166] -> PASS
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: FAIL [fdo#109016] -> PASS
* igt@kms_vblank@pipe-b-ts-continuation-dpms-rpm:
- shard-apl: FAIL [fdo#104894] -> PASS +1
* igt@perf_pmu@rc6:
- shard-kbl: SKIP [fdo#109271] -> PASS
#### Warnings ####
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-apl: INCOMPLETE [fdo#103927] -> SKIP [fdo#109271]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104671]: https://bugs.freedesktop.org/show_bug.cgi?id=104671
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
[fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#107791]: https://bugs.freedesktop.org/show_bug.cgi?id=107791
[fdo#107803]: https://bugs.freedesktop.org/show_bug.cgi?id=107803
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#107931]: https://bugs.freedesktop.org/show_bug.cgi?id=107931
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108228]: https://bugs.freedesktop.org/show_bug.cgi?id=108228
[fdo#108470]: https://bugs.freedesktop.org/show_bug.cgi?id=108470
[fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
[fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#109660]: https://bugs.freedesktop.org/show_bug.cgi?id=109660
[fdo#109674]: https://bugs.freedesktop.org/show_bug.cgi?id=109674
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (6 -> 6)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_5703 -> Patchwork_12368
CI_DRM_5703: 453da75010eb2a0806e75490b86d24beb6fa76a7 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4870: ed944b45563c694dc6373bc48dc83b8ba7edb19f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12368: 9efdc3519652a7f7f48fe2ff6039f6212ace487d @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12368/
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads
2019-03-05 12:48 [PATCH 1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads Michał Winiarski
` (2 preceding siblings ...)
2019-03-05 14:48 ` ✓ Fi.CI.IGT: " Patchwork
@ 2019-03-05 17:30 ` Rafael Antognolli
2019-03-05 19:10 ` Chris Wilson
2019-03-05 17:37 ` Anuj Phogat
4 siblings, 1 reply; 14+ messages in thread
From: Rafael Antognolli @ 2019-03-05 17:30 UTC (permalink / raw)
To: Michał Winiarski; +Cc: intel-gfx, Anuj Phogat
On Tue, Mar 05, 2019 at 01:48:26PM +0100, Michał Winiarski wrote:
> We assumed that the default preemption granularity is fine for ICL.
> Unfortunately, it turns out that some drivers don't support mid-thread
> preemption for compute workloads.
> If a workload that doesn't support mid-thread preemption gets mid-thread
> preempted, we're going to observe a GPU hang.
> While I'm here, let's also update the "workaround" naming.
Yeah, in Mesa we are not implementing the SIP, so we can't do
thread-level preemption yet and need the granularity to be no higher
than thread group level.
Acked-by: Rafael Antognolli <rafael.antognolli@intel.com>
> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Anuj Phogat <anuj.phogat@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Tested-by: Anuj Phogat <anuj.phogat@intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_workarounds.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 89b4007d5200..2fba33509f4e 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -555,6 +555,11 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine)
> GEN10_CACHE_MODE_SS,
> 0, /* write-only, so skip validation */
> _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE));
> +
> + /* WaDisableGPGPUMidThreadPreemption:icl */
> + WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
> + GEN9_PREEMPT_GPGPU_LEVEL_MASK,
> + GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
> }
>
> void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
> @@ -1162,8 +1167,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> GEN7_DISABLE_SAMPLER_PREFETCH);
> }
>
> - if (IS_GEN(i915, 9) || IS_CANNONLAKE(i915)) {
> - /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl */
> + if (IS_GEN_RANGE(i915, 9, 11)) {
> + /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl */
> wa_masked_en(wal,
> GEN7_FF_SLICE_CS_CHICKEN1,
> GEN9_FFSC_PERCTX_PREEMPT_CTRL);
> --
> 2.20.1
>
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/2] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD
2019-03-05 12:48 ` [PATCH 2/2] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD Michał Winiarski
@ 2019-03-05 17:31 ` Rafael Antognolli
2019-03-05 18:41 ` Chris Wilson
1 sibling, 0 replies; 14+ messages in thread
From: Rafael Antognolli @ 2019-03-05 17:31 UTC (permalink / raw)
To: Michał Winiarski; +Cc: intel-gfx, Anuj Phogat
On Tue, Mar 05, 2019 at 01:48:27PM +0100, Michał Winiarski wrote:
> There are still some cases where userspace needs to change the
> preemption granularity for compute workloads. Let's whitelist the
> per-ctx granularity control register to allow it.
We are not planning to enable it just yet but would be good to easily
enable it in the future.
Acked-by: Rafael Antognolli <rafael.antognolli@intel.com>
> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Anuj Phogat <anuj.phogat@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 2fba33509f4e..582f554e53f4 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -1053,6 +1053,9 @@ static void icl_whitelist_build(struct i915_wa_list *w)
>
> /* WaAllowUMDToModifySamplerMode:icl */
> whitelist_reg(w, GEN10_SAMPLER_MODE);
> +
> + /* WaEnablePreemptionGranularityControlByUMD:icl */
> + whitelist_reg(w, GEN8_CS_CHICKEN1);
> }
>
> void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> --
> 2.20.1
>
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads
2019-03-05 12:48 [PATCH 1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads Michał Winiarski
` (3 preceding siblings ...)
2019-03-05 17:30 ` [PATCH 1/2] " Rafael Antognolli
@ 2019-03-05 17:37 ` Anuj Phogat
4 siblings, 0 replies; 14+ messages in thread
From: Anuj Phogat @ 2019-03-05 17:37 UTC (permalink / raw)
To: Michał Winiarski; +Cc: Intel GFX, Anuj Phogat
Fixes multiple gpu hangs in piglit and vulkancts.
Both patches are:
Tested-by: Anuj Phogat <anuj.phogat@intel.com>
On Tue, Mar 5, 2019 at 4:48 AM Michał Winiarski
<michal.winiarski@intel.com> wrote:
>
> We assumed that the default preemption granularity is fine for ICL.
> Unfortunately, it turns out that some drivers don't support mid-thread
> preemption for compute workloads.
> If a workload that doesn't support mid-thread preemption gets mid-thread
> preempted, we're going to observe a GPU hang.
> While I'm here, let's also update the "workaround" naming.
>
> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Anuj Phogat <anuj.phogat@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Tested-by: Anuj Phogat <anuj.phogat@intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_workarounds.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 89b4007d5200..2fba33509f4e 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -555,6 +555,11 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine)
> GEN10_CACHE_MODE_SS,
> 0, /* write-only, so skip validation */
> _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE));
> +
> + /* WaDisableGPGPUMidThreadPreemption:icl */
> + WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
> + GEN9_PREEMPT_GPGPU_LEVEL_MASK,
> + GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
> }
>
> void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
> @@ -1162,8 +1167,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> GEN7_DISABLE_SAMPLER_PREFETCH);
> }
>
> - if (IS_GEN(i915, 9) || IS_CANNONLAKE(i915)) {
> - /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl */
> + if (IS_GEN_RANGE(i915, 9, 11)) {
> + /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl */
> wa_masked_en(wal,
> GEN7_FF_SLICE_CS_CHICKEN1,
> GEN9_FFSC_PERCTX_PREEMPT_CTRL);
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/2] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD
2019-03-05 12:48 ` [PATCH 2/2] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD Michał Winiarski
2019-03-05 17:31 ` Rafael Antognolli
@ 2019-03-05 18:41 ` Chris Wilson
1 sibling, 0 replies; 14+ messages in thread
From: Chris Wilson @ 2019-03-05 18:41 UTC (permalink / raw)
To: Michał Winiarski, intel-gfx; +Cc: Anuj Phogat
Quoting Michał Winiarski (2019-03-05 12:48:27)
> There are still some cases where userspace needs to change the
> preemption granularity for compute workloads. Let's whitelist the
> per-ctx granularity control register to allow it.
>
> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Anuj Phogat <anuj.phogat@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
Trusting that since it was context saved on earlier gen, it remains so.
(One more selftest to write.)
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads
2019-03-05 17:30 ` [PATCH 1/2] " Rafael Antognolli
@ 2019-03-05 19:10 ` Chris Wilson
2019-03-06 11:20 ` Joonas Lahtinen
0 siblings, 1 reply; 14+ messages in thread
From: Chris Wilson @ 2019-03-05 19:10 UTC (permalink / raw)
To: Michał Winiarski, Rafael Antognolli; +Cc: intel-gfx, Anuj Phogat
Quoting Rafael Antognolli (2019-03-05 17:30:00)
> On Tue, Mar 05, 2019 at 01:48:26PM +0100, Michał Winiarski wrote:
> > We assumed that the default preemption granularity is fine for ICL.
> > Unfortunately, it turns out that some drivers don't support mid-thread
> > preemption for compute workloads.
> > If a workload that doesn't support mid-thread preemption gets mid-thread
> > preempted, we're going to observe a GPU hang.
> > While I'm here, let's also update the "workaround" naming.
>
> Yeah, in Mesa we are not implementing the SIP, so we can't do
> thread-level preemption yet and need the granularity to be no higher
> than thread group level.
>
> Acked-by: Rafael Antognolli <rafael.antognolli@intel.com>
>
> > Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> > Cc: Anuj Phogat <anuj.phogat@intel.com>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > Tested-by: Anuj Phogat <anuj.phogat@intel.com>
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
And pushed, thanks everyone for the testing and reviewed. I've held off
on pushing the second patch as we just want to double check that the
whitelisting is required.
-Chris
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads
2019-03-05 19:10 ` Chris Wilson
@ 2019-03-06 11:20 ` Joonas Lahtinen
2020-03-03 18:31 ` [Intel-gfx] " Jason Ekstrand
0 siblings, 1 reply; 14+ messages in thread
From: Joonas Lahtinen @ 2019-03-06 11:20 UTC (permalink / raw)
To: Michał Winiarski, Chris Wilson, Rafael Antognolli
Cc: intel-gfx, Anuj Phogat
Quoting Chris Wilson (2019-03-05 21:10:42)
> Quoting Rafael Antognolli (2019-03-05 17:30:00)
> > On Tue, Mar 05, 2019 at 01:48:26PM +0100, Michał Winiarski wrote:
> > > We assumed that the default preemption granularity is fine for ICL.
> > > Unfortunately, it turns out that some drivers don't support mid-thread
> > > preemption for compute workloads.
> > > If a workload that doesn't support mid-thread preemption gets mid-thread
> > > preempted, we're going to observe a GPU hang.
> > > While I'm here, let's also update the "workaround" naming.
> >
> > Yeah, in Mesa we are not implementing the SIP, so we can't do
> > thread-level preemption yet and need the granularity to be no higher
> > than thread group level.
> >
> > Acked-by: Rafael Antognolli <rafael.antognolli@intel.com>
> >
> > > Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> > > Cc: Anuj Phogat <anuj.phogat@intel.com>
> > > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > > Tested-by: Anuj Phogat <anuj.phogat@intel.com>
> > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> And pushed, thanks everyone for the testing and reviewed. I've held off
> on pushing the second patch as we just want to double check that the
> whitelisting is required.
Yeah, we should only need to push it once there is an actual consumer
that will enable it.
Regards, Joonas
> -Chris
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads
2019-03-06 11:20 ` Joonas Lahtinen
@ 2020-03-03 18:31 ` Jason Ekstrand
0 siblings, 0 replies; 14+ messages in thread
From: Jason Ekstrand @ 2020-03-03 18:31 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: Intel GFX, Anuj Phogat
FYI: For compute shaders, we have a bit in INTERFACE_DESCRIPTOR_DATA
for this which we can set from userspace without whitelisting a
register. If drivers can't handle mid-thread, they should just set
that bit. Unless we can mid-thread preempt media or 3D which don't
have such a bit in which case maybe we need to do something in the
kernel.
--Jason
On Wed, Mar 6, 2019 at 5:20 AM Joonas Lahtinen
<joonas.lahtinen@linux.intel.com> wrote:
>
> Quoting Chris Wilson (2019-03-05 21:10:42)
> > Quoting Rafael Antognolli (2019-03-05 17:30:00)
> > > On Tue, Mar 05, 2019 at 01:48:26PM +0100, Michał Winiarski wrote:
> > > > We assumed that the default preemption granularity is fine for ICL.
> > > > Unfortunately, it turns out that some drivers don't support mid-thread
> > > > preemption for compute workloads.
> > > > If a workload that doesn't support mid-thread preemption gets mid-thread
> > > > preempted, we're going to observe a GPU hang.
> > > > While I'm here, let's also update the "workaround" naming.
> > >
> > > Yeah, in Mesa we are not implementing the SIP, so we can't do
> > > thread-level preemption yet and need the granularity to be no higher
> > > than thread group level.
> > >
> > > Acked-by: Rafael Antognolli <rafael.antognolli@intel.com>
> > >
> > > > Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> > > > Cc: Anuj Phogat <anuj.phogat@intel.com>
> > > > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > > > Tested-by: Anuj Phogat <anuj.phogat@intel.com>
> > > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >
> > And pushed, thanks everyone for the testing and reviewed. I've held off
> > on pushing the second patch as we just want to double check that the
> > whitelisting is required.
>
> Yeah, we should only need to push it once there is an actual consumer
> that will enable it.
>
> Regards, Joonas
>
> > -Chris
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/2] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD
2019-02-27 15:51 ` [PATCH 2/2] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD Michał Winiarski
2019-02-27 15:59 ` Chris Wilson
@ 2019-02-27 16:03 ` Chris Wilson
1 sibling, 0 replies; 14+ messages in thread
From: Chris Wilson @ 2019-02-27 16:03 UTC (permalink / raw)
To: Michał Winiarski, intel-gfx; +Cc: Anuj Phogat
Quoting Michał Winiarski (2019-02-27 15:51:09)
> There are still some cases where userspace needs to change the
> preemption granularity for compute workloads. Let's whitelist the
> per-ctx granularity control register to allow it.
>
> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Anuj Phogat <anuj.phogat@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> ---
> drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index a19e1c0052a7..1aa167415096 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -1057,6 +1057,9 @@ static void icl_whitelist_build(struct i915_wa_list *w)
>
> /* WaAllowUMDToModifySamplerMode:icl */
> whitelist_reg(w, GEN10_SAMPLER_MODE);
> +
> + /* WaEnablePreemptionGranularityControlByUMD:icl */
> + whitelist_reg(w, GEN8_CS_CHICKEN1);
Whilst you are here, I have a task to add a quick little test to check
to make sure that "userspace" can actually write to the whitelisted
register. Or at least review the selftest and fill in a few gaps.
-Chris
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/2] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD
2019-02-27 15:51 ` [PATCH 2/2] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD Michał Winiarski
@ 2019-02-27 15:59 ` Chris Wilson
2019-02-27 16:03 ` Chris Wilson
1 sibling, 0 replies; 14+ messages in thread
From: Chris Wilson @ 2019-02-27 15:59 UTC (permalink / raw)
To: Michał Winiarski, intel-gfx; +Cc: Anuj Phogat
Quoting Michał Winiarski (2019-02-27 15:51:09)
> There are still some cases where userspace needs to change the
> preemption granularity for compute workloads. Let's whitelist the
> per-ctx granularity control register to allow it.
Just wondering aloud if this should a single patch; change the default
and allow userspace to opt-in in a single switch.
-Chris
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 2/2] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD
2019-02-27 15:51 Michał Winiarski
@ 2019-02-27 15:51 ` Michał Winiarski
2019-02-27 15:59 ` Chris Wilson
2019-02-27 16:03 ` Chris Wilson
0 siblings, 2 replies; 14+ messages in thread
From: Michał Winiarski @ 2019-02-27 15:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Anuj Phogat
There are still some cases where userspace needs to change the
preemption granularity for compute workloads. Let's whitelist the
per-ctx granularity control register to allow it.
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Anuj Phogat <anuj.phogat@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
---
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index a19e1c0052a7..1aa167415096 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -1057,6 +1057,9 @@ static void icl_whitelist_build(struct i915_wa_list *w)
/* WaAllowUMDToModifySamplerMode:icl */
whitelist_reg(w, GEN10_SAMPLER_MODE);
+
+ /* WaEnablePreemptionGranularityControlByUMD:icl */
+ whitelist_reg(w, GEN8_CS_CHICKEN1);
}
void intel_engine_init_whitelist(struct intel_engine_cs *engine)
--
2.20.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
end of thread, other threads:[~2020-03-03 18:31 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-05 12:48 [PATCH 1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads Michał Winiarski
2019-03-05 12:48 ` [PATCH 2/2] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD Michał Winiarski
2019-03-05 17:31 ` Rafael Antognolli
2019-03-05 18:41 ` Chris Wilson
2019-03-05 13:45 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads Patchwork
2019-03-05 14:48 ` ✓ Fi.CI.IGT: " Patchwork
2019-03-05 17:30 ` [PATCH 1/2] " Rafael Antognolli
2019-03-05 19:10 ` Chris Wilson
2019-03-06 11:20 ` Joonas Lahtinen
2020-03-03 18:31 ` [Intel-gfx] " Jason Ekstrand
2019-03-05 17:37 ` Anuj Phogat
-- strict thread matches above, loose matches on Subject: below --
2019-02-27 15:51 Michał Winiarski
2019-02-27 15:51 ` [PATCH 2/2] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD Michał Winiarski
2019-02-27 15:59 ` Chris Wilson
2019-02-27 16:03 ` Chris Wilson
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