From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v11 1/9] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10
Date: Thu, 7 Mar 2019 08:30:50 +0000 [thread overview]
Message-ID: <1551947450.9744.39.camel@intel.com> (raw)
In-Reply-To: <9555051b-24ca-5cad-1f7b-4fa392e7ae66@denx.de>
On Thu, 2019-03-07 at 09:18 +0100, Marek Vasut wrote:
> On 3/7/19 8:51 AM, Chee, Tien Fong wrote:
> >
> > On Tue, 2019-03-05 at 13:12 -0600, Dinh Nguyen wrote:
> > >
> > > Curious, you sent out 3 versions(2x v10, and v11) within ~2
> > > hours.
> > > What
> > > versions should we be reviewing?
> > 2nd version of v10 was resent quickly after request from Dalon to
> > change the node names. I have comment on the 1st version v10 cover
> > letter to void the whole series since no review starting yet.
> >
> > After that, Marek told me to resend in v11.
> That is not true, I merely asked whether the v10 that was reposted is
> actually v11 .
Ohh...sorry for misunderstanding, i thought you was asking me to resend
v11 if there are any changes on v10.
>
> >
> > Sorry for any confusion, please help to review v11, this series of
> > patches mainly resolved some comments from Simek on [v9]: https://w
> > ww.m
> > ail-archive.com/u-boot at lists.denx.de/msg316086.html and node names
> > changed on patch [2/9]
> > >
> > >
> > > On 3/5/19 10:23 AM, tien.fong.chee at intel.com wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > >
> > > > This patch adds description on properties about file name used
> > > > for
> > > > both
> > > > peripheral bitstream and core bitstream.
> > > >
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>
next prev parent reply other threads:[~2019-03-07 8:30 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-05 16:23 [U-Boot] [PATCH v11 0/9] Add support for loading FPGA bitstream tien.fong.chee at intel.com
2019-03-05 16:23 ` [U-Boot] [PATCH v11 1/9] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 tien.fong.chee at intel.com
2019-03-05 19:12 ` Dinh Nguyen
2019-03-07 7:51 ` Chee, Tien Fong
2019-03-07 8:18 ` Marek Vasut
2019-03-07 8:30 ` Chee, Tien Fong [this message]
2019-03-07 8:38 ` Marek Vasut
2019-03-07 8:56 ` Chee, Tien Fong
2019-03-05 16:23 ` [U-Boot] [PATCH v11 2/9] ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK tien.fong.chee at intel.com
2019-03-05 16:23 ` [U-Boot] [PATCH v11 3/9] ARM: socfpga: Cleaning up the messages tien.fong.chee at intel.com
2019-03-06 4:31 ` Dinh Nguyen
2019-03-07 7:57 ` Chee, Tien Fong
2019-03-05 16:23 ` [U-Boot] [PATCH v11 4/9] ARM: socfpga: Move the watchdog reset to the looping location tien.fong.chee at intel.com
2019-03-06 4:35 ` Dinh Nguyen
2019-03-07 8:04 ` Chee, Tien Fong
2019-03-05 16:23 ` [U-Boot] [PATCH v11 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading tien.fong.chee at intel.com
2019-03-05 16:23 ` [U-Boot] [PATCH v11 6/9] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK tien.fong.chee at intel.com
2019-03-06 4:11 ` Dinh Nguyen
2019-03-07 8:06 ` Chee, Tien Fong
2019-03-05 16:23 ` [U-Boot] [PATCH v11 7/9] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs tien.fong.chee at intel.com
2019-03-05 16:23 ` [U-Boot] [PATCH v11 8/9] ARM: socfpga: Synchronize the configuration for A10 SoCDK tien.fong.chee at intel.com
2019-03-06 4:54 ` Dinh Nguyen
2019-03-07 8:14 ` Chee, Tien Fong
2019-03-05 16:23 ` [U-Boot] [PATCH v11 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL tien.fong.chee at intel.com
2019-03-05 20:05 ` Simon Goldschmidt
2019-03-06 2:04 ` Chee, Tien Fong
2019-03-07 7:07 ` Chee, Tien Fong
2019-03-07 8:10 ` Simon Goldschmidt
2019-03-07 8:32 ` Chee, Tien Fong
2019-03-06 4:52 ` Dinh Nguyen
2019-03-07 8:24 ` Chee, Tien Fong
2019-03-07 15:33 ` Dinh Nguyen
2019-03-08 4:36 ` Chee, Tien Fong
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