* [U-Boot] [PATCH 1/4] pinctrl: at91: add option to use drive strength bits
2019-03-25 10:33 [U-Boot] [PATCH 0/4] add drive strenght and slew rate support for SAM9X60 Claudiu.Beznea at microchip.com
@ 2019-03-25 10:33 ` Claudiu.Beznea at microchip.com
2019-03-25 10:33 ` [U-Boot] [PATCH 2/4] pinctrl: at91: add drive strength support for SAM9X60 Claudiu.Beznea at microchip.com
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Claudiu.Beznea at microchip.com @ 2019-03-25 10:33 UTC (permalink / raw)
To: u-boot
From: Claudiu Beznea <claudiu.beznea@microchip.com>
SAM9X60 uses high and low drive strengths. To implement this, in
at91_pinctrl_mux_ops::set_drivestrength we need bit numbers of
drive strengths (1 for low, 2 for high), thus change the code to
allow the usage of drive strength bit numbers.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
drivers/pinctrl/pinctrl-at91.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 4bdad62dc906..8997732376e4 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -50,10 +50,15 @@ struct at91_pinctrl_priv {
* DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
* strength when there is no dt config for it.
*/
-#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
-#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
-#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
-#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
+enum drive_strength_bit {
+ DRIVE_STRENGTH_BIT_DEF,
+ DRIVE_STRENGTH_BIT_LOW,
+ DRIVE_STRENGTH_BIT_MED,
+ DRIVE_STRENGTH_BIT_HI,
+};
+
+#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
+ DRIVE_STRENGTH_SHIFT)
enum at91_mux {
AT91_MUX_GPIO = 0,
@@ -238,7 +243,7 @@ static void at91_mux_sam9x5_set_drivestrength(struct at91_port *pio,
/* strength is inverse on SAM9x5s with our defines
* 0 = hi, 1 = med, 2 = low, 3 = rsvd */
- setting = DRIVE_STRENGTH_HI - setting;
+ setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
set_drive_strength(reg, pin, setting);
}
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [U-Boot] [PATCH 2/4] pinctrl: at91: add drive strength support for SAM9X60
2019-03-25 10:33 [U-Boot] [PATCH 0/4] add drive strenght and slew rate support for SAM9X60 Claudiu.Beznea at microchip.com
2019-03-25 10:33 ` [U-Boot] [PATCH 1/4] pinctrl: at91: add option to use drive strength bits Claudiu.Beznea at microchip.com
@ 2019-03-25 10:33 ` Claudiu.Beznea at microchip.com
2019-03-25 10:33 ` [U-Boot] [PATCH 3/4] pinctrl: at91: add compatibles for SAM9X60 pin controller Claudiu.Beznea at microchip.com
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Claudiu.Beznea at microchip.com @ 2019-03-25 10:33 UTC (permalink / raw)
To: u-boot
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Add drive strength support for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
drivers/pinctrl/pinctrl-at91.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 8997732376e4..134ee851d978 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -248,6 +248,28 @@ static void at91_mux_sam9x5_set_drivestrength(struct at91_port *pio,
set_drive_strength(reg, pin, setting);
}
+static void at91_mux_sam9x60_set_drivestrength(struct at91_port *pio, u32 pin,
+ u32 setting)
+{
+ void *reg = &pio->driver12;
+ u32 tmp;
+
+ if (setting <= DRIVE_STRENGTH_BIT_DEF ||
+ setting == DRIVE_STRENGTH_BIT_MED ||
+ setting > DRIVE_STRENGTH_BIT_HI)
+ return;
+
+ tmp = readl(reg);
+
+ /* Strength is 0: low, 1: hi */
+ if (setting == DRIVE_STRENGTH_BIT_LOW)
+ tmp &= ~BIT(pin);
+ else
+ tmp |= BIT(pin);
+
+ writel(tmp, reg);
+}
+
static struct at91_pinctrl_mux_ops at91rm9200_ops = {
.mux_A_periph = at91_mux_set_A_periph,
.mux_B_periph = at91_mux_set_B_periph,
@@ -278,6 +300,18 @@ static struct at91_pinctrl_mux_ops sama5d3_ops = {
.set_drivestrength = at91_mux_sama5d3_set_drivestrength,
};
+static struct at91_pinctrl_mux_ops sam9x60_ops = {
+ .mux_A_periph = at91_mux_pio3_set_A_periph,
+ .mux_B_periph = at91_mux_pio3_set_B_periph,
+ .mux_C_periph = at91_mux_pio3_set_C_periph,
+ .mux_D_periph = at91_mux_pio3_set_D_periph,
+ .set_deglitch = at91_mux_pio3_set_deglitch,
+ .set_debounce = at91_mux_pio3_set_debounce,
+ .set_pulldown = at91_mux_pio3_set_pulldown,
+ .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
+ .set_drivestrength = at91_mux_sam9x60_set_drivestrength,
+};
+
static void at91_mux_gpio_disable(struct at91_port *pio, u32 mask)
{
writel(mask, &pio->pdr);
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [U-Boot] [PATCH 3/4] pinctrl: at91: add compatibles for SAM9X60 pin controller
2019-03-25 10:33 [U-Boot] [PATCH 0/4] add drive strenght and slew rate support for SAM9X60 Claudiu.Beznea at microchip.com
2019-03-25 10:33 ` [U-Boot] [PATCH 1/4] pinctrl: at91: add option to use drive strength bits Claudiu.Beznea at microchip.com
2019-03-25 10:33 ` [U-Boot] [PATCH 2/4] pinctrl: at91: add drive strength support for SAM9X60 Claudiu.Beznea at microchip.com
@ 2019-03-25 10:33 ` Claudiu.Beznea at microchip.com
2019-03-25 10:34 ` [U-Boot] [PATCH 4/4] pinctrl: at91: add slewrate support for SAM9X60 Claudiu.Beznea at microchip.com
2019-04-08 6:04 ` [U-Boot] [PATCH 0/4] add drive strenght and slew rate " Eugen.Hristev at microchip.com
4 siblings, 0 replies; 6+ messages in thread
From: Claudiu.Beznea at microchip.com @ 2019-03-25 10:33 UTC (permalink / raw)
To: u-boot
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Add compatibles for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
drivers/pinctrl/pinctrl-at91.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 134ee851d978..62ee7668ab17 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -479,6 +479,7 @@ static const struct udevice_id at91_pinctrl_match[] = {
{ .compatible = "atmel,sama5d3-pinctrl", .data = (ulong)&sama5d3_ops },
{ .compatible = "atmel,at91sam9x5-pinctrl", .data = (ulong)&at91sam9x5_ops },
{ .compatible = "atmel,at91rm9200-pinctrl", .data = (ulong)&at91rm9200_ops },
+ { .compatible = "microchip,sam9x60-pinctrl", .data = (ulong)&sam9x60_ops },
{}
};
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [U-Boot] [PATCH 4/4] pinctrl: at91: add slewrate support for SAM9X60
2019-03-25 10:33 [U-Boot] [PATCH 0/4] add drive strenght and slew rate support for SAM9X60 Claudiu.Beznea at microchip.com
` (2 preceding siblings ...)
2019-03-25 10:33 ` [U-Boot] [PATCH 3/4] pinctrl: at91: add compatibles for SAM9X60 pin controller Claudiu.Beznea at microchip.com
@ 2019-03-25 10:34 ` Claudiu.Beznea at microchip.com
2019-04-08 6:04 ` [U-Boot] [PATCH 0/4] add drive strenght and slew rate " Eugen.Hristev at microchip.com
4 siblings, 0 replies; 6+ messages in thread
From: Claudiu.Beznea at microchip.com @ 2019-03-25 10:34 UTC (permalink / raw)
To: u-boot
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Add slew rate support for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
drivers/pinctrl/pinctrl-at91.c | 34 ++++++++++++++++++++++++++++++++++
include/dt-bindings/pinctrl/at91.h | 4 ++++
2 files changed, 38 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 62ee7668ab17..27f274ff0224 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -37,6 +37,9 @@ struct at91_pinctrl_priv {
#define OUTPUT BIT(7)
#define OUTPUT_VAL_SHIFT 8
#define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT)
+#define SLEWRATE_SHIFT 9
+#define SLEWRATE_MASK 0x1
+#define SLEWRATE (SLEWRATE_MASK << SLEWRATE_SHIFT)
#define DEBOUNCE BIT(16)
#define DEBOUNCE_VAL_SHIFT 17
#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
@@ -60,6 +63,13 @@ enum drive_strength_bit {
#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
DRIVE_STRENGTH_SHIFT)
+enum slewrate_bit {
+ SLEWRATE_BIT_DIS,
+ SLEWRATE_BIT_ENA,
+};
+
+#define SLEWRATE_BIT_MSK(name) (SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
+
enum at91_mux {
AT91_MUX_GPIO = 0,
AT91_MUX_PERIPH_A = 1,
@@ -95,6 +105,7 @@ struct at91_pinctrl_mux_ops {
void (*disable_schmitt_trig)(struct at91_port *pio, u32 mask);
void (*set_drivestrength)(struct at91_port *pio, u32 pin,
u32 strength);
+ void (*set_slewrate)(struct at91_port *pio, u32 pin, u32 slewrate);
};
static u32 two_bit_pin_value_shift_amount(u32 pin)
@@ -270,6 +281,25 @@ static void at91_mux_sam9x60_set_drivestrength(struct at91_port *pio, u32 pin,
writel(tmp, reg);
}
+static void at91_mux_sam9x60_set_slewrate(struct at91_port *pio, u32 pin,
+ u32 setting)
+{
+ void *reg = &pio->reserved12[3];
+ u32 tmp;
+
+ if (setting < SLEWRATE_BIT_DIS || setting > SLEWRATE_BIT_ENA)
+ return;
+
+ tmp = readl(reg);
+
+ if (setting == SLEWRATE_BIT_DIS)
+ tmp &= ~BIT(pin);
+ else
+ tmp |= BIT(pin);
+
+ writel(tmp, reg);
+}
+
static struct at91_pinctrl_mux_ops at91rm9200_ops = {
.mux_A_periph = at91_mux_set_A_periph,
.mux_B_periph = at91_mux_set_B_periph,
@@ -310,6 +340,7 @@ static struct at91_pinctrl_mux_ops sam9x60_ops = {
.set_pulldown = at91_mux_pio3_set_pulldown,
.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
.set_drivestrength = at91_mux_sam9x60_set_drivestrength,
+ .set_slewrate = at91_mux_sam9x60_set_slewrate,
};
static void at91_mux_gpio_disable(struct at91_port *pio, u32 mask)
@@ -378,6 +409,9 @@ static int at91_pinconf_set(struct at91_pinctrl_mux_ops *ops,
if (ops->set_drivestrength)
ops->set_drivestrength(pio, pin,
(config & DRIVE_STRENGTH) >> DRIVE_STRENGTH_SHIFT);
+ if (ops->set_slewrate)
+ ops->set_slewrate(pio, pin,
+ (config & SLEWRATE) >> SLEWRATE_SHIFT);
return 0;
}
diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h
index 2732d6c0fb39..616f5ce40079 100644
--- a/include/dt-bindings/pinctrl/at91.h
+++ b/include/dt-bindings/pinctrl/at91.h
@@ -17,6 +17,7 @@
#define AT91_PINCTRL_DIS_SCHMIT (1 << 4)
#define AT91_PINCTRL_OUTPUT (1 << 7)
#define AT91_PINCTRL_OUTPUT_VAL(x) ((x & 0x1) << 8)
+#define AT91_PINCTRL_SLEWRATE (1 << 9)
#define AT91_PINCTRL_DEBOUNCE (1 << 16)
#define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17)
@@ -27,6 +28,9 @@
#define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5)
#define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5)
+#define AT91_PINCTRL_SLEWRATE_DIS (0x0 << 9)
+#define AT91_PINCTRL_SLEWRATE_ENA (0x1 << 9)
+
#define AT91_PIOA 0
#define AT91_PIOB 1
#define AT91_PIOC 2
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [U-Boot] [PATCH 0/4] add drive strenght and slew rate support for SAM9X60
2019-03-25 10:33 [U-Boot] [PATCH 0/4] add drive strenght and slew rate support for SAM9X60 Claudiu.Beznea at microchip.com
` (3 preceding siblings ...)
2019-03-25 10:34 ` [U-Boot] [PATCH 4/4] pinctrl: at91: add slewrate support for SAM9X60 Claudiu.Beznea at microchip.com
@ 2019-04-08 6:04 ` Eugen.Hristev at microchip.com
4 siblings, 0 replies; 6+ messages in thread
From: Eugen.Hristev at microchip.com @ 2019-04-08 6:04 UTC (permalink / raw)
To: u-boot
On 25.03.2019 12:33, Claudiu.Beznea at microchip.com wrote:
> From: Claudiu Beznea <claudiu.beznea@microchip.com>
>
> Hi,
>
> This series adds support for drive strength and slew rate support for
> Microchip SAMX60's pin controller. For drive strenght we could have 2
> values: low, high. For slew rate we could have 2 values: enable, disabled.
>
> Thank you,
> Claudiu Beznea
>
> Claudiu Beznea (4):
> pinctrl: at91: add option to use drive strength bits
> pinctrl: at91: add drive strength support for SAM9X60
> pinctrl: at91: add compatibles for SAM9X60 pin controller
> pinctrl: at91: add slewrate support for SAM9X60
>
> drivers/pinctrl/pinctrl-at91.c | 84 +++++++++++++++++++++++++++++++++++---
> include/dt-bindings/pinctrl/at91.h | 4 ++
> 2 files changed, 83 insertions(+), 5 deletions(-)
Applied the whole series to u-boot-atmel/next
Thanks !
^ permalink raw reply [flat|nested] 6+ messages in thread