* [v6][PATCH 01/12] drm/i915: Introduce vfunc read_luts() to create hw lut
2019-05-14 9:43 [PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
@ 2019-05-14 9:43 ` Swati Sharma
2019-05-14 15:23 ` Ville Syrjälä
2019-05-14 9:43 ` [v6][PATCH 02/12] drm/i915: Enable intel_color_get_config() Swati Sharma
` (18 subsequent siblings)
19 siblings, 1 reply; 26+ messages in thread
From: Swati Sharma @ 2019-05-14 9:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
In this patch, a vfunc read_luts() is introduced to create a hw lut
i.e. lut having values read from gamma/degamma registers which will
later be used to compare with sw lut to validate gamma/degamma lut values.
v3: -Rebase
v4: -Renamed intel_get_color_config to intel_color_get_config [Jani]
-Wrapped get_color_config() [Jani]
v5: -Renamed intel_color_get_config() to intel_color_read_luts()
-Renamed get_color_config to read_luts
v6: -Renamed intel_color_read_luts() back to intel_color_get_config()
[Jani and Ville]
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_color.c | 8 ++++++++
drivers/gpu/drm/i915/intel_color.h | 1 +
3 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d025780..6343e70 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -343,6 +343,7 @@ struct drm_i915_display_funcs {
* involved with the same commit.
*/
void (*load_luts)(const struct intel_crtc_state *crtc_state);
+ void (*read_luts)(struct intel_crtc_state *crtc_state);
};
struct intel_csr {
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 962db12..50b98ee 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -879,6 +879,14 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
return dev_priv->display.color_check(crtc_state);
}
+void intel_color_get_config(struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+
+ if (dev_priv->display.read_luts)
+ dev_priv->display.read_luts(crtc_state);
+}
+
static bool need_plane_update(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state)
{
diff --git a/drivers/gpu/drm/i915/intel_color.h b/drivers/gpu/drm/i915/intel_color.h
index b8a3ce6..057e8ac 100644
--- a/drivers/gpu/drm/i915/intel_color.h
+++ b/drivers/gpu/drm/i915/intel_color.h
@@ -13,5 +13,6 @@
int intel_color_check(struct intel_crtc_state *crtc_state);
void intel_color_commit(const struct intel_crtc_state *crtc_state);
void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
+void intel_color_get_config(struct intel_crtc_state *crtc_state);
#endif /* __INTEL_COLOR_H__ */
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [v6][PATCH 01/12] drm/i915: Introduce vfunc read_luts() to create hw lut
2019-05-14 9:43 ` [v6][PATCH 01/12] drm/i915: Introduce vfunc read_luts() to create hw lut Swati Sharma
@ 2019-05-14 15:23 ` Ville Syrjälä
2019-05-15 7:45 ` Jani Nikula
0 siblings, 1 reply; 26+ messages in thread
From: Ville Syrjälä @ 2019-05-14 15:23 UTC (permalink / raw)
To: Swati Sharma; +Cc: jani.nikula, intel-gfx
On Tue, May 14, 2019 at 03:13:19PM +0530, Swati Sharma wrote:
> In this patch, a vfunc read_luts() is introduced to create a hw lut
> i.e. lut having values read from gamma/degamma registers which will
> later be used to compare with sw lut to validate gamma/degamma lut values.
>
> v3: -Rebase
> v4: -Renamed intel_get_color_config to intel_color_get_config [Jani]
> -Wrapped get_color_config() [Jani]
> v5: -Renamed intel_color_get_config() to intel_color_read_luts()
> -Renamed get_color_config to read_luts
> v6: -Renamed intel_color_read_luts() back to intel_color_get_config()
> [Jani and Ville]
>
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_color.c | 8 ++++++++
> drivers/gpu/drm/i915/intel_color.h | 1 +
> 3 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d025780..6343e70 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -343,6 +343,7 @@ struct drm_i915_display_funcs {
> * involved with the same commit.
> */
> void (*load_luts)(const struct intel_crtc_state *crtc_state);
> + void (*read_luts)(struct intel_crtc_state *crtc_state);
I think Jani wanted the entire vfunc renamed back.
> };
>
> struct intel_csr {
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 962db12..50b98ee 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -879,6 +879,14 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
> return dev_priv->display.color_check(crtc_state);
> }
>
> +void intel_color_get_config(struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +
> + if (dev_priv->display.read_luts)
> + dev_priv->display.read_luts(crtc_state);
> +}
> +
> static bool need_plane_update(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state)
> {
> diff --git a/drivers/gpu/drm/i915/intel_color.h b/drivers/gpu/drm/i915/intel_color.h
> index b8a3ce6..057e8ac 100644
> --- a/drivers/gpu/drm/i915/intel_color.h
> +++ b/drivers/gpu/drm/i915/intel_color.h
> @@ -13,5 +13,6 @@
> int intel_color_check(struct intel_crtc_state *crtc_state);
> void intel_color_commit(const struct intel_crtc_state *crtc_state);
> void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
> +void intel_color_get_config(struct intel_crtc_state *crtc_state);
>
> #endif /* __INTEL_COLOR_H__ */
> --
> 1.9.1
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [v6][PATCH 01/12] drm/i915: Introduce vfunc read_luts() to create hw lut
2019-05-14 15:23 ` Ville Syrjälä
@ 2019-05-15 7:45 ` Jani Nikula
0 siblings, 0 replies; 26+ messages in thread
From: Jani Nikula @ 2019-05-15 7:45 UTC (permalink / raw)
To: Ville Syrjälä, Swati Sharma; +Cc: intel-gfx
On Tue, 14 May 2019, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Tue, May 14, 2019 at 03:13:19PM +0530, Swati Sharma wrote:
>> In this patch, a vfunc read_luts() is introduced to create a hw lut
>> i.e. lut having values read from gamma/degamma registers which will
>> later be used to compare with sw lut to validate gamma/degamma lut values.
>>
>> v3: -Rebase
>> v4: -Renamed intel_get_color_config to intel_color_get_config [Jani]
>> -Wrapped get_color_config() [Jani]
>> v5: -Renamed intel_color_get_config() to intel_color_read_luts()
>> -Renamed get_color_config to read_luts
>> v6: -Renamed intel_color_read_luts() back to intel_color_get_config()
>> [Jani and Ville]
>>
>> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 1 +
>> drivers/gpu/drm/i915/intel_color.c | 8 ++++++++
>> drivers/gpu/drm/i915/intel_color.h | 1 +
>> 3 files changed, 10 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index d025780..6343e70 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -343,6 +343,7 @@ struct drm_i915_display_funcs {
>> * involved with the same commit.
>> */
>> void (*load_luts)(const struct intel_crtc_state *crtc_state);
>> + void (*read_luts)(struct intel_crtc_state *crtc_state);
>
> I think Jani wanted the entire vfunc renamed back.
*shrug* not so important as the main entry point below.
BR,
Jani,
>
>> };
>>
>> struct intel_csr {
>> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
>> index 962db12..50b98ee 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -879,6 +879,14 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
>> return dev_priv->display.color_check(crtc_state);
>> }
>>
>> +void intel_color_get_config(struct intel_crtc_state *crtc_state)
>> +{
>> + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>> +
>> + if (dev_priv->display.read_luts)
>> + dev_priv->display.read_luts(crtc_state);
>> +}
>> +
>> static bool need_plane_update(struct intel_plane *plane,
>> const struct intel_crtc_state *crtc_state)
>> {
>> diff --git a/drivers/gpu/drm/i915/intel_color.h b/drivers/gpu/drm/i915/intel_color.h
>> index b8a3ce6..057e8ac 100644
>> --- a/drivers/gpu/drm/i915/intel_color.h
>> +++ b/drivers/gpu/drm/i915/intel_color.h
>> @@ -13,5 +13,6 @@
>> int intel_color_check(struct intel_crtc_state *crtc_state);
>> void intel_color_commit(const struct intel_crtc_state *crtc_state);
>> void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
>> +void intel_color_get_config(struct intel_crtc_state *crtc_state);
>>
>> #endif /* __INTEL_COLOR_H__ */
>> --
>> 1.9.1
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* [v6][PATCH 02/12] drm/i915: Enable intel_color_get_config()
2019-05-14 9:43 [PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
2019-05-14 9:43 ` [v6][PATCH 01/12] drm/i915: Introduce vfunc read_luts() to create hw lut Swati Sharma
@ 2019-05-14 9:43 ` Swati Sharma
2019-05-14 9:43 ` [v6][PATCH 03/12] drm/i915: Add intel_color_lut_equal() to compare hw and sw gamma/degamma lut values Swati Sharma
` (17 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Swati Sharma @ 2019-05-14 9:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
In this patch, intel_color_get_config() is enabled and support
for read_luts() will be added platform by platform incrementally
in the follow-up patches.
v4: -Renamed intel_get_color_config to intel_color_get_config [Jani]
-Added the user early on such that support for get_color_config()
can be added platform by platform incrementally [Jani]
v5: -Incorrect place for calling intel_color_get_config() in
haswell_get_pipe_config() [Ville]
v6: -Renamed intel_color_read_luts() to intel_color_get_config()
[Jani and Ville]
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 05177f3..3e01028 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8351,6 +8351,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc->pipe));
i9xx_get_pipe_color_config(pipe_config);
+ intel_color_get_config(pipe_config);
if (INTEL_GEN(dev_priv) < 4)
pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
@@ -9426,6 +9427,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
i9xx_get_pipe_color_config(pipe_config);
+ intel_color_get_config(pipe_config);
if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
struct intel_shared_dpll *pll;
@@ -9874,6 +9876,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
i9xx_get_pipe_color_config(pipe_config);
}
+ intel_color_get_config(pipe_config);
+
power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
WARN_ON(power_domain_mask & BIT_ULL(power_domain));
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [v6][PATCH 03/12] drm/i915: Add intel_color_lut_equal() to compare hw and sw gamma/degamma lut values
2019-05-14 9:43 [PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
2019-05-14 9:43 ` [v6][PATCH 01/12] drm/i915: Introduce vfunc read_luts() to create hw lut Swati Sharma
2019-05-14 9:43 ` [v6][PATCH 02/12] drm/i915: Enable intel_color_get_config() Swati Sharma
@ 2019-05-14 9:43 ` Swati Sharma
2019-05-14 16:10 ` Ville Syrjälä
2019-05-14 9:43 ` [v6][PATCH 04/12] drm/i915: Extract i9xx_read_luts() Swati Sharma
` (16 subsequent siblings)
19 siblings, 1 reply; 26+ messages in thread
From: Swati Sharma @ 2019-05-14 9:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
v3: -Rebase
v4: -Renamed intel_compare_color_lut() to intel_color_lut_equal() [Jani]
-Added the default label above the correct label [Jani]
-Corrected smatch warn "variable dereferenced before check" [Dan Carpenter]
v5: -Added condition (!blob1 && !blob2) return true [Jani]
-Called PIPE_CONF_CHECK_COLOR_LUT inside if (!adjust) [Jani]
-Added #undef PIPE_CONF_CHECK_COLOR_LUT [Jani]
v6: -Added func intel_color_get_bit_precision() to get bit precision for
gamma and degamma lut readout depending upon platform and
corresponding to load_luts() [Ankit]
-Added debug log for color para in intel_dump_pipe_config [Jani]
-Made patch11 as patch3 [Jani]
I could think of adding intel_color_get_bit_precision() to be the way
to get away with bit precision problem for degamma and gamma (its like a table
having hard coded values depening on gamma_mode).
If anybody could think of better way then this then please guide.
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/intel_color.c | 93 ++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_color.h | 7 +++
drivers/gpu/drm/i915/intel_display.c | 24 ++++++++++
3 files changed, 124 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 50b98ee..1e60369 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -1251,6 +1251,99 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
return 0;
}
+void intel_color_get_bit_precision(struct intel_crtc_state *crtc_state, int *bp_gamma)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+ if (HAS_GMCH(dev_priv)) {
+ if (IS_CHERRYVIEW(dev_priv)) {
+ if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
+ *bp_gamma = 8;
+ return;
+ }
+ if (crtc_state->cgm_mode == CGM_PIPE_MODE_GAMMA)
+ *bp_gamma = 10;
+ } else if (INTEL_GEN(dev_priv) >= 4) {
+ if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+ *bp_gamma = 8;
+ else
+ *bp_gamma = 16;
+ } else {
+ *bp_gamma = 8;
+ }
+ } else {
+ if (INTEL_GEN(dev_priv) >= 11) {
+ if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
+ GAMMA_MODE_MODE_8BIT)
+ *bp_gamma = 8;
+ else
+ *bp_gamma = 10;
+ } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
+ if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+ *bp_gamma = 8;
+ else
+ *bp_gamma = 10;
+ } else if (INTEL_GEN(dev_priv) >= 7) {
+ if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+ *bp_gamma = 8;
+ else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
+ *bp_gamma = 10;
+ else
+ *bp_gamma = 10;
+ } else {
+ if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+ *bp_gamma = 8;
+ else
+ *bp_gamma = 10;
+ }
+ }
+}
+
+static inline bool err_check(struct drm_color_lut *sw_lut,
+ struct drm_color_lut *hw_lut, u32 err)
+{
+ return ((abs((long)hw_lut->red - sw_lut->red)) <= err) &&
+ ((abs((long)hw_lut->blue - sw_lut->blue)) <= err) &&
+ ((abs((long)hw_lut->green - sw_lut->green)) <= err);
+}
+
+bool intel_color_lut_equal(struct drm_property_blob *blob1,
+ struct drm_property_blob *blob2,
+ u32 bit_precision)
+{
+ struct drm_color_lut *sw_lut, *hw_lut;
+ int sw_lut_size, hw_lut_size, i;
+ u32 err;
+
+ if (!blob1 && !blob2)
+ return true;
+
+ if (!blob1)
+ return true;
+
+ if (!blob2)
+ return false;
+
+ sw_lut_size = drm_color_lut_size(blob1);
+ hw_lut_size = drm_color_lut_size(blob2);
+
+ if (sw_lut_size != hw_lut_size)
+ return false;
+
+ sw_lut = blob1->data;
+ hw_lut = blob2->data;
+
+ err = 0xffff >> bit_precision;
+
+ for (i = 0; i < sw_lut_size; i++) {
+ if (!err_check(&hw_lut[i], &sw_lut[i], err))
+ return false;
+ }
+
+ return true;
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
diff --git a/drivers/gpu/drm/i915/intel_color.h b/drivers/gpu/drm/i915/intel_color.h
index 057e8ac..f2872d3 100644
--- a/drivers/gpu/drm/i915/intel_color.h
+++ b/drivers/gpu/drm/i915/intel_color.h
@@ -6,13 +6,20 @@
#ifndef __INTEL_COLOR_H__
#define __INTEL_COLOR_H__
+#include <linux/types.h>
+
struct intel_crtc_state;
struct intel_crtc;
+struct drm_property_blob;
void intel_color_init(struct intel_crtc *crtc);
int intel_color_check(struct intel_crtc_state *crtc_state);
void intel_color_commit(const struct intel_crtc_state *crtc_state);
void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
void intel_color_get_config(struct intel_crtc_state *crtc_state);
+bool intel_color_lut_equal(struct drm_property_blob *blob1,
+ struct drm_property_blob *blob2,
+ u32 bit_precision);
+void intel_color_get_bit_precision(struct intel_crtc_state *crtc_state, int *bp_gamma);
#endif /* __INTEL_COLOR_H__ */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3e01028..46985c15 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11570,6 +11570,16 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
drm_rect_width(&state->base.dst),
drm_rect_height(&state->base.dst));
}
+
+ if (IS_CHERRYVIEW(dev_priv))
+ DRM_DEBUG_KMS("cgm_mode:%d gamma_mode:%d gamma_enable:%d csc_enable:%d\n",
+ pipe_config->cgm_mode, pipe_config->gamma_mode, pipe_config->gamma_enable,
+ pipe_config->csc_enable);
+ else
+ DRM_DEBUG_KMS("csc_mode:%d gamma_mode:%d gamma_enable:%d csc_enable:%d\n",
+ pipe_config->csc_mode, pipe_config->gamma_mode, pipe_config->gamma_enable,
+ pipe_config->csc_enable);
+
}
static bool check_digital_port_conflicts(struct drm_atomic_state *state)
@@ -11947,6 +11957,7 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
bool adjust)
{
bool ret = true;
+ u32 bp_gamma = 0;
bool fixup_inherited = adjust &&
(current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
!(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
@@ -12098,6 +12109,15 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
} \
} while (0)
+#define PIPE_CONF_CHECK_COLOR_LUT(name, bit_precision) do { \
+ if (!intel_color_lut_equal(current_config->name, \
+ pipe_config->name, bit_precision)) { \
+ pipe_config_err(adjust, __stringify(name), \
+ "hw_state doesn't match sw_state\n"); \
+ ret = false; \
+ } \
+} while (0)
+
#define PIPE_CONF_QUIRK(quirk) \
((current_config->quirks | pipe_config->quirks) & (quirk))
@@ -12193,6 +12213,9 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
PIPE_CONF_CHECK_X(csc_mode);
PIPE_CONF_CHECK_BOOL(gamma_enable);
PIPE_CONF_CHECK_BOOL(csc_enable);
+
+ intel_color_get_bit_precision(pipe_config, &bp_gamma);
+ PIPE_CONF_CHECK_COLOR_LUT(base.gamma_lut, bp_gamma);
}
PIPE_CONF_CHECK_BOOL(double_wide);
@@ -12255,6 +12278,7 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
#undef PIPE_CONF_CHECK_FLAGS
#undef PIPE_CONF_CHECK_CLOCK_FUZZY
#undef PIPE_CONF_QUIRK
+#undef PIPE_CONF_CHECK_COLOR_LUT
return ret;
}
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [v6][PATCH 03/12] drm/i915: Add intel_color_lut_equal() to compare hw and sw gamma/degamma lut values
2019-05-14 9:43 ` [v6][PATCH 03/12] drm/i915: Add intel_color_lut_equal() to compare hw and sw gamma/degamma lut values Swati Sharma
@ 2019-05-14 16:10 ` Ville Syrjälä
2019-05-21 13:42 ` Sharma, Swati2
0 siblings, 1 reply; 26+ messages in thread
From: Ville Syrjälä @ 2019-05-14 16:10 UTC (permalink / raw)
To: Swati Sharma; +Cc: jani.nikula, intel-gfx
On Tue, May 14, 2019 at 03:13:21PM +0530, Swati Sharma wrote:
> v3: -Rebase
> v4: -Renamed intel_compare_color_lut() to intel_color_lut_equal() [Jani]
> -Added the default label above the correct label [Jani]
> -Corrected smatch warn "variable dereferenced before check" [Dan Carpenter]
> v5: -Added condition (!blob1 && !blob2) return true [Jani]
> -Called PIPE_CONF_CHECK_COLOR_LUT inside if (!adjust) [Jani]
> -Added #undef PIPE_CONF_CHECK_COLOR_LUT [Jani]
> v6: -Added func intel_color_get_bit_precision() to get bit precision for
> gamma and degamma lut readout depending upon platform and
> corresponding to load_luts() [Ankit]
> -Added debug log for color para in intel_dump_pipe_config [Jani]
> -Made patch11 as patch3 [Jani]
>
> I could think of adding intel_color_get_bit_precision() to be the way
> to get away with bit precision problem for degamma and gamma (its like a table
> having hard coded values depening on gamma_mode).
> If anybody could think of better way then this then please guide.
>
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> ---
> drivers/gpu/drm/i915/intel_color.c | 93 ++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_color.h | 7 +++
> drivers/gpu/drm/i915/intel_display.c | 24 ++++++++++
> 3 files changed, 124 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 50b98ee..1e60369 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -1251,6 +1251,99 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
> return 0;
> }
>
> +void intel_color_get_bit_precision(struct intel_crtc_state *crtc_state, int *bp_gamma)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +
> + if (HAS_GMCH(dev_priv)) {
> + if (IS_CHERRYVIEW(dev_priv)) {
> + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
> + *bp_gamma = 8;
> + return;
Functions can actually return values.
Not sure I particularly like this function though. We can't fit
the gamma vs. degamm stuff in here neatly. I think per-platform
stuff to determine the precision is required to make this sane.
And it should probably got into intel_color.c to keep things
neatly contained.
Something along the lines of:
i9xx_gamma_precision()
{
if (!gamma_enable)
return 0;
switch (gamma_mode) {
case GAMMA_MODE_MODE_8BIT:
return 8;
case GAMMA_MODE_MODE_10BIT:
return 16;
}
}
chv_gamma_precision()
{
if (cgm_mode & CGM_PIPE_MODE_GAMMA)
return 10;
else
return i9xx_gamma_precision();
}
chv_degamma_precision(crtc_state)
{
if (cgm_mode & CGM_PIPE_MODE_DEGAMMA)
return 14;
else
return 0
}
ilk_gamma_precision()
{
if (!gamma_enable)
return 0;
if ((csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
return 0;
switch (gamma_mode) {
case GAMMA_MODE_MODE_8BIT:
return 8;
case GAMMA_MODE_MODE_10BIT:
return 10;
}
}
ilk_degamma_precision()
{
if (!gamma_enable)
return 0;
if ((csc_mode & CSC_POSITION_BEFORE_GAMMA) != 0)
return 0;
switch (gamma_mode) {
case GAMMA_MODE_MODE_8BIT:
return 8;
case GAMMA_MODE_MODE_10BIT:
return 10;
}
}
... extend to ivb, glk, and icl variants too.
> + }
> + if (crtc_state->cgm_mode == CGM_PIPE_MODE_GAMMA)
> + *bp_gamma = 10;
> + } else if (INTEL_GEN(dev_priv) >= 4) {
> + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> + *bp_gamma = 8;
> + else
> + *bp_gamma = 16;
> + } else {
> + *bp_gamma = 8;
> + }
> + } else {
> + if (INTEL_GEN(dev_priv) >= 11) {
> + if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
> + GAMMA_MODE_MODE_8BIT)
> + *bp_gamma = 8;
> + else
> + *bp_gamma = 10;
> + } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
> + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> + *bp_gamma = 8;
> + else
> + *bp_gamma = 10;
> + } else if (INTEL_GEN(dev_priv) >= 7) {
> + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> + *bp_gamma = 8;
> + else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
> + *bp_gamma = 10;
> + else
> + *bp_gamma = 10;
> + } else {
> + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> + *bp_gamma = 8;
> + else
> + *bp_gamma = 10;
> + }
> + }
> +}
> +
> +static inline bool err_check(struct drm_color_lut *sw_lut,
> + struct drm_color_lut *hw_lut, u32 err)
> +{
> + return ((abs((long)hw_lut->red - sw_lut->red)) <= err) &&
> + ((abs((long)hw_lut->blue - sw_lut->blue)) <= err) &&
> + ((abs((long)hw_lut->green - sw_lut->green)) <= err);
> +}
> +
> +bool intel_color_lut_equal(struct drm_property_blob *blob1,
> + struct drm_property_blob *blob2,
> + u32 bit_precision)
> +{
> + struct drm_color_lut *sw_lut, *hw_lut;
> + int sw_lut_size, hw_lut_size, i;
> + u32 err;
> +
> + if (!blob1 && !blob2)
> + return true;
> +
> + if (!blob1)
> + return true;
> +
> + if (!blob2)
> + return false;
> +
> + sw_lut_size = drm_color_lut_size(blob1);
> + hw_lut_size = drm_color_lut_size(blob2);
> +
> + if (sw_lut_size != hw_lut_size)
> + return false;
> +
> + sw_lut = blob1->data;
> + hw_lut = blob2->data;
> +
> + err = 0xffff >> bit_precision;
> +
> + for (i = 0; i < sw_lut_size; i++) {
> + if (!err_check(&hw_lut[i], &sw_lut[i], err))
> + return false;
> + }
> +
> + return true;
> +}
> +
> void intel_color_init(struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> diff --git a/drivers/gpu/drm/i915/intel_color.h b/drivers/gpu/drm/i915/intel_color.h
> index 057e8ac..f2872d3 100644
> --- a/drivers/gpu/drm/i915/intel_color.h
> +++ b/drivers/gpu/drm/i915/intel_color.h
> @@ -6,13 +6,20 @@
> #ifndef __INTEL_COLOR_H__
> #define __INTEL_COLOR_H__
>
> +#include <linux/types.h>
> +
> struct intel_crtc_state;
> struct intel_crtc;
> +struct drm_property_blob;
>
> void intel_color_init(struct intel_crtc *crtc);
> int intel_color_check(struct intel_crtc_state *crtc_state);
> void intel_color_commit(const struct intel_crtc_state *crtc_state);
> void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
> void intel_color_get_config(struct intel_crtc_state *crtc_state);
> +bool intel_color_lut_equal(struct drm_property_blob *blob1,
> + struct drm_property_blob *blob2,
> + u32 bit_precision);
> +void intel_color_get_bit_precision(struct intel_crtc_state *crtc_state, int *bp_gamma);
>
> #endif /* __INTEL_COLOR_H__ */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3e01028..46985c15 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11570,6 +11570,16 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
> drm_rect_width(&state->base.dst),
> drm_rect_height(&state->base.dst));
> }
> +
> + if (IS_CHERRYVIEW(dev_priv))
> + DRM_DEBUG_KMS("cgm_mode:%d gamma_mode:%d gamma_enable:%d csc_enable:%d\n",
> + pipe_config->cgm_mode, pipe_config->gamma_mode, pipe_config->gamma_enable,
> + pipe_config->csc_enable);
> + else
> + DRM_DEBUG_KMS("csc_mode:%d gamma_mode:%d gamma_enable:%d csc_enable:%d\n",
> + pipe_config->csc_mode, pipe_config->gamma_mode, pipe_config->gamma_enable,
> + pipe_config->csc_enable);
> +
> }
>
> static bool check_digital_port_conflicts(struct drm_atomic_state *state)
> @@ -11947,6 +11957,7 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
> bool adjust)
> {
> bool ret = true;
> + u32 bp_gamma = 0;
> bool fixup_inherited = adjust &&
> (current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
> !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
> @@ -12098,6 +12109,15 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
> } \
> } while (0)
>
> +#define PIPE_CONF_CHECK_COLOR_LUT(name, bit_precision) do { \
> + if (!intel_color_lut_equal(current_config->name, \
> + pipe_config->name, bit_precision)) { \
> + pipe_config_err(adjust, __stringify(name), \
> + "hw_state doesn't match sw_state\n"); \
> + ret = false; \
> + } \
> +} while (0)
> +
> #define PIPE_CONF_QUIRK(quirk) \
> ((current_config->quirks | pipe_config->quirks) & (quirk))
>
> @@ -12193,6 +12213,9 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
> PIPE_CONF_CHECK_X(csc_mode);
> PIPE_CONF_CHECK_BOOL(gamma_enable);
> PIPE_CONF_CHECK_BOOL(csc_enable);
> +
> + intel_color_get_bit_precision(pipe_config, &bp_gamma);
> + PIPE_CONF_CHECK_COLOR_LUT(base.gamma_lut, bp_gamma);
> }
>
> PIPE_CONF_CHECK_BOOL(double_wide);
> @@ -12255,6 +12278,7 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
> #undef PIPE_CONF_CHECK_FLAGS
> #undef PIPE_CONF_CHECK_CLOCK_FUZZY
> #undef PIPE_CONF_QUIRK
> +#undef PIPE_CONF_CHECK_COLOR_LUT
>
> return ret;
> }
> --
> 1.9.1
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [v6][PATCH 03/12] drm/i915: Add intel_color_lut_equal() to compare hw and sw gamma/degamma lut values
2019-05-14 16:10 ` Ville Syrjälä
@ 2019-05-21 13:42 ` Sharma, Swati2
2019-05-24 15:25 ` Ville Syrjälä
0 siblings, 1 reply; 26+ messages in thread
From: Sharma, Swati2 @ 2019-05-21 13:42 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: jani.nikula, intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 9995 bytes --]
On 14-May-19 9:40 PM, Ville Syrjälä wrote:
> On Tue, May 14, 2019 at 03:13:21PM +0530, Swati Sharma wrote:
>> v3: -Rebase
>> v4: -Renamed intel_compare_color_lut() to intel_color_lut_equal() [Jani]
>> -Added the default label above the correct label [Jani]
>> -Corrected smatch warn "variable dereferenced before check" [Dan Carpenter]
>> v5: -Added condition (!blob1 && !blob2) return true [Jani]
>> -Called PIPE_CONF_CHECK_COLOR_LUT inside if (!adjust) [Jani]
>> -Added #undef PIPE_CONF_CHECK_COLOR_LUT [Jani]
>> v6: -Added func intel_color_get_bit_precision() to get bit precision for
>> gamma and degamma lut readout depending upon platform and
>> corresponding to load_luts() [Ankit]
>> -Added debug log for color para in intel_dump_pipe_config [Jani]
>> -Made patch11 as patch3 [Jani]
>>
>> I could think of adding intel_color_get_bit_precision() to be the way
>> to get away with bit precision problem for degamma and gamma (its like a table
>> having hard coded values depening on gamma_mode).
>> If anybody could think of better way then this then please guide.
>>
>> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_color.c | 93 ++++++++++++++++++++++++++++++++++++
>> drivers/gpu/drm/i915/intel_color.h | 7 +++
>> drivers/gpu/drm/i915/intel_display.c | 24 ++++++++++
>> 3 files changed, 124 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
>> index 50b98ee..1e60369 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -1251,6 +1251,99 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
>> return 0;
>> }
>>
>> +void intel_color_get_bit_precision(struct intel_crtc_state *crtc_state, int *bp_gamma)
>> +{
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> +
>> + if (HAS_GMCH(dev_priv)) {
>> + if (IS_CHERRYVIEW(dev_priv)) {
>> + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
>> + *bp_gamma = 8;
>> + return;
> Functions can actually return values.
>
> Not sure I particularly like this function though. We can't fit
> the gamma vs. degamm stuff in here neatly. I think per-platform
> stuff to determine the precision is required to make this sane.
> And it should probably got into intel_color.c to keep things
> neatly contained.
>
> Something along the lines of:
>
> i9xx_gamma_precision()
> {
> if (!gamma_enable)
> return 0;
>
> switch (gamma_mode) {
> case GAMMA_MODE_MODE_8BIT:
> return 8;
> case GAMMA_MODE_MODE_10BIT:
> return 16;
> }
> }
>
> chv_gamma_precision()
> {
> if (cgm_mode & CGM_PIPE_MODE_GAMMA)
> return 10;
> else
> return i9xx_gamma_precision();
> }
>
> chv_degamma_precision(crtc_state)
> {
> if (cgm_mode & CGM_PIPE_MODE_DEGAMMA)
> return 14;
> else
> return 0
> }
>
> ilk_gamma_precision()
> {
> if (!gamma_enable)
> return 0;
>
> if ((csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
> return 0;
>
> switch (gamma_mode) {
> case GAMMA_MODE_MODE_8BIT:
> return 8;
> case GAMMA_MODE_MODE_10BIT:
> return 10;
> }
> }
>
> ilk_degamma_precision()
> {
> if (!gamma_enable)
> return 0;
>
> if ((csc_mode & CSC_POSITION_BEFORE_GAMMA) != 0)
> return 0;
>
> switch (gamma_mode) {
> case GAMMA_MODE_MODE_8BIT:
> return 8;
> case GAMMA_MODE_MODE_10BIT:
> return 10;
> }
> }
>
> ... extend to ivb, glk, and icl variants too.
ok..will do like this. thanks! sorry i was on leave.
2 queries:
(1) Since intel_color_get_bit_precision() will be used to set bit precision for gamma and degamma both, it will
return multiple values..should i return values as struct? or sending as pointer is ok?
if (HAS_GMCH(dev_priv)) {
if (IS_CHERRYVIEW(dev_priv))
*bp_gamma = chv_gamma_precision(crtc_state);
(2) (or) if this method is not fine, should we have function ptr for the same?
Please suggest the best method?
>
>> + }
>> + if (crtc_state->cgm_mode == CGM_PIPE_MODE_GAMMA)
>> + *bp_gamma = 10;
>> + } else if (INTEL_GEN(dev_priv) >= 4) {
>> + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
>> + *bp_gamma = 8;
>> + else
>> + *bp_gamma = 16;
>> + } else {
>> + *bp_gamma = 8;
>> + }
>> + } else {
>> + if (INTEL_GEN(dev_priv) >= 11) {
>> + if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
>> + GAMMA_MODE_MODE_8BIT)
>> + *bp_gamma = 8;
>> + else
>> + *bp_gamma = 10;
>> + } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
>> + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
>> + *bp_gamma = 8;
>> + else
>> + *bp_gamma = 10;
>> + } else if (INTEL_GEN(dev_priv) >= 7) {
>> + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
>> + *bp_gamma = 8;
>> + else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
>> + *bp_gamma = 10;
>> + else
>> + *bp_gamma = 10;
>> + } else {
>> + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
>> + *bp_gamma = 8;
>> + else
>> + *bp_gamma = 10;
>> + }
>> + }
>> +}
>> +
>> +static inline bool err_check(struct drm_color_lut *sw_lut,
>> + struct drm_color_lut *hw_lut, u32 err)
>> +{
>> + return ((abs((long)hw_lut->red - sw_lut->red)) <= err) &&
>> + ((abs((long)hw_lut->blue - sw_lut->blue)) <= err) &&
>> + ((abs((long)hw_lut->green - sw_lut->green)) <= err);
>> +}
>> +
>> +bool intel_color_lut_equal(struct drm_property_blob *blob1,
>> + struct drm_property_blob *blob2,
>> + u32 bit_precision)
>> +{
>> + struct drm_color_lut *sw_lut, *hw_lut;
>> + int sw_lut_size, hw_lut_size, i;
>> + u32 err;
>> +
>> + if (!blob1 && !blob2)
>> + return true;
>> +
>> + if (!blob1)
>> + return true;
>> +
>> + if (!blob2)
>> + return false;
>> +
>> + sw_lut_size = drm_color_lut_size(blob1);
>> + hw_lut_size = drm_color_lut_size(blob2);
>> +
>> + if (sw_lut_size != hw_lut_size)
>> + return false;
>> +
>> + sw_lut = blob1->data;
>> + hw_lut = blob2->data;
>> +
>> + err = 0xffff >> bit_precision;
>> +
>> + for (i = 0; i < sw_lut_size; i++) {
>> + if (!err_check(&hw_lut[i], &sw_lut[i], err))
>> + return false;
>> + }
>> +
>> + return true;
>> +}
>> +
>> void intel_color_init(struct intel_crtc *crtc)
>> {
>> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> diff --git a/drivers/gpu/drm/i915/intel_color.h b/drivers/gpu/drm/i915/intel_color.h
>> index 057e8ac..f2872d3 100644
>> --- a/drivers/gpu/drm/i915/intel_color.h
>> +++ b/drivers/gpu/drm/i915/intel_color.h
>> @@ -6,13 +6,20 @@
>> #ifndef __INTEL_COLOR_H__
>> #define __INTEL_COLOR_H__
>>
>> +#include <linux/types.h>
>> +
>> struct intel_crtc_state;
>> struct intel_crtc;
>> +struct drm_property_blob;
>>
>> void intel_color_init(struct intel_crtc *crtc);
>> int intel_color_check(struct intel_crtc_state *crtc_state);
>> void intel_color_commit(const struct intel_crtc_state *crtc_state);
>> void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
>> void intel_color_get_config(struct intel_crtc_state *crtc_state);
>> +bool intel_color_lut_equal(struct drm_property_blob *blob1,
>> + struct drm_property_blob *blob2,
>> + u32 bit_precision);
>> +void intel_color_get_bit_precision(struct intel_crtc_state *crtc_state, int *bp_gamma);
>>
>> #endif /* __INTEL_COLOR_H__ */
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 3e01028..46985c15 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -11570,6 +11570,16 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
>> drm_rect_width(&state->base.dst),
>> drm_rect_height(&state->base.dst));
>> }
>> +
>> + if (IS_CHERRYVIEW(dev_priv))
>> + DRM_DEBUG_KMS("cgm_mode:%d gamma_mode:%d gamma_enable:%d csc_enable:%d\n",
>> + pipe_config->cgm_mode, pipe_config->gamma_mode, pipe_config->gamma_enable,
>> + pipe_config->csc_enable);
>> + else
>> + DRM_DEBUG_KMS("csc_mode:%d gamma_mode:%d gamma_enable:%d csc_enable:%d\n",
>> + pipe_config->csc_mode, pipe_config->gamma_mode, pipe_config->gamma_enable,
>> + pipe_config->csc_enable);
>> +
>> }
>>
>> static bool check_digital_port_conflicts(struct drm_atomic_state *state)
>> @@ -11947,6 +11957,7 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
>> bool adjust)
>> {
>> bool ret = true;
>> + u32 bp_gamma = 0;
>> bool fixup_inherited = adjust &&
>> (current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
>> !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
>> @@ -12098,6 +12109,15 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
>> } \
>> } while (0)
>>
>> +#define PIPE_CONF_CHECK_COLOR_LUT(name, bit_precision) do { \
>> + if (!intel_color_lut_equal(current_config->name, \
>> + pipe_config->name, bit_precision)) { \
>> + pipe_config_err(adjust, __stringify(name), \
>> + "hw_state doesn't match sw_state\n"); \
>> + ret = false; \
>> + } \
>> +} while (0)
>> +
>> #define PIPE_CONF_QUIRK(quirk) \
>> ((current_config->quirks | pipe_config->quirks) & (quirk))
>>
>> @@ -12193,6 +12213,9 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
>> PIPE_CONF_CHECK_X(csc_mode);
>> PIPE_CONF_CHECK_BOOL(gamma_enable);
>> PIPE_CONF_CHECK_BOOL(csc_enable);
>> +
>> + intel_color_get_bit_precision(pipe_config, &bp_gamma);
>> + PIPE_CONF_CHECK_COLOR_LUT(base.gamma_lut, bp_gamma);
>> }
>>
>> PIPE_CONF_CHECK_BOOL(double_wide);
>> @@ -12255,6 +12278,7 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
>> #undef PIPE_CONF_CHECK_FLAGS
>> #undef PIPE_CONF_CHECK_CLOCK_FUZZY
>> #undef PIPE_CONF_QUIRK
>> +#undef PIPE_CONF_CHECK_COLOR_LUT
>>
>> return ret;
>> }
>> --
>> 1.9.1
--
~Swati Sharma
[-- Attachment #1.2: Type: text/html, Size: 10418 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [v6][PATCH 03/12] drm/i915: Add intel_color_lut_equal() to compare hw and sw gamma/degamma lut values
2019-05-21 13:42 ` Sharma, Swati2
@ 2019-05-24 15:25 ` Ville Syrjälä
0 siblings, 0 replies; 26+ messages in thread
From: Ville Syrjälä @ 2019-05-24 15:25 UTC (permalink / raw)
To: Sharma, Swati2; +Cc: jani.nikula, intel-gfx
On Tue, May 21, 2019 at 07:12:28PM +0530, Sharma, Swati2 wrote:
> On 14-May-19 9:40 PM, Ville Syrjälä wrote:
>
> > On Tue, May 14, 2019 at 03:13:21PM +0530, Swati Sharma wrote:
> >> v3: -Rebase
> >> v4: -Renamed intel_compare_color_lut() to intel_color_lut_equal() [Jani]
> >> -Added the default label above the correct label [Jani]
> >> -Corrected smatch warn "variable dereferenced before check" [Dan Carpenter]
> >> v5: -Added condition (!blob1 && !blob2) return true [Jani]
> >> -Called PIPE_CONF_CHECK_COLOR_LUT inside if (!adjust) [Jani]
> >> -Added #undef PIPE_CONF_CHECK_COLOR_LUT [Jani]
> >> v6: -Added func intel_color_get_bit_precision() to get bit precision for
> >> gamma and degamma lut readout depending upon platform and
> >> corresponding to load_luts() [Ankit]
> >> -Added debug log for color para in intel_dump_pipe_config [Jani]
> >> -Made patch11 as patch3 [Jani]
> >>
> >> I could think of adding intel_color_get_bit_precision() to be the way
> >> to get away with bit precision problem for degamma and gamma (its like a table
> >> having hard coded values depening on gamma_mode).
> >> If anybody could think of better way then this then please guide.
> >>
> >> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/intel_color.c | 93 ++++++++++++++++++++++++++++++++++++
> >> drivers/gpu/drm/i915/intel_color.h | 7 +++
> >> drivers/gpu/drm/i915/intel_display.c | 24 ++++++++++
> >> 3 files changed, 124 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> >> index 50b98ee..1e60369 100644
> >> --- a/drivers/gpu/drm/i915/intel_color.c
> >> +++ b/drivers/gpu/drm/i915/intel_color.c
> >> @@ -1251,6 +1251,99 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
> >> return 0;
> >> }
> >>
> >> +void intel_color_get_bit_precision(struct intel_crtc_state *crtc_state, int *bp_gamma)
> >> +{
> >> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> >> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >> +
> >> + if (HAS_GMCH(dev_priv)) {
> >> + if (IS_CHERRYVIEW(dev_priv)) {
> >> + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
> >> + *bp_gamma = 8;
> >> + return;
> > Functions can actually return values.
> >
> > Not sure I particularly like this function though. We can't fit
> > the gamma vs. degamm stuff in here neatly. I think per-platform
> > stuff to determine the precision is required to make this sane.
> > And it should probably got into intel_color.c to keep things
> > neatly contained.
> >
> > Something along the lines of:
> >
> > i9xx_gamma_precision()
> > {
> > if (!gamma_enable)
> > return 0;
> >
> > switch (gamma_mode) {
> > case GAMMA_MODE_MODE_8BIT:
> > return 8;
> > case GAMMA_MODE_MODE_10BIT:
> > return 16;
> > }
> > }
> >
> > chv_gamma_precision()
> > {
> > if (cgm_mode & CGM_PIPE_MODE_GAMMA)
> > return 10;
> > else
> > return i9xx_gamma_precision();
> > }
> >
> > chv_degamma_precision(crtc_state)
> > {
> > if (cgm_mode & CGM_PIPE_MODE_DEGAMMA)
> > return 14;
> > else
> > return 0
> > }
> >
> > ilk_gamma_precision()
> > {
> > if (!gamma_enable)
> > return 0;
> >
> > if ((csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
> > return 0;
> >
> > switch (gamma_mode) {
> > case GAMMA_MODE_MODE_8BIT:
> > return 8;
> > case GAMMA_MODE_MODE_10BIT:
> > return 10;
> > }
> > }
> >
> > ilk_degamma_precision()
> > {
> > if (!gamma_enable)
> > return 0;
> >
> > if ((csc_mode & CSC_POSITION_BEFORE_GAMMA) != 0)
> > return 0;
> >
> > switch (gamma_mode) {
> > case GAMMA_MODE_MODE_8BIT:
> > return 8;
> > case GAMMA_MODE_MODE_10BIT:
> > return 10;
> > }
> > }
> >
> > ... extend to ivb, glk, and icl variants too.
>
> ok..will do like this. thanks! sorry i was on leave.
> 2 queries:
> (1) Since intel_color_get_bit_precision() will be used to set bit precision for gamma and degamma both, it will
> return multiple values..should i return values as struct? or sending as pointer is ok?
> if (HAS_GMCH(dev_priv)) {
> if (IS_CHERRYVIEW(dev_priv))
> *bp_gamma = chv_gamma_precision(crtc_state);
> (2) (or) if this method is not fine, should we have function ptr for the same?
> Please suggest the best method?
I would go for separate functions for gamma and degamma.
>
> >
> >> + }
> >> + if (crtc_state->cgm_mode == CGM_PIPE_MODE_GAMMA)
> >> + *bp_gamma = 10;
> >> + } else if (INTEL_GEN(dev_priv) >= 4) {
> >> + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> >> + *bp_gamma = 8;
> >> + else
> >> + *bp_gamma = 16;
> >> + } else {
> >> + *bp_gamma = 8;
> >> + }
> >> + } else {
> >> + if (INTEL_GEN(dev_priv) >= 11) {
> >> + if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
> >> + GAMMA_MODE_MODE_8BIT)
> >> + *bp_gamma = 8;
> >> + else
> >> + *bp_gamma = 10;
> >> + } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
> >> + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> >> + *bp_gamma = 8;
> >> + else
> >> + *bp_gamma = 10;
> >> + } else if (INTEL_GEN(dev_priv) >= 7) {
> >> + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> >> + *bp_gamma = 8;
> >> + else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
> >> + *bp_gamma = 10;
> >> + else
> >> + *bp_gamma = 10;
> >> + } else {
> >> + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> >> + *bp_gamma = 8;
> >> + else
> >> + *bp_gamma = 10;
> >> + }
> >> + }
> >> +}
> >> +
> >> +static inline bool err_check(struct drm_color_lut *sw_lut,
> >> + struct drm_color_lut *hw_lut, u32 err)
> >> +{
> >> + return ((abs((long)hw_lut->red - sw_lut->red)) <= err) &&
> >> + ((abs((long)hw_lut->blue - sw_lut->blue)) <= err) &&
> >> + ((abs((long)hw_lut->green - sw_lut->green)) <= err);
> >> +}
> >> +
> >> +bool intel_color_lut_equal(struct drm_property_blob *blob1,
> >> + struct drm_property_blob *blob2,
> >> + u32 bit_precision)
> >> +{
> >> + struct drm_color_lut *sw_lut, *hw_lut;
> >> + int sw_lut_size, hw_lut_size, i;
> >> + u32 err;
> >> +
> >> + if (!blob1 && !blob2)
> >> + return true;
> >> +
> >> + if (!blob1)
> >> + return true;
> >> +
> >> + if (!blob2)
> >> + return false;
> >> +
> >> + sw_lut_size = drm_color_lut_size(blob1);
> >> + hw_lut_size = drm_color_lut_size(blob2);
> >> +
> >> + if (sw_lut_size != hw_lut_size)
> >> + return false;
> >> +
> >> + sw_lut = blob1->data;
> >> + hw_lut = blob2->data;
> >> +
> >> + err = 0xffff >> bit_precision;
> >> +
> >> + for (i = 0; i < sw_lut_size; i++) {
> >> + if (!err_check(&hw_lut[i], &sw_lut[i], err))
> >> + return false;
> >> + }
> >> +
> >> + return true;
> >> +}
> >> +
> >> void intel_color_init(struct intel_crtc *crtc)
> >> {
> >> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >> diff --git a/drivers/gpu/drm/i915/intel_color.h b/drivers/gpu/drm/i915/intel_color.h
> >> index 057e8ac..f2872d3 100644
> >> --- a/drivers/gpu/drm/i915/intel_color.h
> >> +++ b/drivers/gpu/drm/i915/intel_color.h
> >> @@ -6,13 +6,20 @@
> >> #ifndef __INTEL_COLOR_H__
> >> #define __INTEL_COLOR_H__
> >>
> >> +#include <linux/types.h>
> >> +
> >> struct intel_crtc_state;
> >> struct intel_crtc;
> >> +struct drm_property_blob;
> >>
> >> void intel_color_init(struct intel_crtc *crtc);
> >> int intel_color_check(struct intel_crtc_state *crtc_state);
> >> void intel_color_commit(const struct intel_crtc_state *crtc_state);
> >> void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
> >> void intel_color_get_config(struct intel_crtc_state *crtc_state);
> >> +bool intel_color_lut_equal(struct drm_property_blob *blob1,
> >> + struct drm_property_blob *blob2,
> >> + u32 bit_precision);
> >> +void intel_color_get_bit_precision(struct intel_crtc_state *crtc_state, int *bp_gamma);
> >>
> >> #endif /* __INTEL_COLOR_H__ */
> >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >> index 3e01028..46985c15 100644
> >> --- a/drivers/gpu/drm/i915/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/intel_display.c
> >> @@ -11570,6 +11570,16 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
> >> drm_rect_width(&state->base.dst),
> >> drm_rect_height(&state->base.dst));
> >> }
> >> +
> >> + if (IS_CHERRYVIEW(dev_priv))
> >> + DRM_DEBUG_KMS("cgm_mode:%d gamma_mode:%d gamma_enable:%d csc_enable:%d\n",
> >> + pipe_config->cgm_mode, pipe_config->gamma_mode, pipe_config->gamma_enable,
> >> + pipe_config->csc_enable);
> >> + else
> >> + DRM_DEBUG_KMS("csc_mode:%d gamma_mode:%d gamma_enable:%d csc_enable:%d\n",
> >> + pipe_config->csc_mode, pipe_config->gamma_mode, pipe_config->gamma_enable,
> >> + pipe_config->csc_enable);
> >> +
> >> }
> >>
> >> static bool check_digital_port_conflicts(struct drm_atomic_state *state)
> >> @@ -11947,6 +11957,7 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
> >> bool adjust)
> >> {
> >> bool ret = true;
> >> + u32 bp_gamma = 0;
> >> bool fixup_inherited = adjust &&
> >> (current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
> >> !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
> >> @@ -12098,6 +12109,15 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
> >> } \
> >> } while (0)
> >>
> >> +#define PIPE_CONF_CHECK_COLOR_LUT(name, bit_precision) do { \
> >> + if (!intel_color_lut_equal(current_config->name, \
> >> + pipe_config->name, bit_precision)) { \
> >> + pipe_config_err(adjust, __stringify(name), \
> >> + "hw_state doesn't match sw_state\n"); \
> >> + ret = false; \
> >> + } \
> >> +} while (0)
> >> +
> >> #define PIPE_CONF_QUIRK(quirk) \
> >> ((current_config->quirks | pipe_config->quirks) & (quirk))
> >>
> >> @@ -12193,6 +12213,9 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
> >> PIPE_CONF_CHECK_X(csc_mode);
> >> PIPE_CONF_CHECK_BOOL(gamma_enable);
> >> PIPE_CONF_CHECK_BOOL(csc_enable);
> >> +
> >> + intel_color_get_bit_precision(pipe_config, &bp_gamma);
> >> + PIPE_CONF_CHECK_COLOR_LUT(base.gamma_lut, bp_gamma);
> >> }
> >>
> >> PIPE_CONF_CHECK_BOOL(double_wide);
> >> @@ -12255,6 +12278,7 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
> >> #undef PIPE_CONF_CHECK_FLAGS
> >> #undef PIPE_CONF_CHECK_CLOCK_FUZZY
> >> #undef PIPE_CONF_QUIRK
> >> +#undef PIPE_CONF_CHECK_COLOR_LUT
> >>
> >> return ret;
> >> }
> >> --
> >> 1.9.1
>
>
> --
> ~Swati Sharma
>
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* [v6][PATCH 04/12] drm/i915: Extract i9xx_read_luts()
2019-05-14 9:43 [PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (2 preceding siblings ...)
2019-05-14 9:43 ` [v6][PATCH 03/12] drm/i915: Add intel_color_lut_equal() to compare hw and sw gamma/degamma lut values Swati Sharma
@ 2019-05-14 9:43 ` Swati Sharma
2019-05-14 9:43 ` [v6][PATCH 05/12] drm/i915: Extract chv_read_luts() Swati Sharma
` (15 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Swati Sharma @ 2019-05-14 9:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
In this patch, hw gamma blob is created for the legacy
gamma. Also, function intel_color_lut_pack is added to
convert hw value with given bit_precision to lut property val.
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
v5: -Returned blob instead of assigning it internally withing the
function [Ville]
-Renamed function i9xx_get_color_config() to i9xx_read_luts()
-Renamed i9xx_get_config_internal() to i9xx_read_lut_8() [Ville]
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_color.c | 51 ++++++++++++++++++++++++++++++++++++++
2 files changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e97c47f..d8475f2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7178,6 +7178,9 @@ enum {
/* legacy palette */
#define _LGC_PALETTE_A 0x4a000
#define _LGC_PALETTE_B 0x4a800
+#define LGC_PALETTE_RED_MASK REG_GENMASK(23, 16)
+#define LGC_PALETTE_GREEN_MASK REG_GENMASK(15, 8)
+#define LGC_PALETTE_BLUE_MASK REG_GENMASK(7, 0)
#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
/* ilk/snb precision palette */
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 1e60369..3396d35 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -1344,6 +1344,56 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
return true;
}
+/* convert hw value with given bit_precision to lut property val */
+static u32 intel_color_lut_pack(u32 val, u32 bit_precision)
+{
+ u32 max = 0xffff >> (16 - bit_precision);
+
+ val = clamp_val(val, 0, max);
+
+ if (bit_precision < 16)
+ val <<= 16 - bit_precision;
+
+ return val;
+}
+
+static struct drm_property_blob *
+i9xx_read_lut_8(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ struct drm_property_blob *blob;
+ struct drm_color_lut *blob_data;
+ u32 i, val;
+
+ blob = drm_property_create_blob(&dev_priv->drm,
+ sizeof(struct drm_color_lut) * 256,
+ NULL);
+ if (IS_ERR(blob))
+ return NULL;
+
+ blob_data = blob->data;
+
+ for (i = 0; i < 256; i++) {
+ if (HAS_GMCH(dev_priv))
+ val = I915_READ(PALETTE(pipe, i));
+ else
+ val = I915_READ(LGC_PALETTE(pipe, i));
+
+ blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_RED_MASK, val), 8);
+ blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_GREEN_MASK, val), 8);
+ blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_BLUE_MASK, val), 8);
+ }
+
+ return blob;
+}
+
+void i9xx_read_luts(struct intel_crtc_state *crtc_state)
+{
+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1364,6 +1414,7 @@ void intel_color_init(struct intel_crtc *crtc)
dev_priv->display.color_check = i9xx_color_check;
dev_priv->display.color_commit = i9xx_color_commit;
dev_priv->display.load_luts = i9xx_load_luts;
+ dev_priv->display.read_luts = i9xx_read_luts;
}
} else {
if (INTEL_GEN(dev_priv) >= 11)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [v6][PATCH 05/12] drm/i915: Extract chv_read_luts()
2019-05-14 9:43 [PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (3 preceding siblings ...)
2019-05-14 9:43 ` [v6][PATCH 04/12] drm/i915: Extract i9xx_read_luts() Swati Sharma
@ 2019-05-14 9:43 ` Swati Sharma
2019-05-14 9:43 ` [v6][PATCH 06/12] drm/i915: Extract i965_read_luts() Swati Sharma
` (14 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Swati Sharma @ 2019-05-14 9:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
In this patch, hw gamma and degamma blob is created for
cherryview.
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
v5: -Returned blob instead of assigning it internally within the
function [Ville]
-Renamed function cherryview_get_color_config() to chv_read_luts()
-Renamed cherryview_get_gamma_config() to chv_read_cgm_gamma_lut() [Ville]
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_color.c | 40 ++++++++++++++++++++++++++++++++++++++
2 files changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d8475f2..b58c66d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10160,6 +10160,9 @@ enum skl_power_gate {
#define CGM_PIPE_MODE_GAMMA (1 << 2)
#define CGM_PIPE_MODE_CSC (1 << 1)
#define CGM_PIPE_MODE_DEGAMMA (1 << 0)
+#define CGM_PIPE_GAMMA_RED_MASK REG_GENMASK(9, 0)
+#define CGM_PIPE_GAMMA_GREEN_MASK REG_GENMASK(25, 16)
+#define CGM_PIPE_GAMMA_BLUE_MASK REG_GENMASK(9, 0)
#define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
#define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 3396d35..a7a0b74 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -1394,6 +1394,45 @@ void i9xx_read_luts(struct intel_crtc_state *crtc_state)
crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
}
+static struct drm_property_blob *
+chv_read_cgm_gamma_lut(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 i, val, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+ enum pipe pipe = crtc->pipe;
+ struct drm_property_blob *blob;
+ struct drm_color_lut *blob_data;
+
+ blob = drm_property_create_blob(&dev_priv->drm,
+ sizeof(struct drm_color_lut) * lut_size,
+ NULL);
+ if (IS_ERR(blob))
+ return NULL;
+
+ blob_data = blob->data;
+
+ for (i = 0; i < lut_size; i++) {
+ val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 0));
+ blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
+ blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, val), 10);
+
+ val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 1));
+ blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, val), 10);
+ }
+
+ return blob;
+}
+
+static void chv_read_luts(struct intel_crtc_state *crtc_state)
+{
+ if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+ else
+ crtc_state->base.gamma_lut = chv_read_cgm_gamma_lut(crtc_state);
+
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1406,6 +1445,7 @@ void intel_color_init(struct intel_crtc *crtc)
dev_priv->display.color_check = chv_color_check;
dev_priv->display.color_commit = i9xx_color_commit;
dev_priv->display.load_luts = chv_load_luts;
+ dev_priv->display.read_luts = chv_read_luts;
} else if (INTEL_GEN(dev_priv) >= 4) {
dev_priv->display.color_check = i9xx_color_check;
dev_priv->display.color_commit = i9xx_color_commit;
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [v6][PATCH 06/12] drm/i915: Extract i965_read_luts()
2019-05-14 9:43 [PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (4 preceding siblings ...)
2019-05-14 9:43 ` [v6][PATCH 05/12] drm/i915: Extract chv_read_luts() Swati Sharma
@ 2019-05-14 9:43 ` Swati Sharma
2019-05-14 9:43 ` [v6][PATCH 07/12] drm/i915: Extract icl_read_luts() Swati Sharma
` (13 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Swati Sharma @ 2019-05-14 9:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
In this patch, hw gamma blob is created for i965.
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
v5: -Returned blob instead of assigning it internally
within the function [Ville]
-Renamed i965_get_color_config() to i965_read_lut() [Ville]
-Renamed i965_get_gamma_config_10p6() to i965_read_gamma_lut_10p6() [Ville]
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_color.c | 39 ++++++++++++++++++++++++++++++++++++++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b58c66d..7988fa5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3584,6 +3584,9 @@ enum i915_power_well_id {
#define _PALETTE_A 0xa000
#define _PALETTE_B 0xa800
#define _CHV_PALETTE_C 0xc000
+#define PALETTE_RED_MASK REG_GENMASK(23, 16)
+#define PALETTE_GREEN_MASK REG_GENMASK(15, 8)
+#define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
_PICK((pipe), _PALETTE_A, \
_PALETTE_B, _CHV_PALETTE_C) + \
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index a7a0b74..121b2c4 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -1433,6 +1433,44 @@ static void chv_read_luts(struct intel_crtc_state *crtc_state)
}
+static struct drm_property_blob *
+i965_read_gamma_lut_10p6(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 i, val1, val2, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+ enum pipe pipe = crtc->pipe;
+ struct drm_property_blob *blob;
+ struct drm_color_lut *blob_data;
+
+ blob = drm_property_create_blob(&dev_priv->drm,
+ sizeof(struct drm_color_lut) * lut_size,
+ NULL);
+ if (IS_ERR(blob))
+ return NULL;
+
+ blob_data = blob->data;
+
+ for (i = 0; i < lut_size - 1; i++) {
+ val1 = I915_READ(PALETTE(pipe, 2 * i + 0));
+ val2 = I915_READ(PALETTE(pipe, 2 * i + 1));
+
+ blob_data[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val1) << 8 | REG_FIELD_GET(PALETTE_RED_MASK, val2);
+ blob_data[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val1) << 8 | REG_FIELD_GET(PALETTE_GREEN_MASK, val2);
+ blob_data[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val1) << 8 | REG_FIELD_GET(PALETTE_BLUE_MASK, val2) ;
+ }
+
+ return blob;
+}
+
+static void i965_read_luts(struct intel_crtc_state *crtc_state)
+{
+ if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+ else
+ crtc_state->base.gamma_lut = i965_read_gamma_lut_10p6(crtc_state);
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1450,6 +1488,7 @@ void intel_color_init(struct intel_crtc *crtc)
dev_priv->display.color_check = i9xx_color_check;
dev_priv->display.color_commit = i9xx_color_commit;
dev_priv->display.load_luts = i965_load_luts;
+ dev_priv->display.read_luts = i965_read_luts;
} else {
dev_priv->display.color_check = i9xx_color_check;
dev_priv->display.color_commit = i9xx_color_commit;
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [v6][PATCH 07/12] drm/i915: Extract icl_read_luts()
2019-05-14 9:43 [PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (5 preceding siblings ...)
2019-05-14 9:43 ` [v6][PATCH 06/12] drm/i915: Extract i965_read_luts() Swati Sharma
@ 2019-05-14 9:43 ` Swati Sharma
2019-05-14 9:43 ` [v6][PATCH 08/12] drm/i915: Extract glk_read_luts() Swati Sharma
` (12 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Swati Sharma @ 2019-05-14 9:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
In this patch, gamma hw blobs are created for ICL.
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
v5: -Returned blob instead of assigning it internally within the
function [Ville]
-Renamed icl_get_color_config() to icl_read_luts() [Ville]
-Renamed bdw_get_gamma_config() to bdw_read_lut_10() [Ville]
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_color.c | 49 +++++++++++++++++++++++++++++++++++++-
2 files changed, 51 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7988fa5..249296b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10124,6 +10124,9 @@ enum skl_power_gate {
#define _PAL_PREC_DATA_A 0x4A404
#define _PAL_PREC_DATA_B 0x4AC04
#define _PAL_PREC_DATA_C 0x4B404
+#define PREC_PAL_DATA_RED_MASK REG_GENMASK(29, 20)
+#define PREC_PAL_DATA_GREEN_MASK REG_GENMASK(19, 10)
+#define PREC_PAL_DATA_BLUE_MASK REG_GENMASK(9, 0)
#define _PAL_PREC_GC_MAX_A 0x4A410
#define _PAL_PREC_GC_MAX_B 0x4AC10
#define _PAL_PREC_GC_MAX_C 0x4B410
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 121b2c4..43723e2 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -1471,6 +1471,51 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state)
crtc_state->base.gamma_lut = i965_read_gamma_lut_10p6(crtc_state);
}
+static struct drm_property_blob *
+bdw_read_lut_10(struct intel_crtc_state *crtc_state,
+ u32 prec_index)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ int hw_lut_size = ivb_lut_10_size(prec_index);
+ enum pipe pipe = crtc->pipe;
+ struct drm_property_blob *blob;
+ struct drm_color_lut *blob_data;
+ u32 i, val;
+
+ I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
+ PAL_PREC_AUTO_INCREMENT);
+
+ blob = drm_property_create_blob(&dev_priv->drm,
+ sizeof(struct drm_color_lut) * hw_lut_size,
+ NULL);
+ if (IS_ERR(blob))
+ return NULL;
+
+ blob_data = blob->data;
+
+ for (i = 0; i < hw_lut_size; i++) {
+ val = I915_READ(PREC_PAL_DATA(pipe));
+
+ blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_RED_MASK, val), 10);
+ blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_GREEN_MASK, val), 10);
+ blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_BLUE_MASK, val), 10);
+ }
+
+ I915_WRITE(PREC_PAL_INDEX(pipe), 0);
+
+ return blob;
+}
+
+static void icl_read_luts(struct intel_crtc_state *crtc_state)
+{
+ if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
+ GAMMA_MODE_MODE_8BIT)
+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+ else
+ crtc_state->base.gamma_lut = bdw_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1512,8 +1557,10 @@ void intel_color_init(struct intel_crtc *crtc)
else
dev_priv->display.color_commit = ilk_color_commit;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (INTEL_GEN(dev_priv) >= 11) {
dev_priv->display.load_luts = icl_load_luts;
+ dev_priv->display.read_luts = icl_read_luts;
+ }
else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
dev_priv->display.load_luts = glk_load_luts;
else if (INTEL_GEN(dev_priv) >= 8)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [v6][PATCH 08/12] drm/i915: Extract glk_read_luts()
2019-05-14 9:43 [PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (6 preceding siblings ...)
2019-05-14 9:43 ` [v6][PATCH 07/12] drm/i915: Extract icl_read_luts() Swati Sharma
@ 2019-05-14 9:43 ` Swati Sharma
2019-05-14 9:43 ` [v6][PATCH 09/12] drm/i915: Extract bdw_read_luts() Swati Sharma
` (11 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Swati Sharma @ 2019-05-14 9:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
In this patch, gamma and degamma hw blobs are created for GLK.
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
v5: -Returned blob instead of assigning it internally within the
function [Ville]
-Renamed glk_get_color_config() to glk_read_luts() [Ville]
-Added degamma validation [Ville]
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/intel_color.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 43723e2..400ec94 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -1516,6 +1516,14 @@ static void icl_read_luts(struct intel_crtc_state *crtc_state)
crtc_state->base.gamma_lut = bdw_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
}
+static void glk_read_luts(struct intel_crtc_state *crtc_state)
+{
+ if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+ else
+ crtc_state->base.gamma_lut = bdw_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1560,9 +1568,10 @@ void intel_color_init(struct intel_crtc *crtc)
if (INTEL_GEN(dev_priv) >= 11) {
dev_priv->display.load_luts = icl_load_luts;
dev_priv->display.read_luts = icl_read_luts;
- }
- else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
dev_priv->display.load_luts = glk_load_luts;
+ dev_priv->display.read_luts = glk_read_luts;
+ }
else if (INTEL_GEN(dev_priv) >= 8)
dev_priv->display.load_luts = bdw_load_luts;
else if (INTEL_GEN(dev_priv) >= 7)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [v6][PATCH 09/12] drm/i915: Extract bdw_read_luts()
2019-05-14 9:43 [PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (7 preceding siblings ...)
2019-05-14 9:43 ` [v6][PATCH 08/12] drm/i915: Extract glk_read_luts() Swati Sharma
@ 2019-05-14 9:43 ` Swati Sharma
2019-05-14 9:43 ` [v6][PATCH 10/12] drm/i915: Extract ivb_read_luts() Swati Sharma
` (10 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Swati Sharma @ 2019-05-14 9:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
In this patch, gamma and degamma hw blobs are created for BDW.
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
v5: -Returned blob instead of assigning it internally within the
function [Ville]
-Renamed bdw_get_color_config() to bdw_read_luts() [Ville]
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/intel_color.c | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 400ec94..f3df351 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -1524,6 +1524,16 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
crtc_state->base.gamma_lut = bdw_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
}
+static void bdw_read_luts(struct intel_crtc_state *crtc_state)
+{
+ if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+ else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
+ crtc_state->base.gamma_lut = bdw_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(512));
+ else
+ crtc_state->base.gamma_lut = bdw_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1571,9 +1581,10 @@ void intel_color_init(struct intel_crtc *crtc)
} else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
dev_priv->display.load_luts = glk_load_luts;
dev_priv->display.read_luts = glk_read_luts;
- }
- else if (INTEL_GEN(dev_priv) >= 8)
+ } else if (INTEL_GEN(dev_priv) >= 8) {
dev_priv->display.load_luts = bdw_load_luts;
+ dev_priv->display.read_luts = bdw_read_luts;
+ }
else if (INTEL_GEN(dev_priv) >= 7)
dev_priv->display.load_luts = ivb_load_luts;
else
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [v6][PATCH 10/12] drm/i915: Extract ivb_read_luts()
2019-05-14 9:43 [PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (8 preceding siblings ...)
2019-05-14 9:43 ` [v6][PATCH 09/12] drm/i915: Extract bdw_read_luts() Swati Sharma
@ 2019-05-14 9:43 ` Swati Sharma
2019-05-14 9:43 ` [v6][PATCH 11/12] drm/i915: Extract ilk_read_luts() Swati Sharma
` (9 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Swati Sharma @ 2019-05-14 9:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
In this patch, gamma and degamma hw blobs are created for IVB.
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
v5: -Returned blob instead of assigning it internally within the
function [Ville]
-Renamed ivb_get_color_config() to ivb_read_luts() [Ville]
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/intel_color.c | 50 ++++++++++++++++++++++++++++++++++++--
1 file changed, 48 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index f3df351..1448f4b 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -1534,6 +1534,51 @@ static void bdw_read_luts(struct intel_crtc_state *crtc_state)
crtc_state->base.gamma_lut = bdw_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
}
+static struct drm_property_blob *
+ivb_read_lut_10(struct intel_crtc_state *crtc_state,
+ u32 prec_index)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ int hw_lut_size = ivb_lut_10_size(prec_index);
+ enum pipe pipe = crtc->pipe;
+ struct drm_property_blob *blob;
+ struct drm_color_lut *blob_data;
+ u32 i, val;
+
+ blob = drm_property_create_blob(&dev_priv->drm,
+ sizeof(struct drm_color_lut) * hw_lut_size,
+ NULL);
+ if (IS_ERR(blob))
+ return NULL;
+
+ blob_data = blob->data;
+
+ for (i = 0; i < hw_lut_size; i++) {
+ I915_WRITE(PREC_PAL_INDEX(pipe), prec_index++);
+ val = I915_READ(PREC_PAL_DATA(pipe));
+
+ blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_RED_MASK, val), 10);
+ blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_GREEN_MASK, val), 10);
+ blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_BLUE_MASK, val), 10);
+ }
+
+ I915_WRITE(PREC_PAL_INDEX(pipe), 0);
+
+ return blob;
+}
+
+static void ivb_read_luts(struct intel_crtc_state *crtc_state)
+{
+ if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+ else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
+ crtc_state->base.gamma_lut = ivb_read_lut_10(crtc_state, PAL_PREC_SPLIT_MODE | PAL_PREC_INDEX_VALUE(512));
+ else
+ crtc_state->base.gamma_lut = ivb_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
+
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1584,9 +1629,10 @@ void intel_color_init(struct intel_crtc *crtc)
} else if (INTEL_GEN(dev_priv) >= 8) {
dev_priv->display.load_luts = bdw_load_luts;
dev_priv->display.read_luts = bdw_read_luts;
- }
- else if (INTEL_GEN(dev_priv) >= 7)
+ } else if (INTEL_GEN(dev_priv) >= 7) {
dev_priv->display.load_luts = ivb_load_luts;
+ dev_priv->display.read_luts = ivb_read_luts;
+ }
else
dev_priv->display.load_luts = ilk_load_luts;
}
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [v6][PATCH 11/12] drm/i915: Extract ilk_read_luts()
2019-05-14 9:43 [PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (9 preceding siblings ...)
2019-05-14 9:43 ` [v6][PATCH 10/12] drm/i915: Extract ivb_read_luts() Swati Sharma
@ 2019-05-14 9:43 ` Swati Sharma
2019-05-14 9:43 ` [v6][PATCH 12/12] FOR_TESTING_ONLY: Print rgb values of hw and sw blobs Swati Sharma
` (8 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Swati Sharma @ 2019-05-14 9:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
In this patch, hw gamma blob is created for ILK.
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
v5: -Returned blob instead of assigning it internally within the
function [Ville]
-Renamed ilk_get_color_config() to ilk_read_luts() [Ville]
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_color.c | 42 ++++++++++++++++++++++++++++++++++++--
2 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 249296b..d5ff323 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7189,6 +7189,9 @@ enum {
/* ilk/snb precision palette */
#define _PREC_PALETTE_A 0x4b000
#define _PREC_PALETTE_B 0x4c000
+#define PREC_PALETTE_RED_MASK REG_GENMASK(29, 20)
+#define PREC_PALETTE_GREEN_MASK REG_GENMASK(19, 10)
+#define PREC_PALETTE_BLUE_MASK REG_GENMASK(9, 0)
#define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)
#define _PREC_PIPEAGCMAX 0x4d000
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 1448f4b..6bbc99a 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -1579,6 +1579,43 @@ static void ivb_read_luts(struct intel_crtc_state *crtc_state)
}
+static struct drm_property_blob *
+ilk_read_gamma_lut(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 i, val, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+ enum pipe pipe = crtc->pipe;
+ struct drm_property_blob *blob;
+ struct drm_color_lut *blob_data;
+
+ blob = drm_property_create_blob(&dev_priv->drm,
+ sizeof(struct drm_color_lut) * lut_size,
+ NULL);
+ if (IS_ERR(blob))
+ return NULL;
+
+ blob_data = blob->data;
+
+ for (i = 0; i < lut_size - 1; i++) {
+ val = I915_READ(PREC_PALETTE(pipe, i));
+
+ blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK, val), 10);
+ blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_GREEN_MASK, val), 10);
+ blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10);
+ }
+
+ return blob;
+}
+
+static void ilk_read_luts(struct intel_crtc_state *crtc_state)
+{
+ if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+ else
+ crtc_state->base.gamma_lut = ilk_read_gamma_lut(crtc_state);
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1632,9 +1669,10 @@ void intel_color_init(struct intel_crtc *crtc)
} else if (INTEL_GEN(dev_priv) >= 7) {
dev_priv->display.load_luts = ivb_load_luts;
dev_priv->display.read_luts = ivb_read_luts;
- }
- else
+ } else {
dev_priv->display.load_luts = ilk_load_luts;
+ dev_priv->display.read_luts = ilk_read_luts;
+ }
}
drm_crtc_enable_color_mgmt(&crtc->base,
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [v6][PATCH 12/12] FOR_TESTING_ONLY: Print rgb values of hw and sw blobs
2019-05-14 9:43 [PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (10 preceding siblings ...)
2019-05-14 9:43 ` [v6][PATCH 11/12] drm/i915: Extract ilk_read_luts() Swati Sharma
@ 2019-05-14 9:43 ` Swati Sharma
2019-05-14 10:36 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: adding state checker for gamma lut values (rev8) Patchwork
` (7 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Swati Sharma @ 2019-05-14 9:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/intel_color.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 6bbc99a..3d9e375 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -1303,6 +1303,8 @@ void intel_color_get_bit_precision(struct intel_crtc_state *crtc_state, int *bp_
static inline bool err_check(struct drm_color_lut *sw_lut,
struct drm_color_lut *hw_lut, u32 err)
{
+ DRM_DEBUG_KMS("hw_lut->red=0x%x sw_lut->red=0x%x hw_lut->blue=0x%x sw_lut->blue=0x%x hw_lut->green=0x%x sw_lut->green=0x%x", hw_lut->red, sw_lut->red, hw_lut->blue, sw_lut->blue, hw_lut->green, sw_lut->green);
+
return ((abs((long)hw_lut->red - sw_lut->red)) <= err) &&
((abs((long)hw_lut->blue - sw_lut->blue)) <= err) &&
((abs((long)hw_lut->green - sw_lut->green)) <= err);
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: adding state checker for gamma lut values (rev8)
2019-05-14 9:43 [PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (11 preceding siblings ...)
2019-05-14 9:43 ` [v6][PATCH 12/12] FOR_TESTING_ONLY: Print rgb values of hw and sw blobs Swati Sharma
@ 2019-05-14 10:36 ` Patchwork
2019-05-14 10:42 ` ✗ Fi.CI.SPARSE: " Patchwork
` (6 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2019-05-14 10:36 UTC (permalink / raw)
To: Swati Sharma; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: adding state checker for gamma lut values (rev8)
URL : https://patchwork.freedesktop.org/series/58039/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
12495d94dac5 drm/i915: Introduce vfunc read_luts() to create hw lut
316533acb64b drm/i915: Enable intel_color_get_config()
1eec6d06f200 drm/i915: Add intel_color_lut_equal() to compare hw and sw gamma/degamma lut values
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#10:
-Corrected smatch warn "variable dereferenced before check" [Dan Carpenter]
-:85: ERROR:CODE_INDENT: code indent should use tabs where possible
#85: FILE: drivers/gpu/drm/i915/intel_color.c:1304:
+^I struct drm_color_lut *hw_lut, u32 err)$
-:85: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#85: FILE: drivers/gpu/drm/i915/intel_color.c:1304:
+static inline bool err_check(struct drm_color_lut *sw_lut,
+ struct drm_color_lut *hw_lut, u32 err)
-:87: WARNING:TABSTOP: Statements should start on a tabstop
#87: FILE: drivers/gpu/drm/i915/intel_color.c:1306:
+ return ((abs((long)hw_lut->red - sw_lut->red)) <= err) &&
-:88: ERROR:CODE_INDENT: code indent should use tabs where possible
#88: FILE: drivers/gpu/drm/i915/intel_color.c:1307:
+^I ((abs((long)hw_lut->blue - sw_lut->blue)) <= err) &&$
-:89: ERROR:CODE_INDENT: code indent should use tabs where possible
#89: FILE: drivers/gpu/drm/i915/intel_color.c:1308:
+^I ((abs((long)hw_lut->green - sw_lut->green)) <= err);$
-:120: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 17)
#120: FILE: drivers/gpu/drm/i915/intel_color.c:1339:
+ for (i = 0; i < sw_lut_size; i++) {
+ if (!err_check(&hw_lut[i], &sw_lut[i], err))
-:121: WARNING:TABSTOP: Statements should start on a tabstop
#121: FILE: drivers/gpu/drm/i915/intel_color.c:1340:
+ if (!err_check(&hw_lut[i], &sw_lut[i], err))
-:167: WARNING:LONG_LINE: line over 100 characters
#167: FILE: drivers/gpu/drm/i915/intel_display.c:11608:
+ pipe_config->cgm_mode, pipe_config->gamma_mode, pipe_config->gamma_enable,
-:167: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#167: FILE: drivers/gpu/drm/i915/intel_display.c:11608:
+ DRM_DEBUG_KMS("cgm_mode:%d gamma_mode:%d gamma_enable:%d csc_enable:%d\n",
+ pipe_config->cgm_mode, pipe_config->gamma_mode, pipe_config->gamma_enable,
-:171: WARNING:LONG_LINE: line over 100 characters
#171: FILE: drivers/gpu/drm/i915/intel_display.c:11612:
+ pipe_config->csc_mode, pipe_config->gamma_mode, pipe_config->gamma_enable,
-:171: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#171: FILE: drivers/gpu/drm/i915/intel_display.c:11612:
+ DRM_DEBUG_KMS("csc_mode:%d gamma_mode:%d gamma_enable:%d csc_enable:%d\n",
+ pipe_config->csc_mode, pipe_config->gamma_mode, pipe_config->gamma_enable,
-:189: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#189: FILE: drivers/gpu/drm/i915/intel_display.c:12144:
+#define PIPE_CONF_CHECK_COLOR_LUT(name, bit_precision) do { \
+ if (!intel_color_lut_equal(current_config->name, \
+ pipe_config->name, bit_precision)) { \
+ pipe_config_err(adjust, __stringify(name), \
+ "hw_state doesn't match sw_state\n"); \
+ ret = false; \
+ } \
+} while (0)
-:189: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as '(name)' to avoid precedence issues
#189: FILE: drivers/gpu/drm/i915/intel_display.c:12144:
+#define PIPE_CONF_CHECK_COLOR_LUT(name, bit_precision) do { \
+ if (!intel_color_lut_equal(current_config->name, \
+ pipe_config->name, bit_precision)) { \
+ pipe_config_err(adjust, __stringify(name), \
+ "hw_state doesn't match sw_state\n"); \
+ ret = false; \
+ } \
+} while (0)
total: 3 errors, 6 warnings, 5 checks, 173 lines checked
2eedef369a97 drm/i915: Extract i9xx_read_luts()
-:13: WARNING:TYPO_SPELLING: 'withing' may be misspelled - perhaps 'within'?
#13:
v5: -Returned blob instead of assigning it internally withing the
-:79: WARNING:LONG_LINE: line over 100 characters
#79: FILE: drivers/gpu/drm/i915/intel_color.c:1384:
+ blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_RED_MASK, val), 8);
-:80: WARNING:LONG_LINE: line over 100 characters
#80: FILE: drivers/gpu/drm/i915/intel_color.c:1385:
+ blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_GREEN_MASK, val), 8);
-:81: WARNING:LONG_LINE: line over 100 characters
#81: FILE: drivers/gpu/drm/i915/intel_color.c:1386:
+ blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_BLUE_MASK, val), 8);
-:89: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#89: FILE: drivers/gpu/drm/i915/intel_color.c:1394:
+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);$
total: 0 errors, 5 warnings, 0 checks, 72 lines checked
308e9522b887 drm/i915: Extract chv_read_luts()
-:15: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#15:
-Renamed cherryview_get_gamma_config() to chv_read_cgm_gamma_lut() [Ville]
-:61: WARNING:LONG_LINE: line over 100 characters
#61: FILE: drivers/gpu/drm/i915/intel_color.c:1417:
+ blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
-:62: WARNING:LONG_LINE: line over 100 characters
#62: FILE: drivers/gpu/drm/i915/intel_color.c:1418:
+ blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, val), 10);
-:65: WARNING:LONG_LINE: line over 100 characters
#65: FILE: drivers/gpu/drm/i915/intel_color.c:1421:
+ blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, val), 10);
-:78: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#78: FILE: drivers/gpu/drm/i915/intel_color.c:1434:
+
+}
total: 0 errors, 4 warnings, 1 checks, 61 lines checked
e4c90e367a15 drm/i915: Extract i965_read_luts()
-:14: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#14:
-Renamed i965_get_gamma_config_10p6() to i965_read_gamma_lut_10p6() [Ville]
-:62: WARNING:LONG_LINE: line over 100 characters
#62: FILE: drivers/gpu/drm/i915/intel_color.c:1458:
+ blob_data[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val1) << 8 | REG_FIELD_GET(PALETTE_RED_MASK, val2);
-:63: WARNING:LONG_LINE: line over 100 characters
#63: FILE: drivers/gpu/drm/i915/intel_color.c:1459:
+ blob_data[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val1) << 8 | REG_FIELD_GET(PALETTE_GREEN_MASK, val2);
-:64: WARNING:LONG_LINE: line over 100 characters
#64: FILE: drivers/gpu/drm/i915/intel_color.c:1460:
+ blob_data[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val1) << 8 | REG_FIELD_GET(PALETTE_BLUE_MASK, val2) ;
-:64: WARNING:SPACING: space prohibited before semicolon
#64: FILE: drivers/gpu/drm/i915/intel_color.c:1460:
+ blob_data[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val1) << 8 | REG_FIELD_GET(PALETTE_BLUE_MASK, val2) ;
total: 0 errors, 5 warnings, 0 checks, 60 lines checked
b9f3d03fb0dc drm/i915: Extract icl_read_luts()
-:42: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#42: FILE: drivers/gpu/drm/i915/intel_color.c:1476:
+bdw_read_lut_10(struct intel_crtc_state *crtc_state,
+ u32 prec_index)
-:66: WARNING:LONG_LINE: line over 100 characters
#66: FILE: drivers/gpu/drm/i915/intel_color.c:1500:
+ blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_RED_MASK, val), 10);
-:67: WARNING:LONG_LINE: line over 100 characters
#67: FILE: drivers/gpu/drm/i915/intel_color.c:1501:
+ blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_GREEN_MASK, val), 10);
-:68: WARNING:LONG_LINE: line over 100 characters
#68: FILE: drivers/gpu/drm/i915/intel_color.c:1502:
+ blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_BLUE_MASK, val), 10);
-:93: CHECK:BRACES: braces {} should be used on all arms of this statement
#93: FILE: drivers/gpu/drm/i915/intel_color.c:1560:
+ if (INTEL_GEN(dev_priv) >= 11) {
[...]
else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
[...]
total: 0 errors, 3 warnings, 2 checks, 71 lines checked
7227ab5cc441 drm/i915: Extract glk_read_luts()
2eebe8f941ad drm/i915: Extract bdw_read_luts()
7510ed3f9d11 drm/i915: Extract ivb_read_luts()
-:27: ERROR:CODE_INDENT: code indent should use tabs where possible
#27: FILE: drivers/gpu/drm/i915/intel_color.c:1539:
+^I u32 prec_index)$
-:27: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#27: FILE: drivers/gpu/drm/i915/intel_color.c:1539:
+ivb_read_lut_10(struct intel_crtc_state *crtc_state,
+ u32 prec_index)
-:49: WARNING:LONG_LINE: line over 100 characters
#49: FILE: drivers/gpu/drm/i915/intel_color.c:1561:
+ blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_RED_MASK, val), 10);
-:50: WARNING:LONG_LINE: line over 100 characters
#50: FILE: drivers/gpu/drm/i915/intel_color.c:1562:
+ blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_GREEN_MASK, val), 10);
-:51: WARNING:LONG_LINE: line over 100 characters
#51: FILE: drivers/gpu/drm/i915/intel_color.c:1563:
+ blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_BLUE_MASK, val), 10);
-:64: WARNING:LONG_LINE: line over 100 characters
#64: FILE: drivers/gpu/drm/i915/intel_color.c:1576:
+ crtc_state->base.gamma_lut = ivb_read_lut_10(crtc_state, PAL_PREC_SPLIT_MODE | PAL_PREC_INDEX_VALUE(512));
-:68: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#68: FILE: drivers/gpu/drm/i915/intel_color.c:1580:
+
+}
total: 1 errors, 4 warnings, 2 checks, 63 lines checked
ea0a00bb8393 drm/i915: Extract ilk_read_luts()
-:60: WARNING:LONG_LINE: line over 100 characters
#60: FILE: drivers/gpu/drm/i915/intel_color.c:1603:
+ blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK, val), 10);
-:61: WARNING:LONG_LINE: line over 100 characters
#61: FILE: drivers/gpu/drm/i915/intel_color.c:1604:
+ blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_GREEN_MASK, val), 10);
-:62: WARNING:LONG_LINE: line over 100 characters
#62: FILE: drivers/gpu/drm/i915/intel_color.c:1605:
+ blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10);
total: 0 errors, 3 warnings, 0 checks, 64 lines checked
b8022e46e5bb FOR_TESTING_ONLY: Print rgb values of hw and sw blobs
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:16: WARNING:LONG_LINE: line over 100 characters
#16: FILE: drivers/gpu/drm/i915/intel_color.c:1306:
+ DRM_DEBUG_KMS("hw_lut->red=0x%x sw_lut->red=0x%x hw_lut->blue=0x%x sw_lut->blue=0x%x hw_lut->green=0x%x sw_lut->green=0x%x", hw_lut->red, sw_lut->red, hw_lut->blue, sw_lut->blue, hw_lut->green, sw_lut->green);
total: 0 errors, 2 warnings, 0 checks, 8 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm/i915: adding state checker for gamma lut values (rev8)
2019-05-14 9:43 [PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (12 preceding siblings ...)
2019-05-14 10:36 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: adding state checker for gamma lut values (rev8) Patchwork
@ 2019-05-14 10:42 ` Patchwork
2019-05-14 10:58 ` ✓ Fi.CI.BAT: success " Patchwork
` (5 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2019-05-14 10:42 UTC (permalink / raw)
To: Swati Sharma; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: adding state checker for gamma lut values (rev8)
URL : https://patchwork.freedesktop.org/series/58039/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Introduce vfunc read_luts() to create hw lut
Okay!
Commit: drm/i915: Enable intel_color_get_config()
Okay!
Commit: drm/i915: Add intel_color_lut_equal() to compare hw and sw gamma/degamma lut values
Okay!
Commit: drm/i915: Extract i9xx_read_luts()
+drivers/gpu/drm/i915/intel_color.c:1352:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:1352:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:1352:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:1352:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:1352:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:1352:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:1352:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:1352:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:1392:6: warning: symbol 'i9xx_read_luts' was not declared. Should it be static?
Commit: drm/i915: Extract chv_read_luts()
Okay!
Commit: drm/i915: Extract i965_read_luts()
Okay!
Commit: drm/i915: Extract icl_read_luts()
Okay!
Commit: drm/i915: Extract glk_read_luts()
Okay!
Commit: drm/i915: Extract bdw_read_luts()
Okay!
Commit: drm/i915: Extract ivb_read_luts()
Okay!
Commit: drm/i915: Extract ilk_read_luts()
Okay!
Commit: FOR_TESTING_ONLY: Print rgb values of hw and sw blobs
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: adding state checker for gamma lut values (rev8)
2019-05-14 9:43 [PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (13 preceding siblings ...)
2019-05-14 10:42 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-05-14 10:58 ` Patchwork
2019-05-14 14:17 ` ✗ Fi.CI.IGT: failure " Patchwork
` (4 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2019-05-14 10:58 UTC (permalink / raw)
To: Swati Sharma; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: adding state checker for gamma lut values (rev8)
URL : https://patchwork.freedesktop.org/series/58039/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6078 -> Patchwork_13014
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/
Known issues
------------
Here are the changes found in Patchwork_13014 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_basic@basic-bsd:
- fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6078/fi-apl-guc/igt@gem_exec_basic@basic-bsd.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/fi-apl-guc/igt@gem_exec_basic@basic-bsd.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6078/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
* igt@i915_selftest@live_execlists:
- fi-apl-guc: [PASS][5] -> [INCOMPLETE][6] ([fdo#103927] / [fdo#109720])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6078/fi-apl-guc/igt@i915_selftest@live_execlists.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/fi-apl-guc/igt@i915_selftest@live_execlists.html
#### Possible fixes ####
* igt@i915_selftest@live_contexts:
- fi-bdw-gvtdvm: [DMESG-FAIL][7] ([fdo#110235]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6078/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
* igt@i915_selftest@live_hangcheck:
- fi-skl-iommu: [INCOMPLETE][9] ([fdo#108602] / [fdo#108744]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6078/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html
- fi-apl-guc: [DMESG-FAIL][11] ([fdo#110620]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6078/fi-apl-guc/igt@i915_selftest@live_hangcheck.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/fi-apl-guc/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
[fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
[fdo#110620]: https://bugs.freedesktop.org/show_bug.cgi?id=110620
Participating hosts (54 -> 46)
------------------------------
Missing (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_6078 -> Patchwork_13014
CI_DRM_6078: c8c778558fd52abd3303d8ea324df788062adc97 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4984: 66c887d2f7a92a4a97acd9611d5342afc5d4f815 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13014: b8022e46e5bbcdaf0c1bd8337420ec3c8995fe9e @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b8022e46e5bb FOR_TESTING_ONLY: Print rgb values of hw and sw blobs
ea0a00bb8393 drm/i915: Extract ilk_read_luts()
7510ed3f9d11 drm/i915: Extract ivb_read_luts()
2eebe8f941ad drm/i915: Extract bdw_read_luts()
7227ab5cc441 drm/i915: Extract glk_read_luts()
b9f3d03fb0dc drm/i915: Extract icl_read_luts()
e4c90e367a15 drm/i915: Extract i965_read_luts()
308e9522b887 drm/i915: Extract chv_read_luts()
2eedef369a97 drm/i915: Extract i9xx_read_luts()
1eec6d06f200 drm/i915: Add intel_color_lut_equal() to compare hw and sw gamma/degamma lut values
316533acb64b drm/i915: Enable intel_color_get_config()
12495d94dac5 drm/i915: Introduce vfunc read_luts() to create hw lut
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915: adding state checker for gamma lut values (rev8)
2019-05-14 9:43 [PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (14 preceding siblings ...)
2019-05-14 10:58 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-05-14 14:17 ` Patchwork
2019-05-14 14:27 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: adding state checker for gamma lut values (rev9) Patchwork
` (3 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2019-05-14 14:17 UTC (permalink / raw)
To: Swati Sharma; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: adding state checker for gamma lut values (rev8)
URL : https://patchwork.freedesktop.org/series/58039/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6078_full -> Patchwork_13014_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_13014_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13014_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_13014_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_color@pipe-b-ctm-negative:
- shard-kbl: [PASS][1] -> [DMESG-WARN][2] +8 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6078/shard-kbl2/igt@kms_color@pipe-b-ctm-negative.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-kbl6/igt@kms_color@pipe-b-ctm-negative.html
- shard-skl: [PASS][3] -> [DMESG-WARN][4] +10 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6078/shard-skl5/igt@kms_color@pipe-b-ctm-negative.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-skl5/igt@kms_color@pipe-b-ctm-negative.html
* igt@kms_color@pipe-b-ctm-red-to-blue:
- shard-hsw: [PASS][5] -> [DMESG-WARN][6] +10 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6078/shard-hsw5/igt@kms_color@pipe-b-ctm-red-to-blue.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-hsw6/igt@kms_color@pipe-b-ctm-red-to-blue.html
* igt@kms_color@pipe-b-gamma:
- shard-snb: [PASS][7] -> [DMESG-WARN][8] +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6078/shard-snb4/igt@kms_color@pipe-b-gamma.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-snb2/igt@kms_color@pipe-b-gamma.html
* igt@kms_color@pipe-c-ctm-0-25:
- shard-apl: [PASS][9] -> [DMESG-WARN][10] +8 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6078/shard-apl8/igt@kms_color@pipe-c-ctm-0-25.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-apl7/igt@kms_color@pipe-c-ctm-0-25.html
* igt@kms_color@pipe-c-degamma:
- shard-skl: NOTRUN -> [DMESG-WARN][11] +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-skl5/igt@kms_color@pipe-c-degamma.html
* igt@runner@aborted:
- shard-hsw: NOTRUN -> ([FAIL][12], [FAIL][13], [FAIL][14], [FAIL][15], [FAIL][16], [FAIL][17], [FAIL][18], [FAIL][19], [FAIL][20], [FAIL][21], [FAIL][22])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-hsw4/igt@runner@aborted.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-hsw6/igt@runner@aborted.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-hsw8/igt@runner@aborted.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-hsw7/igt@runner@aborted.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-hsw8/igt@runner@aborted.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-hsw1/igt@runner@aborted.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-hsw1/igt@runner@aborted.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-hsw1/igt@runner@aborted.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-hsw1/igt@runner@aborted.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-hsw2/igt@runner@aborted.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-hsw4/igt@runner@aborted.html
- shard-snb: NOTRUN -> ([FAIL][23], [FAIL][24])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-snb2/igt@runner@aborted.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-snb2/igt@runner@aborted.html
- shard-kbl: NOTRUN -> ([FAIL][25], [FAIL][26], [FAIL][27], [FAIL][28], [FAIL][29], [FAIL][30], [FAIL][31], [FAIL][32], [FAIL][33])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-kbl2/igt@runner@aborted.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-kbl6/igt@runner@aborted.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-kbl1/igt@runner@aborted.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-kbl1/igt@runner@aborted.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-kbl4/igt@runner@aborted.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-kbl1/igt@runner@aborted.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-kbl2/igt@runner@aborted.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-kbl2/igt@runner@aborted.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-kbl1/igt@runner@aborted.html
- shard-apl: NOTRUN -> ([FAIL][34], [FAIL][35], [FAIL][36], [FAIL][37], [FAIL][38], [FAIL][39], [FAIL][40], [FAIL][41], [FAIL][42])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-apl7/igt@runner@aborted.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-apl6/igt@runner@aborted.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-apl5/igt@runner@aborted.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-apl8/igt@runner@aborted.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-apl7/igt@runner@aborted.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-apl6/igt@runner@aborted.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-apl4/igt@runner@aborted.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-apl1/igt@runner@aborted.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-apl3/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_13014_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_tiled_swapping@non-threaded:
- shard-kbl: [PASS][43] -> [FAIL][44] ([fdo#108686])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6078/shard-kbl1/igt@gem_tiled_swapping@non-threaded.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-kbl3/igt@gem_tiled_swapping@non-threaded.html
* igt@gem_workarounds@suspend-resume:
- shard-apl: [PASS][45] -> [DMESG-WARN][46] ([fdo#108566]) +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6078/shard-apl5/igt@gem_workarounds@suspend-resume.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-apl3/igt@gem_workarounds@suspend-resume.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [PASS][47] -> [FAIL][48] ([fdo#105363])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6078/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip_tiling@flip-changes-tiling-y:
- shard-skl: [PASS][49] -> [FAIL][50] ([fdo#107931] / [fdo#108303])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6078/shard-skl9/igt@kms_flip_tiling@flip-changes-tiling-y.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-skl9/igt@kms_flip_tiling@flip-changes-tiling-y.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-skl: [PASS][51] -> [INCOMPLETE][52] ([fdo#104108])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6078/shard-skl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-skl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][53] -> [FAIL][54] ([fdo#108145])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6078/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
#### Possible fixes ####
* igt@i915_pm_rpm@reg-read-ioctl:
- shard-skl: [INCOMPLETE][55] ([fdo#107807]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6078/shard-skl2/igt@i915_pm_rpm@reg-read-ioctl.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-skl7/igt@i915_pm_rpm@reg-read-ioctl.html
* igt@i915_pm_rpm@system-suspend-modeset:
- shard-skl: [INCOMPLETE][57] ([fdo#104108] / [fdo#107807]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6078/shard-skl7/igt@i915_pm_rpm@system-suspend-modeset.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-skl5/igt@i915_pm_rpm@system-suspend-modeset.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: [FAIL][59] ([fdo#105767]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6078/shard-hsw1/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-hsw7/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic:
- shard-hsw: [INCOMPLETE][61] ([fdo#103540]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6078/shard-hsw8/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-hsw4/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt:
- shard-skl: [FAIL][63] ([fdo#108040]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6078/shard-skl8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-skl2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][65] ([fdo#108566]) -> [PASS][66] +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6078/shard-apl5/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-apl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- shard-snb: [DMESG-WARN][67] -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6078/shard-snb5/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-snb1/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
* igt@tools_test@tools_test:
- shard-glk: [SKIP][69] ([fdo#109271]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6078/shard-glk4/igt@tools_test@tools_test.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/shard-glk7/igt@tools_test@tools_test.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#107931]: https://bugs.freedesktop.org/show_bug.cgi?id=107931
[fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108303]: https://bugs.freedesktop.org/show_bug.cgi?id=108303
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_6078 -> Patchwork_13014
CI_DRM_6078: c8c778558fd52abd3303d8ea324df788062adc97 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4984: 66c887d2f7a92a4a97acd9611d5342afc5d4f815 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13014: b8022e46e5bbcdaf0c1bd8337420ec3c8995fe9e @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13014/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: adding state checker for gamma lut values (rev9)
2019-05-14 9:43 [PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (15 preceding siblings ...)
2019-05-14 14:17 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2019-05-14 14:27 ` Patchwork
2019-05-14 14:33 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2019-05-14 14:27 UTC (permalink / raw)
To: Swati Sharma; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: adding state checker for gamma lut values (rev9)
URL : https://patchwork.freedesktop.org/series/58039/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
cb7a05f563c1 drm/i915: Introduce vfunc read_luts() to create hw lut
c687e9d64838 drm/i915: Enable intel_color_get_config()
a13dd89268a2 drm/i915: Add intel_color_lut_equal() to compare hw and sw gamma/degamma lut values
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#10:
-Corrected smatch warn "variable dereferenced before check" [Dan Carpenter]
-:85: ERROR:CODE_INDENT: code indent should use tabs where possible
#85: FILE: drivers/gpu/drm/i915/intel_color.c:1304:
+^I struct drm_color_lut *hw_lut, u32 err)$
-:85: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#85: FILE: drivers/gpu/drm/i915/intel_color.c:1304:
+static inline bool err_check(struct drm_color_lut *sw_lut,
+ struct drm_color_lut *hw_lut, u32 err)
-:87: WARNING:TABSTOP: Statements should start on a tabstop
#87: FILE: drivers/gpu/drm/i915/intel_color.c:1306:
+ return ((abs((long)hw_lut->red - sw_lut->red)) <= err) &&
-:88: ERROR:CODE_INDENT: code indent should use tabs where possible
#88: FILE: drivers/gpu/drm/i915/intel_color.c:1307:
+^I ((abs((long)hw_lut->blue - sw_lut->blue)) <= err) &&$
-:89: ERROR:CODE_INDENT: code indent should use tabs where possible
#89: FILE: drivers/gpu/drm/i915/intel_color.c:1308:
+^I ((abs((long)hw_lut->green - sw_lut->green)) <= err);$
-:120: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 17)
#120: FILE: drivers/gpu/drm/i915/intel_color.c:1339:
+ for (i = 0; i < sw_lut_size; i++) {
+ if (!err_check(&hw_lut[i], &sw_lut[i], err))
-:121: WARNING:TABSTOP: Statements should start on a tabstop
#121: FILE: drivers/gpu/drm/i915/intel_color.c:1340:
+ if (!err_check(&hw_lut[i], &sw_lut[i], err))
-:167: WARNING:LONG_LINE: line over 100 characters
#167: FILE: drivers/gpu/drm/i915/intel_display.c:11608:
+ pipe_config->cgm_mode, pipe_config->gamma_mode, pipe_config->gamma_enable,
-:167: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#167: FILE: drivers/gpu/drm/i915/intel_display.c:11608:
+ DRM_DEBUG_KMS("cgm_mode:%d gamma_mode:%d gamma_enable:%d csc_enable:%d\n",
+ pipe_config->cgm_mode, pipe_config->gamma_mode, pipe_config->gamma_enable,
-:171: WARNING:LONG_LINE: line over 100 characters
#171: FILE: drivers/gpu/drm/i915/intel_display.c:11612:
+ pipe_config->csc_mode, pipe_config->gamma_mode, pipe_config->gamma_enable,
-:171: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#171: FILE: drivers/gpu/drm/i915/intel_display.c:11612:
+ DRM_DEBUG_KMS("csc_mode:%d gamma_mode:%d gamma_enable:%d csc_enable:%d\n",
+ pipe_config->csc_mode, pipe_config->gamma_mode, pipe_config->gamma_enable,
-:189: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#189: FILE: drivers/gpu/drm/i915/intel_display.c:12144:
+#define PIPE_CONF_CHECK_COLOR_LUT(name, bit_precision) do { \
+ if (!intel_color_lut_equal(current_config->name, \
+ pipe_config->name, bit_precision)) { \
+ pipe_config_err(adjust, __stringify(name), \
+ "hw_state doesn't match sw_state\n"); \
+ ret = false; \
+ } \
+} while (0)
-:189: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as '(name)' to avoid precedence issues
#189: FILE: drivers/gpu/drm/i915/intel_display.c:12144:
+#define PIPE_CONF_CHECK_COLOR_LUT(name, bit_precision) do { \
+ if (!intel_color_lut_equal(current_config->name, \
+ pipe_config->name, bit_precision)) { \
+ pipe_config_err(adjust, __stringify(name), \
+ "hw_state doesn't match sw_state\n"); \
+ ret = false; \
+ } \
+} while (0)
total: 3 errors, 6 warnings, 5 checks, 173 lines checked
92f0143b746e drm/i915: Extract i9xx_read_luts()
-:13: WARNING:TYPO_SPELLING: 'withing' may be misspelled - perhaps 'within'?
#13:
v5: -Returned blob instead of assigning it internally withing the
-:79: WARNING:LONG_LINE: line over 100 characters
#79: FILE: drivers/gpu/drm/i915/intel_color.c:1384:
+ blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_RED_MASK, val), 8);
-:80: WARNING:LONG_LINE: line over 100 characters
#80: FILE: drivers/gpu/drm/i915/intel_color.c:1385:
+ blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_GREEN_MASK, val), 8);
-:81: WARNING:LONG_LINE: line over 100 characters
#81: FILE: drivers/gpu/drm/i915/intel_color.c:1386:
+ blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_BLUE_MASK, val), 8);
-:89: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#89: FILE: drivers/gpu/drm/i915/intel_color.c:1394:
+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);$
total: 0 errors, 5 warnings, 0 checks, 72 lines checked
aed86d8c5e91 drm/i915: Extract chv_read_luts()
-:15: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#15:
-Renamed cherryview_get_gamma_config() to chv_read_cgm_gamma_lut() [Ville]
-:61: WARNING:LONG_LINE: line over 100 characters
#61: FILE: drivers/gpu/drm/i915/intel_color.c:1417:
+ blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
-:62: WARNING:LONG_LINE: line over 100 characters
#62: FILE: drivers/gpu/drm/i915/intel_color.c:1418:
+ blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, val), 10);
-:65: WARNING:LONG_LINE: line over 100 characters
#65: FILE: drivers/gpu/drm/i915/intel_color.c:1421:
+ blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, val), 10);
-:78: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#78: FILE: drivers/gpu/drm/i915/intel_color.c:1434:
+
+}
total: 0 errors, 4 warnings, 1 checks, 61 lines checked
7e433388b2bb drm/i915: Extract i965_read_luts()
-:14: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#14:
-Renamed i965_get_gamma_config_10p6() to i965_read_gamma_lut_10p6() [Ville]
-:62: WARNING:LONG_LINE: line over 100 characters
#62: FILE: drivers/gpu/drm/i915/intel_color.c:1458:
+ blob_data[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val1) << 8 | REG_FIELD_GET(PALETTE_RED_MASK, val2);
-:63: WARNING:LONG_LINE: line over 100 characters
#63: FILE: drivers/gpu/drm/i915/intel_color.c:1459:
+ blob_data[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val1) << 8 | REG_FIELD_GET(PALETTE_GREEN_MASK, val2);
-:64: WARNING:LONG_LINE: line over 100 characters
#64: FILE: drivers/gpu/drm/i915/intel_color.c:1460:
+ blob_data[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val1) << 8 | REG_FIELD_GET(PALETTE_BLUE_MASK, val2) ;
-:64: WARNING:SPACING: space prohibited before semicolon
#64: FILE: drivers/gpu/drm/i915/intel_color.c:1460:
+ blob_data[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val1) << 8 | REG_FIELD_GET(PALETTE_BLUE_MASK, val2) ;
total: 0 errors, 5 warnings, 0 checks, 60 lines checked
109f2d52ff4d drm/i915: Extract icl_read_luts()
-:42: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#42: FILE: drivers/gpu/drm/i915/intel_color.c:1476:
+bdw_read_lut_10(struct intel_crtc_state *crtc_state,
+ u32 prec_index)
-:66: WARNING:LONG_LINE: line over 100 characters
#66: FILE: drivers/gpu/drm/i915/intel_color.c:1500:
+ blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_RED_MASK, val), 10);
-:67: WARNING:LONG_LINE: line over 100 characters
#67: FILE: drivers/gpu/drm/i915/intel_color.c:1501:
+ blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_GREEN_MASK, val), 10);
-:68: WARNING:LONG_LINE: line over 100 characters
#68: FILE: drivers/gpu/drm/i915/intel_color.c:1502:
+ blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_BLUE_MASK, val), 10);
-:93: CHECK:BRACES: braces {} should be used on all arms of this statement
#93: FILE: drivers/gpu/drm/i915/intel_color.c:1560:
+ if (INTEL_GEN(dev_priv) >= 11) {
[...]
else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
[...]
total: 0 errors, 3 warnings, 2 checks, 71 lines checked
f371c0809856 drm/i915: Extract glk_read_luts()
13e33d98fba6 drm/i915: Extract bdw_read_luts()
8aadfb2b3ffe drm/i915: Extract ivb_read_luts()
-:27: ERROR:CODE_INDENT: code indent should use tabs where possible
#27: FILE: drivers/gpu/drm/i915/intel_color.c:1539:
+^I u32 prec_index)$
-:27: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#27: FILE: drivers/gpu/drm/i915/intel_color.c:1539:
+ivb_read_lut_10(struct intel_crtc_state *crtc_state,
+ u32 prec_index)
-:49: WARNING:LONG_LINE: line over 100 characters
#49: FILE: drivers/gpu/drm/i915/intel_color.c:1561:
+ blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_RED_MASK, val), 10);
-:50: WARNING:LONG_LINE: line over 100 characters
#50: FILE: drivers/gpu/drm/i915/intel_color.c:1562:
+ blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_GREEN_MASK, val), 10);
-:51: WARNING:LONG_LINE: line over 100 characters
#51: FILE: drivers/gpu/drm/i915/intel_color.c:1563:
+ blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_BLUE_MASK, val), 10);
-:64: WARNING:LONG_LINE: line over 100 characters
#64: FILE: drivers/gpu/drm/i915/intel_color.c:1576:
+ crtc_state->base.gamma_lut = ivb_read_lut_10(crtc_state, PAL_PREC_SPLIT_MODE | PAL_PREC_INDEX_VALUE(512));
-:68: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#68: FILE: drivers/gpu/drm/i915/intel_color.c:1580:
+
+}
total: 1 errors, 4 warnings, 2 checks, 63 lines checked
d821530ccc4c drm/i915: Extract ilk_read_luts()
-:60: WARNING:LONG_LINE: line over 100 characters
#60: FILE: drivers/gpu/drm/i915/intel_color.c:1603:
+ blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK, val), 10);
-:61: WARNING:LONG_LINE: line over 100 characters
#61: FILE: drivers/gpu/drm/i915/intel_color.c:1604:
+ blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_GREEN_MASK, val), 10);
-:62: WARNING:LONG_LINE: line over 100 characters
#62: FILE: drivers/gpu/drm/i915/intel_color.c:1605:
+ blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10);
total: 0 errors, 3 warnings, 0 checks, 64 lines checked
3c319ee505b6 FOR_TESTING_ONLY: Print rgb values of hw and sw blobs
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:16: WARNING:LONG_LINE: line over 100 characters
#16: FILE: drivers/gpu/drm/i915/intel_color.c:1306:
+ DRM_DEBUG_KMS("hw_lut->red=0x%x sw_lut->red=0x%x hw_lut->blue=0x%x sw_lut->blue=0x%x hw_lut->green=0x%x sw_lut->green=0x%x", hw_lut->red, sw_lut->red, hw_lut->blue, sw_lut->blue, hw_lut->green, sw_lut->green);
total: 0 errors, 2 warnings, 0 checks, 8 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm/i915: adding state checker for gamma lut values (rev9)
2019-05-14 9:43 [PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (16 preceding siblings ...)
2019-05-14 14:27 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: adding state checker for gamma lut values (rev9) Patchwork
@ 2019-05-14 14:33 ` Patchwork
2019-05-14 15:17 ` ✓ Fi.CI.BAT: success " Patchwork
2019-05-14 22:14 ` ✗ Fi.CI.IGT: failure " Patchwork
19 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2019-05-14 14:33 UTC (permalink / raw)
To: Swati Sharma; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: adding state checker for gamma lut values (rev9)
URL : https://patchwork.freedesktop.org/series/58039/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Introduce vfunc read_luts() to create hw lut
Okay!
Commit: drm/i915: Enable intel_color_get_config()
Okay!
Commit: drm/i915: Add intel_color_lut_equal() to compare hw and sw gamma/degamma lut values
Okay!
Commit: drm/i915: Extract i9xx_read_luts()
+drivers/gpu/drm/i915/intel_color.c:1352:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:1352:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:1352:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:1352:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:1352:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:1352:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:1352:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:1352:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:1392:6: warning: symbol 'i9xx_read_luts' was not declared. Should it be static?
Commit: drm/i915: Extract chv_read_luts()
Okay!
Commit: drm/i915: Extract i965_read_luts()
Okay!
Commit: drm/i915: Extract icl_read_luts()
Okay!
Commit: drm/i915: Extract glk_read_luts()
Okay!
Commit: drm/i915: Extract bdw_read_luts()
Okay!
Commit: drm/i915: Extract ivb_read_luts()
Okay!
Commit: drm/i915: Extract ilk_read_luts()
Okay!
Commit: FOR_TESTING_ONLY: Print rgb values of hw and sw blobs
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: adding state checker for gamma lut values (rev9)
2019-05-14 9:43 [PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (17 preceding siblings ...)
2019-05-14 14:33 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-05-14 15:17 ` Patchwork
2019-05-14 22:14 ` ✗ Fi.CI.IGT: failure " Patchwork
19 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2019-05-14 15:17 UTC (permalink / raw)
To: Swati Sharma; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: adding state checker for gamma lut values (rev9)
URL : https://patchwork.freedesktop.org/series/58039/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6080 -> Patchwork_13015
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/
Known issues
------------
Here are the changes found in Patchwork_13015 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html
* igt@i915_selftest@live_evict:
- fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([fdo#107709])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/fi-bsw-kefka/igt@i915_selftest@live_evict.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/fi-bsw-kefka/igt@i915_selftest@live_evict.html
* igt@i915_selftest@live_execlists:
- fi-apl-guc: [PASS][5] -> [INCOMPLETE][6] ([fdo#103927] / [fdo#109720])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/fi-apl-guc/igt@i915_selftest@live_execlists.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/fi-apl-guc/igt@i915_selftest@live_execlists.html
#### Possible fixes ####
* igt@i915_selftest@live_contexts:
- fi-bdw-gvtdvm: [DMESG-FAIL][7] ([fdo#110235]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
* igt@i915_selftest@live_hangcheck:
- fi-apl-guc: [DMESG-FAIL][9] ([fdo#110620]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/fi-apl-guc/igt@i915_selftest@live_hangcheck.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/fi-apl-guc/igt@i915_selftest@live_hangcheck.html
#### Warnings ####
* igt@runner@aborted:
- fi-apl-guc: [FAIL][11] ([fdo#110622]) -> [FAIL][12] ([fdo#108622] / [fdo#109720])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/fi-apl-guc/igt@runner@aborted.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/fi-apl-guc/igt@runner@aborted.html
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
[fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
[fdo#110620]: https://bugs.freedesktop.org/show_bug.cgi?id=110620
[fdo#110622]: https://bugs.freedesktop.org/show_bug.cgi?id=110622
Participating hosts (54 -> 46)
------------------------------
Missing (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_6080 -> Patchwork_13015
CI_DRM_6080: 6c6b621677cc0d3616de3dab025d967aa2c43877 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4985: dc0598498a16d43b0bc9cbc654491d4e6dc56626 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13015: 3c319ee505b6e02d5024963430217f9fde2089a2 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3c319ee505b6 FOR_TESTING_ONLY: Print rgb values of hw and sw blobs
d821530ccc4c drm/i915: Extract ilk_read_luts()
8aadfb2b3ffe drm/i915: Extract ivb_read_luts()
13e33d98fba6 drm/i915: Extract bdw_read_luts()
f371c0809856 drm/i915: Extract glk_read_luts()
109f2d52ff4d drm/i915: Extract icl_read_luts()
7e433388b2bb drm/i915: Extract i965_read_luts()
aed86d8c5e91 drm/i915: Extract chv_read_luts()
92f0143b746e drm/i915: Extract i9xx_read_luts()
a13dd89268a2 drm/i915: Add intel_color_lut_equal() to compare hw and sw gamma/degamma lut values
c687e9d64838 drm/i915: Enable intel_color_get_config()
cb7a05f563c1 drm/i915: Introduce vfunc read_luts() to create hw lut
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915: adding state checker for gamma lut values (rev9)
2019-05-14 9:43 [PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (18 preceding siblings ...)
2019-05-14 15:17 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-05-14 22:14 ` Patchwork
19 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2019-05-14 22:14 UTC (permalink / raw)
To: Swati Sharma; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: adding state checker for gamma lut values (rev9)
URL : https://patchwork.freedesktop.org/series/58039/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6080_full -> Patchwork_13015_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_13015_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13015_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_13015_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_available_modes_crc@available_mode_test_crc:
- shard-snb: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-snb4/igt@kms_available_modes_crc@available_mode_test_crc.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-snb6/igt@kms_available_modes_crc@available_mode_test_crc.html
* igt@kms_color@pipe-a-ctm-negative:
- shard-skl: [PASS][3] -> [DMESG-WARN][4] +11 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-skl5/igt@kms_color@pipe-a-ctm-negative.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-skl2/igt@kms_color@pipe-a-ctm-negative.html
* igt@kms_color@pipe-b-ctm-negative:
- shard-kbl: [PASS][5] -> [DMESG-WARN][6] +7 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-kbl7/igt@kms_color@pipe-b-ctm-negative.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-kbl4/igt@kms_color@pipe-b-ctm-negative.html
* igt@kms_color@pipe-b-ctm-red-to-blue:
- shard-hsw: [PASS][7] -> [DMESG-WARN][8] +11 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-hsw2/igt@kms_color@pipe-b-ctm-red-to-blue.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-hsw6/igt@kms_color@pipe-b-ctm-red-to-blue.html
* igt@kms_color@pipe-b-degamma:
- shard-skl: NOTRUN -> [DMESG-WARN][9]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-skl8/igt@kms_color@pipe-b-degamma.html
* igt@kms_color@pipe-c-ctm-0-25:
- shard-apl: [PASS][10] -> [DMESG-WARN][11] +6 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-apl1/igt@kms_color@pipe-c-ctm-0-25.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-apl2/igt@kms_color@pipe-c-ctm-0-25.html
* igt@runner@aborted:
- shard-hsw: NOTRUN -> ([FAIL][12], [FAIL][13], [FAIL][14], [FAIL][15], [FAIL][16], [FAIL][17], [FAIL][18], [FAIL][19], [FAIL][20], [FAIL][21], [FAIL][22], [FAIL][23])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-hsw6/igt@runner@aborted.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-hsw7/igt@runner@aborted.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-hsw7/igt@runner@aborted.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-hsw7/igt@runner@aborted.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-hsw6/igt@runner@aborted.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-hsw7/igt@runner@aborted.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-hsw6/igt@runner@aborted.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-hsw1/igt@runner@aborted.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-hsw4/igt@runner@aborted.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-hsw2/igt@runner@aborted.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-hsw1/igt@runner@aborted.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-hsw1/igt@runner@aborted.html
- shard-snb: NOTRUN -> [FAIL][24]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-snb6/igt@runner@aborted.html
- shard-kbl: NOTRUN -> ([FAIL][25], [FAIL][26], [FAIL][27], [FAIL][28], [FAIL][29], [FAIL][30], [FAIL][31], [FAIL][32])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-kbl3/igt@runner@aborted.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-kbl1/igt@runner@aborted.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-kbl1/igt@runner@aborted.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-kbl1/igt@runner@aborted.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-kbl4/igt@runner@aborted.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-kbl3/igt@runner@aborted.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-kbl4/igt@runner@aborted.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-kbl7/igt@runner@aborted.html
- shard-apl: NOTRUN -> ([FAIL][33], [FAIL][34], [FAIL][35], [FAIL][36], [FAIL][37], [FAIL][38], [FAIL][39])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-apl1/igt@runner@aborted.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-apl4/igt@runner@aborted.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-apl4/igt@runner@aborted.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-apl2/igt@runner@aborted.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-apl8/igt@runner@aborted.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-apl2/igt@runner@aborted.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-apl5/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_13015_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_mmap_gtt@big-copy:
- shard-iclb: [PASS][40] -> [INCOMPLETE][41] ([fdo#107713] / [fdo#109100])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-iclb7/igt@gem_mmap_gtt@big-copy.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-iclb7/igt@gem_mmap_gtt@big-copy.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [PASS][42] -> [DMESG-WARN][43] ([fdo#108566]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-apl3/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_pm_rpm@debugfs-read:
- shard-skl: [PASS][44] -> [INCOMPLETE][45] ([fdo#107807])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-skl3/igt@i915_pm_rpm@debugfs-read.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-skl6/igt@i915_pm_rpm@debugfs-read.html
* igt@i915_suspend@forcewake:
- shard-skl: [PASS][46] -> [INCOMPLETE][47] ([fdo#104108] / [fdo#107773]) +1 similar issue
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-skl1/igt@i915_suspend@forcewake.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-skl9/igt@i915_suspend@forcewake.html
* igt@kms_draw_crc@draw-method-rgb565-blt-xtiled:
- shard-snb: [PASS][48] -> [SKIP][49] ([fdo#109271])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-snb4/igt@kms_draw_crc@draw-method-rgb565-blt-xtiled.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-snb6/igt@kms_draw_crc@draw-method-rgb565-blt-xtiled.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
- shard-iclb: [PASS][50] -> [FAIL][51] ([fdo#103167]) +5 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-badstride:
- shard-skl: [PASS][52] -> [FAIL][53] ([fdo#108040]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-skl10/igt@kms_frontbuffer_tracking@fbc-badstride.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-skl4/igt@kms_frontbuffer_tracking@fbc-badstride.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-rte:
- shard-iclb: [PASS][54] -> [FAIL][55] ([fdo#103167] / [fdo#110378])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render:
- shard-skl: [PASS][56] -> [FAIL][57] ([fdo#103167])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][58] -> [FAIL][59] ([fdo#108145])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][60] -> [SKIP][61] ([fdo#109441]) +2 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-iclb3/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_psr@suspend:
- shard-iclb: [PASS][62] -> [INCOMPLETE][63] ([fdo#107713])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-iclb5/igt@kms_psr@suspend.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-iclb3/igt@kms_psr@suspend.html
#### Possible fixes ####
* igt@gem_ctx_isolation@vcs0-s3:
- shard-kbl: [DMESG-WARN][64] ([fdo#103313]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-kbl4/igt@gem_ctx_isolation@vcs0-s3.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-kbl3/igt@gem_ctx_isolation@vcs0-s3.html
* igt@i915_pm_rpm@gem-pread:
- shard-skl: [INCOMPLETE][66] ([fdo#107807]) -> [PASS][67]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-skl4/igt@i915_pm_rpm@gem-pread.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-skl8/igt@i915_pm_rpm@gem-pread.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: [INCOMPLETE][68] ([fdo#109507]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-skl4/igt@kms_flip@flip-vs-suspend-interruptible.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-skl10/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite:
- shard-iclb: [FAIL][70] ([fdo#103167]) -> [PASS][71] +3 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-apl: [DMESG-WARN][72] ([fdo#108566]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-apl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-apl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [FAIL][74] ([fdo#103166]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-iclb1/igt@kms_plane_lowres@pipe-a-tiling-x.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-iclb1/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][76] ([fdo#109642]) -> [PASS][77] +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-iclb3/igt@kms_psr2_su@frontbuffer.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [SKIP][78] ([fdo#109441]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-iclb5/igt@kms_psr@psr2_sprite_blt.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
#### Warnings ####
* igt@gem_mmap_gtt@forked-big-copy-odd:
- shard-iclb: [INCOMPLETE][80] ([fdo#107713] / [fdo#109100]) -> [TIMEOUT][81] ([fdo#109673])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6080/shard-iclb3/igt@gem_mmap_gtt@forked-big-copy-odd.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/shard-iclb8/igt@gem_mmap_gtt@forked-big-copy-odd.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
[fdo#110378]: https://bugs.freedesktop.org/show_bug.cgi?id=110378
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_6080 -> Patchwork_13015
CI_DRM_6080: 6c6b621677cc0d3616de3dab025d967aa2c43877 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4985: dc0598498a16d43b0bc9cbc654491d4e6dc56626 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13015: 3c319ee505b6e02d5024963430217f9fde2089a2 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13015/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread