* [PATCH 00/10] Add further support for PHYTEC phyBOARD-Segin
@ 2019-07-09 7:19 ` Stefan Riedmueller
0 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, martyn.welch, linux-kernel, linux-imx, kernel,
festevam, linux-arm-kernel
This patchstack adjusts the already existing naming for the PHYTEC
phyBOARD-Segin to the PHYTEC naming scheme that is already used with the
phyCORE-i.MX 6 and the phyBOARD-Mira.
Furthermore it introduces some small fixes and adds support for the PHYTEC
phyCORE-i.MX 6ULL which also comes with the phyBORAD-Segin. It comes in a
full featured option with either NAND flash or eMMC and a low cost option
only with NAND flash.
Stefan Riedmueller (10):
ARM: dts: imx6ul: phyboard-segin: Rename dts to PHYTEC name scheme
ARM: dts: imx6ul: segin: Add boot media to dts filename
ARM: dts: imx6ul: segin: Reduce eth drive strength
ARM: dts: imx6ul: segin: Fix LED naming for phyCORE and PEB-EVAL-01
ARM: dts: imx6ul: segin: Make FEC and ethphy configurable in dts
ARM: dts: imx6ul: segin: Only enable NAND if it is populated
ARM: dts: imx6ul: phycore: Add eMMC at usdhc2
ARM: dts: imx6ul: segin: Move ECSPI interface to board include file
ARM: dts: imx6ul: segin: Move machine include to dts files
ARM: dts: imx6ull: Add support for PHYTEC phyBOARD-Segin with i.MX
6ULL
arch/arm/boot/dts/Makefile | 5 +-
...-pcl063.dtsi => imx6ul-phytec-phycore-som.dtsi} | 51 ++++++++----
...ull.dts => imx6ul-phytec-segin-ff-rdk-nand.dts} | 42 +++++-----
...1.dtsi => imx6ul-phytec-segin-peb-eval-01.dtsi} | 16 ++--
...hyboard-segin.dtsi => imx6ul-phytec-segin.dtsi} | 31 ++++++--
arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi | 24 ++++++
.../boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts | 93 ++++++++++++++++++++++
.../boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts | 93 ++++++++++++++++++++++
.../boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts | 45 +++++++++++
.../boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi | 19 +++++
arch/arm/boot/dts/imx6ull-phytec-segin.dtsi | 38 +++++++++
11 files changed, 409 insertions(+), 48 deletions(-)
rename arch/arm/boot/dts/{imx6ul-phytec-pcl063.dtsi => imx6ul-phytec-phycore-som.dtsi} (72%)
rename arch/arm/boot/dts/{imx6ul-phytec-phyboard-segin-full.dts => imx6ul-phytec-segin-ff-rdk-nand.dts} (51%)
rename arch/arm/boot/dts/{imx6ul-phytec-peb-eval-01.dtsi => imx6ul-phytec-segin-peb-eval-01.dtsi} (84%)
rename arch/arm/boot/dts/{imx6ul-phytec-phyboard-segin.dtsi => imx6ul-phytec-segin.dtsi} (91%)
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin.dtsi
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 37+ messages in thread* [PATCH 00/10] Add further support for PHYTEC phyBOARD-Segin
@ 2019-07-09 7:19 ` Stefan Riedmueller
0 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, martyn.welch, linux-kernel, linux-imx, kernel,
festevam, linux-arm-kernel
This patchstack adjusts the already existing naming for the PHYTEC
phyBOARD-Segin to the PHYTEC naming scheme that is already used with the
phyCORE-i.MX 6 and the phyBOARD-Mira.
Furthermore it introduces some small fixes and adds support for the PHYTEC
phyCORE-i.MX 6ULL which also comes with the phyBORAD-Segin. It comes in a
full featured option with either NAND flash or eMMC and a low cost option
only with NAND flash.
Stefan Riedmueller (10):
ARM: dts: imx6ul: phyboard-segin: Rename dts to PHYTEC name scheme
ARM: dts: imx6ul: segin: Add boot media to dts filename
ARM: dts: imx6ul: segin: Reduce eth drive strength
ARM: dts: imx6ul: segin: Fix LED naming for phyCORE and PEB-EVAL-01
ARM: dts: imx6ul: segin: Make FEC and ethphy configurable in dts
ARM: dts: imx6ul: segin: Only enable NAND if it is populated
ARM: dts: imx6ul: phycore: Add eMMC at usdhc2
ARM: dts: imx6ul: segin: Move ECSPI interface to board include file
ARM: dts: imx6ul: segin: Move machine include to dts files
ARM: dts: imx6ull: Add support for PHYTEC phyBOARD-Segin with i.MX
6ULL
arch/arm/boot/dts/Makefile | 5 +-
...-pcl063.dtsi => imx6ul-phytec-phycore-som.dtsi} | 51 ++++++++----
...ull.dts => imx6ul-phytec-segin-ff-rdk-nand.dts} | 42 +++++-----
...1.dtsi => imx6ul-phytec-segin-peb-eval-01.dtsi} | 16 ++--
...hyboard-segin.dtsi => imx6ul-phytec-segin.dtsi} | 31 ++++++--
arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi | 24 ++++++
.../boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts | 93 ++++++++++++++++++++++
.../boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts | 93 ++++++++++++++++++++++
.../boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts | 45 +++++++++++
.../boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi | 19 +++++
arch/arm/boot/dts/imx6ull-phytec-segin.dtsi | 38 +++++++++
11 files changed, 409 insertions(+), 48 deletions(-)
rename arch/arm/boot/dts/{imx6ul-phytec-pcl063.dtsi => imx6ul-phytec-phycore-som.dtsi} (72%)
rename arch/arm/boot/dts/{imx6ul-phytec-phyboard-segin-full.dts => imx6ul-phytec-segin-ff-rdk-nand.dts} (51%)
rename arch/arm/boot/dts/{imx6ul-phytec-peb-eval-01.dtsi => imx6ul-phytec-segin-peb-eval-01.dtsi} (84%)
rename arch/arm/boot/dts/{imx6ul-phytec-phyboard-segin.dtsi => imx6ul-phytec-segin.dtsi} (91%)
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin.dtsi
--
2.7.4
^ permalink raw reply [flat|nested] 37+ messages in thread* [PATCH 01/10] ARM: dts: imx6ul: phyboard-segin: Rename dts to PHYTEC name scheme
2019-07-09 7:19 ` Stefan Riedmueller
(?)
@ 2019-07-09 7:19 ` Stefan Riedmueller
-1 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, linux-kernel, linux-arm-kernel, martyn.welch, kernel,
festevam, linux-imx
Use the same name scheme for the phyBOARD-Segin and the phyCORE-i.MX
6UL as is used for the PHYTEC phyBOARD-Mira and phyCORE-i.MX 6.
This is only a cosmetic change and there is no functional change
intended.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/Makefile | 2 +-
.../{imx6ul-phytec-pcl063.dtsi => imx6ul-phytec-phycore-som.dtsi} | 2 +-
...tec-phyboard-segin-full.dts => imx6ul-phytec-segin-ff-rdk.dts} | 8 ++++----
...ytec-peb-eval-01.dtsi => imx6ul-phytec-segin-peb-eval-01.dtsi} | 0
...imx6ul-phytec-phyboard-segin.dtsi => imx6ul-phytec-segin.dtsi} | 2 +-
5 files changed, 7 insertions(+), 7 deletions(-)
rename arch/arm/boot/dts/{imx6ul-phytec-pcl063.dtsi => imx6ul-phytec-phycore-som.dtsi} (98%)
rename arch/arm/boot/dts/{imx6ul-phytec-phyboard-segin-full.dts => imx6ul-phytec-segin-ff-rdk.dts} (84%)
rename arch/arm/boot/dts/{imx6ul-phytec-peb-eval-01.dtsi => imx6ul-phytec-segin-peb-eval-01.dtsi} (100%)
rename arch/arm/boot/dts/{imx6ul-phytec-phyboard-segin.dtsi => imx6ul-phytec-segin.dtsi} (99%)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index dab2914fa293..e1924b06f3cb 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -573,7 +573,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-opos6uldev.dtb \
imx6ul-pico-hobbit.dtb \
imx6ul-pico-pi.dtb \
- imx6ul-phytec-phyboard-segin-full.dtb \
+ imx6ul-phytec-segin-ff-rdk.dtb \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
diff --git a/arch/arm/boot/dts/imx6ul-phytec-pcl063.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
similarity index 98%
rename from arch/arm/boot/dts/imx6ul-phytec-pcl063.dtsi
rename to arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
index fc2997449b49..bff13d0eb064 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-pcl063.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
@@ -10,7 +10,7 @@
#include "imx6ul.dtsi"
/ {
- model = "Phytec phyCORE i.MX6 UltraLite";
+ model = "PHYTEC phyCORE-i.MX6 UltraLite";
compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
chosen {
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin-full.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk.dts
similarity index 84%
rename from arch/arm/boot/dts/imx6ul-phytec-phyboard-segin-full.dts
rename to arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk.dts
index b6a1407a9d44..1e59183a2f7c 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin-full.dts
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk.dts
@@ -5,12 +5,12 @@
*/
/dts-v1/;
-#include "imx6ul-phytec-pcl063.dtsi"
-#include "imx6ul-phytec-phyboard-segin.dtsi"
-#include "imx6ul-phytec-peb-eval-01.dtsi"
+#include "imx6ul-phytec-phycore-som.dtsi"
+#include "imx6ul-phytec-segin.dtsi"
+#include "imx6ul-phytec-segin-peb-eval-01.dtsi"
/ {
- model = "Phytec phyBOARD-Segin i.MX6 UltraLite Full Featured";
+ model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured";
compatible = "phytec,imx6ul-pbacd10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
};
diff --git a/arch/arm/boot/dts/imx6ul-phytec-peb-eval-01.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi
similarity index 100%
rename from arch/arm/boot/dts/imx6ul-phytec-peb-eval-01.dtsi
rename to arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
similarity index 99%
rename from arch/arm/boot/dts/imx6ul-phytec-phyboard-segin.dtsi
rename to arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
index 7bf439a77d2c..78425c3290a1 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
@@ -5,7 +5,7 @@
*/
/ {
- model = "Phytec phyBOARD-Segin i.MX6 UltraLite";
+ model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite";
compatible = "phytec,imx6ul-pbacd-10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
aliases {
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 01/10] ARM: dts: imx6ul: phyboard-segin: Rename dts to PHYTEC name scheme
@ 2019-07-09 7:19 ` Stefan Riedmueller
0 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, martyn.welch, linux-kernel, linux-imx, kernel,
festevam, linux-arm-kernel
Use the same name scheme for the phyBOARD-Segin and the phyCORE-i.MX
6UL as is used for the PHYTEC phyBOARD-Mira and phyCORE-i.MX 6.
This is only a cosmetic change and there is no functional change
intended.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/Makefile | 2 +-
.../{imx6ul-phytec-pcl063.dtsi => imx6ul-phytec-phycore-som.dtsi} | 2 +-
...tec-phyboard-segin-full.dts => imx6ul-phytec-segin-ff-rdk.dts} | 8 ++++----
...ytec-peb-eval-01.dtsi => imx6ul-phytec-segin-peb-eval-01.dtsi} | 0
...imx6ul-phytec-phyboard-segin.dtsi => imx6ul-phytec-segin.dtsi} | 2 +-
5 files changed, 7 insertions(+), 7 deletions(-)
rename arch/arm/boot/dts/{imx6ul-phytec-pcl063.dtsi => imx6ul-phytec-phycore-som.dtsi} (98%)
rename arch/arm/boot/dts/{imx6ul-phytec-phyboard-segin-full.dts => imx6ul-phytec-segin-ff-rdk.dts} (84%)
rename arch/arm/boot/dts/{imx6ul-phytec-peb-eval-01.dtsi => imx6ul-phytec-segin-peb-eval-01.dtsi} (100%)
rename arch/arm/boot/dts/{imx6ul-phytec-phyboard-segin.dtsi => imx6ul-phytec-segin.dtsi} (99%)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index dab2914fa293..e1924b06f3cb 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -573,7 +573,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-opos6uldev.dtb \
imx6ul-pico-hobbit.dtb \
imx6ul-pico-pi.dtb \
- imx6ul-phytec-phyboard-segin-full.dtb \
+ imx6ul-phytec-segin-ff-rdk.dtb \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
diff --git a/arch/arm/boot/dts/imx6ul-phytec-pcl063.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
similarity index 98%
rename from arch/arm/boot/dts/imx6ul-phytec-pcl063.dtsi
rename to arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
index fc2997449b49..bff13d0eb064 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-pcl063.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
@@ -10,7 +10,7 @@
#include "imx6ul.dtsi"
/ {
- model = "Phytec phyCORE i.MX6 UltraLite";
+ model = "PHYTEC phyCORE-i.MX6 UltraLite";
compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
chosen {
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin-full.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk.dts
similarity index 84%
rename from arch/arm/boot/dts/imx6ul-phytec-phyboard-segin-full.dts
rename to arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk.dts
index b6a1407a9d44..1e59183a2f7c 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin-full.dts
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk.dts
@@ -5,12 +5,12 @@
*/
/dts-v1/;
-#include "imx6ul-phytec-pcl063.dtsi"
-#include "imx6ul-phytec-phyboard-segin.dtsi"
-#include "imx6ul-phytec-peb-eval-01.dtsi"
+#include "imx6ul-phytec-phycore-som.dtsi"
+#include "imx6ul-phytec-segin.dtsi"
+#include "imx6ul-phytec-segin-peb-eval-01.dtsi"
/ {
- model = "Phytec phyBOARD-Segin i.MX6 UltraLite Full Featured";
+ model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured";
compatible = "phytec,imx6ul-pbacd10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
};
diff --git a/arch/arm/boot/dts/imx6ul-phytec-peb-eval-01.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi
similarity index 100%
rename from arch/arm/boot/dts/imx6ul-phytec-peb-eval-01.dtsi
rename to arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
similarity index 99%
rename from arch/arm/boot/dts/imx6ul-phytec-phyboard-segin.dtsi
rename to arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
index 7bf439a77d2c..78425c3290a1 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
@@ -5,7 +5,7 @@
*/
/ {
- model = "Phytec phyBOARD-Segin i.MX6 UltraLite";
+ model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite";
compatible = "phytec,imx6ul-pbacd-10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
aliases {
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 01/10] ARM: dts: imx6ul: phyboard-segin: Rename dts to PHYTEC name scheme
@ 2019-07-09 7:19 ` Stefan Riedmueller
0 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, martyn.welch, linux-kernel, linux-imx, kernel,
festevam, linux-arm-kernel
Use the same name scheme for the phyBOARD-Segin and the phyCORE-i.MX
6UL as is used for the PHYTEC phyBOARD-Mira and phyCORE-i.MX 6.
This is only a cosmetic change and there is no functional change
intended.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/Makefile | 2 +-
.../{imx6ul-phytec-pcl063.dtsi => imx6ul-phytec-phycore-som.dtsi} | 2 +-
...tec-phyboard-segin-full.dts => imx6ul-phytec-segin-ff-rdk.dts} | 8 ++++----
...ytec-peb-eval-01.dtsi => imx6ul-phytec-segin-peb-eval-01.dtsi} | 0
...imx6ul-phytec-phyboard-segin.dtsi => imx6ul-phytec-segin.dtsi} | 2 +-
5 files changed, 7 insertions(+), 7 deletions(-)
rename arch/arm/boot/dts/{imx6ul-phytec-pcl063.dtsi => imx6ul-phytec-phycore-som.dtsi} (98%)
rename arch/arm/boot/dts/{imx6ul-phytec-phyboard-segin-full.dts => imx6ul-phytec-segin-ff-rdk.dts} (84%)
rename arch/arm/boot/dts/{imx6ul-phytec-peb-eval-01.dtsi => imx6ul-phytec-segin-peb-eval-01.dtsi} (100%)
rename arch/arm/boot/dts/{imx6ul-phytec-phyboard-segin.dtsi => imx6ul-phytec-segin.dtsi} (99%)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index dab2914fa293..e1924b06f3cb 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -573,7 +573,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-opos6uldev.dtb \
imx6ul-pico-hobbit.dtb \
imx6ul-pico-pi.dtb \
- imx6ul-phytec-phyboard-segin-full.dtb \
+ imx6ul-phytec-segin-ff-rdk.dtb \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
diff --git a/arch/arm/boot/dts/imx6ul-phytec-pcl063.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
similarity index 98%
rename from arch/arm/boot/dts/imx6ul-phytec-pcl063.dtsi
rename to arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
index fc2997449b49..bff13d0eb064 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-pcl063.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
@@ -10,7 +10,7 @@
#include "imx6ul.dtsi"
/ {
- model = "Phytec phyCORE i.MX6 UltraLite";
+ model = "PHYTEC phyCORE-i.MX6 UltraLite";
compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
chosen {
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin-full.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk.dts
similarity index 84%
rename from arch/arm/boot/dts/imx6ul-phytec-phyboard-segin-full.dts
rename to arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk.dts
index b6a1407a9d44..1e59183a2f7c 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin-full.dts
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk.dts
@@ -5,12 +5,12 @@
*/
/dts-v1/;
-#include "imx6ul-phytec-pcl063.dtsi"
-#include "imx6ul-phytec-phyboard-segin.dtsi"
-#include "imx6ul-phytec-peb-eval-01.dtsi"
+#include "imx6ul-phytec-phycore-som.dtsi"
+#include "imx6ul-phytec-segin.dtsi"
+#include "imx6ul-phytec-segin-peb-eval-01.dtsi"
/ {
- model = "Phytec phyBOARD-Segin i.MX6 UltraLite Full Featured";
+ model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured";
compatible = "phytec,imx6ul-pbacd10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
};
diff --git a/arch/arm/boot/dts/imx6ul-phytec-peb-eval-01.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi
similarity index 100%
rename from arch/arm/boot/dts/imx6ul-phytec-peb-eval-01.dtsi
rename to arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
similarity index 99%
rename from arch/arm/boot/dts/imx6ul-phytec-phyboard-segin.dtsi
rename to arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
index 7bf439a77d2c..78425c3290a1 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
@@ -5,7 +5,7 @@
*/
/ {
- model = "Phytec phyBOARD-Segin i.MX6 UltraLite";
+ model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite";
compatible = "phytec,imx6ul-pbacd-10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
aliases {
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 02/10] ARM: dts: imx6ul: segin: Add boot media to dts filename
2019-07-09 7:19 ` Stefan Riedmueller
(?)
@ 2019-07-09 7:19 ` Stefan Riedmueller
-1 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, linux-kernel, linux-arm-kernel, martyn.welch, kernel,
festevam, linux-imx
There is now a PHYTEC phyCORE-i.MX 6UL with eMMC instead of NAND flash
available. The dts filename needs to reflect that to differentiate both.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/Makefile | 2 +-
...l-phytec-segin-ff-rdk.dts => imx6ul-phytec-segin-ff-rdk-nand.dts} | 5 +++--
2 files changed, 4 insertions(+), 3 deletions(-)
rename arch/arm/boot/dts/{imx6ul-phytec-segin-ff-rdk.dts => imx6ul-phytec-segin-ff-rdk-nand.dts} (85%)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e1924b06f3cb..668b57c8cc57 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -573,7 +573,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-opos6uldev.dtb \
imx6ul-pico-hobbit.dtb \
imx6ul-pico-pi.dtb \
- imx6ul-phytec-segin-ff-rdk.dtb \
+ imx6ul-phytec-segin-ff-rdk-nand.dtb \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
similarity index 85%
rename from arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk.dts
rename to arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
index 1e59183a2f7c..dc06029c5701 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk.dts
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
@@ -10,8 +10,9 @@
#include "imx6ul-phytec-segin-peb-eval-01.dtsi"
/ {
- model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured";
- compatible = "phytec,imx6ul-pbacd10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
+ model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND";
+ compatible = "phytec,imx6ul-pbacd10-nand", "phytec,imx6ul-pbacd10",
+ "phytec,imx6ul-pcl063", "fsl,imx6ul";
};
&adc1 {
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 02/10] ARM: dts: imx6ul: segin: Add boot media to dts filename
@ 2019-07-09 7:19 ` Stefan Riedmueller
0 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, martyn.welch, linux-kernel, linux-imx, kernel,
festevam, linux-arm-kernel
There is now a PHYTEC phyCORE-i.MX 6UL with eMMC instead of NAND flash
available. The dts filename needs to reflect that to differentiate both.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/Makefile | 2 +-
...l-phytec-segin-ff-rdk.dts => imx6ul-phytec-segin-ff-rdk-nand.dts} | 5 +++--
2 files changed, 4 insertions(+), 3 deletions(-)
rename arch/arm/boot/dts/{imx6ul-phytec-segin-ff-rdk.dts => imx6ul-phytec-segin-ff-rdk-nand.dts} (85%)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e1924b06f3cb..668b57c8cc57 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -573,7 +573,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-opos6uldev.dtb \
imx6ul-pico-hobbit.dtb \
imx6ul-pico-pi.dtb \
- imx6ul-phytec-segin-ff-rdk.dtb \
+ imx6ul-phytec-segin-ff-rdk-nand.dtb \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
similarity index 85%
rename from arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk.dts
rename to arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
index 1e59183a2f7c..dc06029c5701 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk.dts
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
@@ -10,8 +10,9 @@
#include "imx6ul-phytec-segin-peb-eval-01.dtsi"
/ {
- model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured";
- compatible = "phytec,imx6ul-pbacd10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
+ model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND";
+ compatible = "phytec,imx6ul-pbacd10-nand", "phytec,imx6ul-pbacd10",
+ "phytec,imx6ul-pcl063", "fsl,imx6ul";
};
&adc1 {
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 02/10] ARM: dts: imx6ul: segin: Add boot media to dts filename
@ 2019-07-09 7:19 ` Stefan Riedmueller
0 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, martyn.welch, linux-kernel, linux-imx, kernel,
festevam, linux-arm-kernel
There is now a PHYTEC phyCORE-i.MX 6UL with eMMC instead of NAND flash
available. The dts filename needs to reflect that to differentiate both.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/Makefile | 2 +-
...l-phytec-segin-ff-rdk.dts => imx6ul-phytec-segin-ff-rdk-nand.dts} | 5 +++--
2 files changed, 4 insertions(+), 3 deletions(-)
rename arch/arm/boot/dts/{imx6ul-phytec-segin-ff-rdk.dts => imx6ul-phytec-segin-ff-rdk-nand.dts} (85%)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e1924b06f3cb..668b57c8cc57 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -573,7 +573,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-opos6uldev.dtb \
imx6ul-pico-hobbit.dtb \
imx6ul-pico-pi.dtb \
- imx6ul-phytec-segin-ff-rdk.dtb \
+ imx6ul-phytec-segin-ff-rdk-nand.dtb \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
similarity index 85%
rename from arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk.dts
rename to arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
index 1e59183a2f7c..dc06029c5701 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk.dts
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
@@ -10,8 +10,9 @@
#include "imx6ul-phytec-segin-peb-eval-01.dtsi"
/ {
- model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured";
- compatible = "phytec,imx6ul-pbacd10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
+ model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND";
+ compatible = "phytec,imx6ul-pbacd10-nand", "phytec,imx6ul-pbacd10",
+ "phytec,imx6ul-pcl063", "fsl,imx6ul";
};
&adc1 {
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH 02/10] ARM: dts: imx6ul: segin: Add boot media to dts filename
2019-07-09 7:19 ` Stefan Riedmueller
@ 2019-07-23 3:10 ` Shawn Guo
-1 siblings, 0 replies; 37+ messages in thread
From: Shawn Guo @ 2019-07-23 3:10 UTC (permalink / raw)
To: Stefan Riedmueller
Cc: s.hauer, robh+dt, mark.rutland, devicetree, martyn.welch,
linux-kernel, linux-imx, kernel, festevam, linux-arm-kernel
On Tue, Jul 09, 2019 at 09:19:19AM +0200, Stefan Riedmueller wrote:
> There is now a PHYTEC phyCORE-i.MX 6UL with eMMC instead of NAND flash
> available. The dts filename needs to reflect that to differentiate both.
>
> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
> ---
> arch/arm/boot/dts/Makefile | 2 +-
> ...l-phytec-segin-ff-rdk.dts => imx6ul-phytec-segin-ff-rdk-nand.dts} | 5 +++--
> 2 files changed, 4 insertions(+), 3 deletions(-)
> rename arch/arm/boot/dts/{imx6ul-phytec-segin-ff-rdk.dts => imx6ul-phytec-segin-ff-rdk-nand.dts} (85%)
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index e1924b06f3cb..668b57c8cc57 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -573,7 +573,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
> imx6ul-opos6uldev.dtb \
> imx6ul-pico-hobbit.dtb \
> imx6ul-pico-pi.dtb \
> - imx6ul-phytec-segin-ff-rdk.dtb \
> + imx6ul-phytec-segin-ff-rdk-nand.dtb \
> imx6ul-tx6ul-0010.dtb \
> imx6ul-tx6ul-0011.dtb \
> imx6ul-tx6ul-mainboard.dtb \
> diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
> similarity index 85%
> rename from arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk.dts
> rename to arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
> index 1e59183a2f7c..dc06029c5701 100644
> --- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk.dts
> +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
> @@ -10,8 +10,9 @@
> #include "imx6ul-phytec-segin-peb-eval-01.dtsi"
>
> / {
> - model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured";
> - compatible = "phytec,imx6ul-pbacd10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
> + model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND";
> + compatible = "phytec,imx6ul-pbacd10-nand", "phytec,imx6ul-pbacd10",
The board compatibles need to be documented.
Shawn
> + "phytec,imx6ul-pcl063", "fsl,imx6ul";
> };
>
> &adc1 {
> --
> 2.7.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH 02/10] ARM: dts: imx6ul: segin: Add boot media to dts filename
@ 2019-07-23 3:10 ` Shawn Guo
0 siblings, 0 replies; 37+ messages in thread
From: Shawn Guo @ 2019-07-23 3:10 UTC (permalink / raw)
To: Stefan Riedmueller
Cc: mark.rutland, devicetree, martyn.welch, s.hauer, linux-kernel,
robh+dt, linux-imx, kernel, festevam, linux-arm-kernel
On Tue, Jul 09, 2019 at 09:19:19AM +0200, Stefan Riedmueller wrote:
> There is now a PHYTEC phyCORE-i.MX 6UL with eMMC instead of NAND flash
> available. The dts filename needs to reflect that to differentiate both.
>
> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
> ---
> arch/arm/boot/dts/Makefile | 2 +-
> ...l-phytec-segin-ff-rdk.dts => imx6ul-phytec-segin-ff-rdk-nand.dts} | 5 +++--
> 2 files changed, 4 insertions(+), 3 deletions(-)
> rename arch/arm/boot/dts/{imx6ul-phytec-segin-ff-rdk.dts => imx6ul-phytec-segin-ff-rdk-nand.dts} (85%)
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index e1924b06f3cb..668b57c8cc57 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -573,7 +573,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
> imx6ul-opos6uldev.dtb \
> imx6ul-pico-hobbit.dtb \
> imx6ul-pico-pi.dtb \
> - imx6ul-phytec-segin-ff-rdk.dtb \
> + imx6ul-phytec-segin-ff-rdk-nand.dtb \
> imx6ul-tx6ul-0010.dtb \
> imx6ul-tx6ul-0011.dtb \
> imx6ul-tx6ul-mainboard.dtb \
> diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
> similarity index 85%
> rename from arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk.dts
> rename to arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
> index 1e59183a2f7c..dc06029c5701 100644
> --- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk.dts
> +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
> @@ -10,8 +10,9 @@
> #include "imx6ul-phytec-segin-peb-eval-01.dtsi"
>
> / {
> - model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured";
> - compatible = "phytec,imx6ul-pbacd10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
> + model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND";
> + compatible = "phytec,imx6ul-pbacd10-nand", "phytec,imx6ul-pbacd10",
The board compatibles need to be documented.
Shawn
> + "phytec,imx6ul-pcl063", "fsl,imx6ul";
> };
>
> &adc1 {
> --
> 2.7.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 03/10] ARM: dts: imx6ul: segin: Reduce eth drive strength
2019-07-09 7:19 ` Stefan Riedmueller
(?)
@ 2019-07-09 7:19 ` Stefan Riedmueller
-1 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, linux-kernel, linux-arm-kernel, martyn.welch, kernel,
festevam, linux-imx
Reduce the drive strength for the MDC, MDIO and TX pins of FEC1 and FEC2
on the phyBOARD-Segin to improve signal quality and EMC. Also disable
internal pull-ups on the MDC and MDIO pins.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 12 ++++++------
arch/arm/boot/dts/imx6ul-phytec-segin.dtsi | 8 ++++----
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
index bff13d0eb064..1b745582911c 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
@@ -93,16 +93,16 @@
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
- MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
- MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x10010
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x10010
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
- MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
- MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x17059
>;
};
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
index 78425c3290a1..28ba3a4c4c74 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
@@ -230,10 +230,10 @@
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
- MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
- MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
- MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
- MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010
+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010
+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010
>;
};
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 03/10] ARM: dts: imx6ul: segin: Reduce eth drive strength
@ 2019-07-09 7:19 ` Stefan Riedmueller
0 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, martyn.welch, linux-kernel, linux-imx, kernel,
festevam, linux-arm-kernel
Reduce the drive strength for the MDC, MDIO and TX pins of FEC1 and FEC2
on the phyBOARD-Segin to improve signal quality and EMC. Also disable
internal pull-ups on the MDC and MDIO pins.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 12 ++++++------
arch/arm/boot/dts/imx6ul-phytec-segin.dtsi | 8 ++++----
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
index bff13d0eb064..1b745582911c 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
@@ -93,16 +93,16 @@
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
- MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
- MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x10010
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x10010
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
- MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
- MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x17059
>;
};
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
index 78425c3290a1..28ba3a4c4c74 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
@@ -230,10 +230,10 @@
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
- MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
- MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
- MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
- MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010
+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010
+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010
>;
};
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 03/10] ARM: dts: imx6ul: segin: Reduce eth drive strength
@ 2019-07-09 7:19 ` Stefan Riedmueller
0 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, martyn.welch, linux-kernel, linux-imx, kernel,
festevam, linux-arm-kernel
Reduce the drive strength for the MDC, MDIO and TX pins of FEC1 and FEC2
on the phyBOARD-Segin to improve signal quality and EMC. Also disable
internal pull-ups on the MDC and MDIO pins.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 12 ++++++------
arch/arm/boot/dts/imx6ul-phytec-segin.dtsi | 8 ++++----
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
index bff13d0eb064..1b745582911c 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
@@ -93,16 +93,16 @@
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
- MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
- MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x10010
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x10010
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
- MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
- MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x17059
>;
};
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
index 78425c3290a1..28ba3a4c4c74 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
@@ -230,10 +230,10 @@
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
- MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
- MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
- MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
- MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010
+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010
+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010
>;
};
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 04/10] ARM: dts: imx6ul: segin: Fix LED naming for phyCORE and PEB-EVAL-01
2019-07-09 7:19 ` Stefan Riedmueller
(?)
@ 2019-07-09 7:19 ` Stefan Riedmueller
-1 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, linux-kernel, linux-arm-kernel, martyn.welch, kernel,
festevam, linux-imx
Fix node name for the user LEDs to prevent the pinctrl of the phyCORE's
leds node from being overwritten. Also use more generic names for user
LEDs.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 3 +--
arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi | 16 +++++++++-------
2 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
index 1b745582911c..73266b4a889b 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
@@ -31,8 +31,7 @@
pinctrl-0 = <&pinctrl_gpioleds_som>;
compatible = "gpio-leds";
- led_green {
- label = "phycore:green";
+ phycore-green {
gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi
index e2f38f39a6ad..2f3fd32a1167 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi
@@ -21,20 +21,22 @@
};
};
- user_leds: leds {
+ user_leds: user-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_user_leds>;
status = "disabled";
- led_yellow {
- gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "default-on";
+ user-led1 {
+ gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "gpio";
+ default-state = "on";
};
- led_red {
- gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "default-on";
+ user-led2 {
+ gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "gpio";
+ default-state = "on";
};
};
};
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 04/10] ARM: dts: imx6ul: segin: Fix LED naming for phyCORE and PEB-EVAL-01
@ 2019-07-09 7:19 ` Stefan Riedmueller
0 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, martyn.welch, linux-kernel, linux-imx, kernel,
festevam, linux-arm-kernel
Fix node name for the user LEDs to prevent the pinctrl of the phyCORE's
leds node from being overwritten. Also use more generic names for user
LEDs.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 3 +--
arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi | 16 +++++++++-------
2 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
index 1b745582911c..73266b4a889b 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
@@ -31,8 +31,7 @@
pinctrl-0 = <&pinctrl_gpioleds_som>;
compatible = "gpio-leds";
- led_green {
- label = "phycore:green";
+ phycore-green {
gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi
index e2f38f39a6ad..2f3fd32a1167 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi
@@ -21,20 +21,22 @@
};
};
- user_leds: leds {
+ user_leds: user-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_user_leds>;
status = "disabled";
- led_yellow {
- gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "default-on";
+ user-led1 {
+ gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "gpio";
+ default-state = "on";
};
- led_red {
- gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "default-on";
+ user-led2 {
+ gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "gpio";
+ default-state = "on";
};
};
};
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 04/10] ARM: dts: imx6ul: segin: Fix LED naming for phyCORE and PEB-EVAL-01
@ 2019-07-09 7:19 ` Stefan Riedmueller
0 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, martyn.welch, linux-kernel, linux-imx, kernel,
festevam, linux-arm-kernel
Fix node name for the user LEDs to prevent the pinctrl of the phyCORE's
leds node from being overwritten. Also use more generic names for user
LEDs.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 3 +--
arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi | 16 +++++++++-------
2 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
index 1b745582911c..73266b4a889b 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
@@ -31,8 +31,7 @@
pinctrl-0 = <&pinctrl_gpioleds_som>;
compatible = "gpio-leds";
- led_green {
- label = "phycore:green";
+ phycore-green {
gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi
index e2f38f39a6ad..2f3fd32a1167 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi
@@ -21,20 +21,22 @@
};
};
- user_leds: leds {
+ user_leds: user-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_user_leds>;
status = "disabled";
- led_yellow {
- gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "default-on";
+ user-led1 {
+ gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "gpio";
+ default-state = "on";
};
- led_red {
- gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "default-on";
+ user-led2 {
+ gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "gpio";
+ default-state = "on";
};
};
};
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 05/10] ARM: dts: imx6ul: segin: Make FEC and ethphy configurable in dts
2019-07-09 7:19 ` Stefan Riedmueller
(?)
@ 2019-07-09 7:19 ` Stefan Riedmueller
-1 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, linux-kernel, linux-arm-kernel, martyn.welch, kernel,
festevam, linux-imx
To disable Ethernet interfaces in case they are not populated
make the FEC and Ethernet PHY status configurable in the dts files.
Also change the Ethernet PHYs labels to make them correspond to
the MDIO address.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 7 ++++---
arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 12 ++++++++++++
arch/arm/boot/dts/imx6ul-phytec-segin.dtsi | 5 +++--
3 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
index 73266b4a889b..fee7a7e938ee 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
@@ -42,20 +42,21 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
- phy-handle = <ðphy0>;
- status = "okay";
+ phy-handle = <ðphy1>;
+ status = "disabled";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
- ethphy0: ethernet-phy@1 {
+ ethphy1: ethernet-phy@1 {
reg = <1>;
interrupt-parent = <&gpio1>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
+ status = "disabled";
};
};
};
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
index dc06029c5701..81a82dd65019 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
@@ -34,6 +34,18 @@
status = "okay";
};
+ðphy1 {
+ status = "okay";
+};
+
+ðphy2 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+};
+
&fec2 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
index 28ba3a4c4c74..7cd24ec40c36 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
@@ -107,7 +107,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rmii";
- phy-handle = <ðphy1>;
+ phy-handle = <ðphy2>;
status = "disabled";
};
@@ -160,11 +160,12 @@
};
&mdio {
- ethphy1: ethernet-phy@2 {
+ ethphy2: ethernet-phy@2 {
reg = <2>;
micrel,led-mode = <1>;
clocks = <&clks IMX6UL_CLK_ENET2_REF>;
clock-names = "rmii-ref";
+ status = "disabled";
};
};
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 05/10] ARM: dts: imx6ul: segin: Make FEC and ethphy configurable in dts
@ 2019-07-09 7:19 ` Stefan Riedmueller
0 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, martyn.welch, linux-kernel, linux-imx, kernel,
festevam, linux-arm-kernel
To disable Ethernet interfaces in case they are not populated
make the FEC and Ethernet PHY status configurable in the dts files.
Also change the Ethernet PHYs labels to make them correspond to
the MDIO address.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 7 ++++---
arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 12 ++++++++++++
arch/arm/boot/dts/imx6ul-phytec-segin.dtsi | 5 +++--
3 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
index 73266b4a889b..fee7a7e938ee 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
@@ -42,20 +42,21 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
- phy-handle = <ðphy0>;
- status = "okay";
+ phy-handle = <ðphy1>;
+ status = "disabled";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
- ethphy0: ethernet-phy@1 {
+ ethphy1: ethernet-phy@1 {
reg = <1>;
interrupt-parent = <&gpio1>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
+ status = "disabled";
};
};
};
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
index dc06029c5701..81a82dd65019 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
@@ -34,6 +34,18 @@
status = "okay";
};
+ðphy1 {
+ status = "okay";
+};
+
+ðphy2 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+};
+
&fec2 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
index 28ba3a4c4c74..7cd24ec40c36 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
@@ -107,7 +107,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rmii";
- phy-handle = <ðphy1>;
+ phy-handle = <ðphy2>;
status = "disabled";
};
@@ -160,11 +160,12 @@
};
&mdio {
- ethphy1: ethernet-phy@2 {
+ ethphy2: ethernet-phy@2 {
reg = <2>;
micrel,led-mode = <1>;
clocks = <&clks IMX6UL_CLK_ENET2_REF>;
clock-names = "rmii-ref";
+ status = "disabled";
};
};
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 05/10] ARM: dts: imx6ul: segin: Make FEC and ethphy configurable in dts
@ 2019-07-09 7:19 ` Stefan Riedmueller
0 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, martyn.welch, linux-kernel, linux-imx, kernel,
festevam, linux-arm-kernel
To disable Ethernet interfaces in case they are not populated
make the FEC and Ethernet PHY status configurable in the dts files.
Also change the Ethernet PHYs labels to make them correspond to
the MDIO address.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 7 ++++---
arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 12 ++++++++++++
arch/arm/boot/dts/imx6ul-phytec-segin.dtsi | 5 +++--
3 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
index 73266b4a889b..fee7a7e938ee 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
@@ -42,20 +42,21 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
- phy-handle = <ðphy0>;
- status = "okay";
+ phy-handle = <ðphy1>;
+ status = "disabled";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
- ethphy0: ethernet-phy@1 {
+ ethphy1: ethernet-phy@1 {
reg = <1>;
interrupt-parent = <&gpio1>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
+ status = "disabled";
};
};
};
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
index dc06029c5701..81a82dd65019 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
@@ -34,6 +34,18 @@
status = "okay";
};
+ðphy1 {
+ status = "okay";
+};
+
+ðphy2 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+};
+
&fec2 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
index 28ba3a4c4c74..7cd24ec40c36 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
@@ -107,7 +107,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rmii";
- phy-handle = <ðphy1>;
+ phy-handle = <ðphy2>;
status = "disabled";
};
@@ -160,11 +160,12 @@
};
&mdio {
- ethphy1: ethernet-phy@2 {
+ ethphy2: ethernet-phy@2 {
reg = <2>;
micrel,led-mode = <1>;
clocks = <&clks IMX6UL_CLK_ENET2_REF>;
clock-names = "rmii-ref";
+ status = "disabled";
};
};
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 06/10] ARM: dts: imx6ul: segin: Only enable NAND if it is populated
2019-07-09 7:19 ` Stefan Riedmueller
(?)
@ 2019-07-09 7:19 ` Stefan Riedmueller
-1 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, linux-kernel, linux-arm-kernel, martyn.welch, kernel,
festevam, linux-imx
The phyCORE-i.MX 6UL/ULL now comes either with NAND flash or eMMC. We
have to configure the populated memory type in the device tree files. So
the GPMI node gets disabled by default and only enabled if populated.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 2 +-
arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 4 ++++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
index fee7a7e938ee..de6ffbb0183c 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
@@ -65,7 +65,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
- status = "okay";
+ status = "disabled";
};
&i2c1 {
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
index 81a82dd65019..c6ef13685a7c 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
@@ -50,6 +50,10 @@
status = "okay";
};
+&gpmi {
+ status = "okay";
+};
+
&i2c_rtc {
status = "okay";
};
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 06/10] ARM: dts: imx6ul: segin: Only enable NAND if it is populated
@ 2019-07-09 7:19 ` Stefan Riedmueller
0 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, martyn.welch, linux-kernel, linux-imx, kernel,
festevam, linux-arm-kernel
The phyCORE-i.MX 6UL/ULL now comes either with NAND flash or eMMC. We
have to configure the populated memory type in the device tree files. So
the GPMI node gets disabled by default and only enabled if populated.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 2 +-
arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 4 ++++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
index fee7a7e938ee..de6ffbb0183c 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
@@ -65,7 +65,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
- status = "okay";
+ status = "disabled";
};
&i2c1 {
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
index 81a82dd65019..c6ef13685a7c 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
@@ -50,6 +50,10 @@
status = "okay";
};
+&gpmi {
+ status = "okay";
+};
+
&i2c_rtc {
status = "okay";
};
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 06/10] ARM: dts: imx6ul: segin: Only enable NAND if it is populated
@ 2019-07-09 7:19 ` Stefan Riedmueller
0 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, martyn.welch, linux-kernel, linux-imx, kernel,
festevam, linux-arm-kernel
The phyCORE-i.MX 6UL/ULL now comes either with NAND flash or eMMC. We
have to configure the populated memory type in the device tree files. So
the GPMI node gets disabled by default and only enabled if populated.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 2 +-
arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 4 ++++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
index fee7a7e938ee..de6ffbb0183c 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
@@ -65,7 +65,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
- status = "okay";
+ status = "disabled";
};
&i2c1 {
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
index 81a82dd65019..c6ef13685a7c 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
@@ -50,6 +50,10 @@
status = "okay";
};
+&gpmi {
+ status = "okay";
+};
+
&i2c_rtc {
status = "okay";
};
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 07/10] ARM: dts: imx6ul: phycore: Add eMMC at usdhc2
2019-07-09 7:19 ` Stefan Riedmueller
(?)
@ 2019-07-09 7:19 ` Stefan Riedmueller
-1 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, linux-kernel, linux-arm-kernel, martyn.welch, kernel,
festevam, linux-imx
The phyCORE-i.MX 6UL/ULL now can have eMMC instead of the NAND flash
memory. Add the eMMC node and disable it by default so it can be enabled
in case it is populated.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
index de6ffbb0183c..09a313daedb8 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
@@ -90,6 +90,15 @@
status = "okay";
};
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <8>;
+ no-1-8-v;
+ non-removable;
+ status = "disabled";
+};
+
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
@@ -145,4 +154,19 @@
>;
};
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
+ >;
+ };
+
};
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 07/10] ARM: dts: imx6ul: phycore: Add eMMC at usdhc2
@ 2019-07-09 7:19 ` Stefan Riedmueller
0 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, martyn.welch, linux-kernel, linux-imx, kernel,
festevam, linux-arm-kernel
The phyCORE-i.MX 6UL/ULL now can have eMMC instead of the NAND flash
memory. Add the eMMC node and disable it by default so it can be enabled
in case it is populated.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
index de6ffbb0183c..09a313daedb8 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
@@ -90,6 +90,15 @@
status = "okay";
};
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <8>;
+ no-1-8-v;
+ non-removable;
+ status = "disabled";
+};
+
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
@@ -145,4 +154,19 @@
>;
};
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
+ >;
+ };
+
};
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 07/10] ARM: dts: imx6ul: phycore: Add eMMC at usdhc2
@ 2019-07-09 7:19 ` Stefan Riedmueller
0 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, martyn.welch, linux-kernel, linux-imx, kernel,
festevam, linux-arm-kernel
The phyCORE-i.MX 6UL/ULL now can have eMMC instead of the NAND flash
memory. Add the eMMC node and disable it by default so it can be enabled
in case it is populated.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
index de6ffbb0183c..09a313daedb8 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
@@ -90,6 +90,15 @@
status = "okay";
};
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <8>;
+ no-1-8-v;
+ non-removable;
+ status = "disabled";
+};
+
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
@@ -145,4 +154,19 @@
>;
};
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
+ >;
+ };
+
};
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 08/10] ARM: dts: imx6ul: segin: Move ECSPI interface to board include file
2019-07-09 7:19 ` Stefan Riedmueller
(?)
@ 2019-07-09 7:19 ` Stefan Riedmueller
-1 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, linux-kernel, linux-arm-kernel, martyn.welch, kernel,
festevam, linux-imx
The ECSPI interface is available on the expansion connector of every
PHYTEC phyBOARD-Segin. Move its definition to the board include file
for better reuse.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 14 --------------
arch/arm/boot/dts/imx6ul-phytec-segin.dtsi | 16 ++++++++++++++++
2 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
index c6ef13685a7c..32d90c67a6f2 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
@@ -28,9 +28,6 @@
};
&ecspi3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi3>;
- cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
status = "okay";
};
@@ -93,14 +90,3 @@
&usdhc1 {
status = "okay";
};
-
-&iomuxc {
- pinctrl_ecspi3: ecspi3grp {
- fsl,pins = <
- MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0
- MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
- MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
- MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0
- >;
- };
-};
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
index 7cd24ec40c36..8d5f8dc6ad58 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
@@ -103,6 +103,13 @@
assigned-clock-rates = <786432000>;
};
+&ecspi3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3>;
+ cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+};
+
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
@@ -225,6 +232,15 @@
>;
};
+ pinctrl_ecspi3: ecspi3grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0
+ MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
+ MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
+ MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0
+ >;
+ };
+
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 08/10] ARM: dts: imx6ul: segin: Move ECSPI interface to board include file
@ 2019-07-09 7:19 ` Stefan Riedmueller
0 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, martyn.welch, linux-kernel, linux-imx, kernel,
festevam, linux-arm-kernel
The ECSPI interface is available on the expansion connector of every
PHYTEC phyBOARD-Segin. Move its definition to the board include file
for better reuse.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 14 --------------
arch/arm/boot/dts/imx6ul-phytec-segin.dtsi | 16 ++++++++++++++++
2 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
index c6ef13685a7c..32d90c67a6f2 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
@@ -28,9 +28,6 @@
};
&ecspi3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi3>;
- cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
status = "okay";
};
@@ -93,14 +90,3 @@
&usdhc1 {
status = "okay";
};
-
-&iomuxc {
- pinctrl_ecspi3: ecspi3grp {
- fsl,pins = <
- MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0
- MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
- MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
- MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0
- >;
- };
-};
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
index 7cd24ec40c36..8d5f8dc6ad58 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
@@ -103,6 +103,13 @@
assigned-clock-rates = <786432000>;
};
+&ecspi3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3>;
+ cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+};
+
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
@@ -225,6 +232,15 @@
>;
};
+ pinctrl_ecspi3: ecspi3grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0
+ MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
+ MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
+ MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0
+ >;
+ };
+
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 08/10] ARM: dts: imx6ul: segin: Move ECSPI interface to board include file
@ 2019-07-09 7:19 ` Stefan Riedmueller
0 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, martyn.welch, linux-kernel, linux-imx, kernel,
festevam, linux-arm-kernel
The ECSPI interface is available on the expansion connector of every
PHYTEC phyBOARD-Segin. Move its definition to the board include file
for better reuse.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 14 --------------
arch/arm/boot/dts/imx6ul-phytec-segin.dtsi | 16 ++++++++++++++++
2 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
index c6ef13685a7c..32d90c67a6f2 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
@@ -28,9 +28,6 @@
};
&ecspi3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi3>;
- cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
status = "okay";
};
@@ -93,14 +90,3 @@
&usdhc1 {
status = "okay";
};
-
-&iomuxc {
- pinctrl_ecspi3: ecspi3grp {
- fsl,pins = <
- MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0
- MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
- MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
- MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0
- >;
- };
-};
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
index 7cd24ec40c36..8d5f8dc6ad58 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
@@ -103,6 +103,13 @@
assigned-clock-rates = <786432000>;
};
+&ecspi3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3>;
+ cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+};
+
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
@@ -225,6 +232,15 @@
>;
};
+ pinctrl_ecspi3: ecspi3grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0
+ MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
+ MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
+ MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0
+ >;
+ };
+
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 09/10] ARM: dts: imx6ul: segin: Move machine include to dts files
2019-07-09 7:19 ` Stefan Riedmueller
(?)
@ 2019-07-09 7:19 ` Stefan Riedmueller
-1 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, linux-kernel, linux-arm-kernel, martyn.welch, kernel,
festevam, linux-imx
Move the imx6ul.dtsi include to the dts files so it is easier to reuse
the SOM dtsi for e.g. an i.MX 6ULL SOM.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 1 -
arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
index 09a313daedb8..92bf91674056 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
@@ -7,7 +7,6 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pwm/pwm.h>
-#include "imx6ul.dtsi"
/ {
model = "PHYTEC phyCORE-i.MX6 UltraLite";
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
index 32d90c67a6f2..699dfcbf9a60 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
@@ -5,6 +5,7 @@
*/
/dts-v1/;
+#include "imx6ul.dtsi"
#include "imx6ul-phytec-phycore-som.dtsi"
#include "imx6ul-phytec-segin.dtsi"
#include "imx6ul-phytec-segin-peb-eval-01.dtsi"
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 09/10] ARM: dts: imx6ul: segin: Move machine include to dts files
@ 2019-07-09 7:19 ` Stefan Riedmueller
0 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, martyn.welch, linux-kernel, linux-imx, kernel,
festevam, linux-arm-kernel
Move the imx6ul.dtsi include to the dts files so it is easier to reuse
the SOM dtsi for e.g. an i.MX 6ULL SOM.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 1 -
arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
index 09a313daedb8..92bf91674056 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
@@ -7,7 +7,6 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pwm/pwm.h>
-#include "imx6ul.dtsi"
/ {
model = "PHYTEC phyCORE-i.MX6 UltraLite";
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
index 32d90c67a6f2..699dfcbf9a60 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
@@ -5,6 +5,7 @@
*/
/dts-v1/;
+#include "imx6ul.dtsi"
#include "imx6ul-phytec-phycore-som.dtsi"
#include "imx6ul-phytec-segin.dtsi"
#include "imx6ul-phytec-segin-peb-eval-01.dtsi"
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 09/10] ARM: dts: imx6ul: segin: Move machine include to dts files
@ 2019-07-09 7:19 ` Stefan Riedmueller
0 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, martyn.welch, linux-kernel, linux-imx, kernel,
festevam, linux-arm-kernel
Move the imx6ul.dtsi include to the dts files so it is easier to reuse
the SOM dtsi for e.g. an i.MX 6ULL SOM.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 1 -
arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
index 09a313daedb8..92bf91674056 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
@@ -7,7 +7,6 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pwm/pwm.h>
-#include "imx6ul.dtsi"
/ {
model = "PHYTEC phyCORE-i.MX6 UltraLite";
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
index 32d90c67a6f2..699dfcbf9a60 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
@@ -5,6 +5,7 @@
*/
/dts-v1/;
+#include "imx6ul.dtsi"
#include "imx6ul-phytec-phycore-som.dtsi"
#include "imx6ul-phytec-segin.dtsi"
#include "imx6ul-phytec-segin-peb-eval-01.dtsi"
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 10/10] ARM: dts: imx6ull: Add support for PHYTEC phyBOARD-Segin with i.MX 6ULL
2019-07-09 7:19 ` Stefan Riedmueller
(?)
@ 2019-07-09 7:19 ` Stefan Riedmueller
-1 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, linux-kernel, linux-arm-kernel, martyn.welch, kernel,
festevam, linux-imx
In addition to the PHYTEC phyCORE-i.MX 6UL the PHYTEC phyBOARD-Segin is
also available with the PHYTEC phyCORE-i.MX 6ULL. So this adds support
for this SOM and its baseboards.
It comes in a full featured option with either NAND flash or eMMC and in
a low cost option only available with NAND flash.
The hardware specs are:
- Full featured with NAND or eMMC:
* i.MX 6ULL Y2
* 512MB DDR3 memory
* 512MB NAND flash or 4GB/8GB eMMC
* Dual 10/100 Ethernet
* USB Host and USB OTG
* RS232
* MicroSD external storage
* Audio, RS232, I2C, SPI, CAN headers
* Further I/O options via A/V and Expansion headers
- Low cost with NAND:
* i.MX 6ULL Y0
* 256MB DDR3 memory
* 128MB NAND flash
* Single 10/100 Ethernet
* USB OTG
* RS232
* MicroSD external storage
* I2C
* Further I/O options via Expansion headers
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/Makefile | 3 +
arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi | 24 ++++++
.../boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts | 93 ++++++++++++++++++++++
.../boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts | 93 ++++++++++++++++++++++
.../boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts | 45 +++++++++++
.../boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi | 19 +++++
arch/arm/boot/dts/imx6ull-phytec-segin.dtsi | 38 +++++++++
7 files changed, 315 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 668b57c8cc57..16efd11cf20f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -580,6 +580,9 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ull-14x14-evk.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-colibri-wifi-eval-v3.dtb \
+ imx6ull-phytec-segin-ff-rdk-nand.dtb \
+ imx6ull-phytec-segin-ff-rdk-emmc.dtb \
+ imx6ull-phytec-segin-lc-rdk-nand.dtb \
imx6ulz-14x14-evk.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-cl-som-imx7.dtb \
diff --git a/arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi
new file mode 100644
index 000000000000..56cd16e5a77f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
+ */
+
+#include "imx6ul-phytec-phycore-som.dtsi"
+
+/ {
+ model = "PHYTEC phyCORE-i.MX6 ULL";
+ compatible = "phytec,imx6ull-pcl063", "fsl,imx6ull";
+};
+
+&iomuxc {
+ /delete-node/ gpioledssomgrp;
+};
+
+&iomuxc_snvs {
+ pinctrl_gpioleds_som: gpioledssomgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts
new file mode 100644
index 000000000000..9648d4ecaf58
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6ull.dtsi"
+#include "imx6ull-phytec-phycore-som.dtsi"
+#include "imx6ull-phytec-segin.dtsi"
+#include "imx6ull-phytec-segin-peb-eval-01.dtsi"
+
+/ {
+ model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with eMMC";
+ compatible = "phytec,imx6ull-pbacd10-emmc", "phytec,imx6ull-pbacd10",
+ "phytec,imx6ull-pcl063","fsl,imx6ull";
+};
+
+&adc1 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&tlv320 {
+ status = "okay";
+};
+
+&ecspi3 {
+ status = "okay";
+};
+
+ðphy1 {
+ status = "okay";
+};
+
+ðphy2 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&fec2 {
+ status = "okay";
+};
+
+&i2c_rtc {
+ status = "okay";
+};
+
+®_can1_en {
+ status = "okay";
+};
+
+®_sound_1v8 {
+ status = "okay";
+};
+
+®_sound_3v3 {
+ status = "okay";
+};
+
+&sai2 {
+ status = "okay";
+};
+
+&sound {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbotg1 {
+ status = "okay";
+};
+
+&usbotg2 {
+ status = "okay";
+};
+
+&usdhc1 {
+ status = "okay";
+};
+
+&usdhc2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
new file mode 100644
index 000000000000..656baf846453
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6ull.dtsi"
+#include "imx6ull-phytec-phycore-som.dtsi"
+#include "imx6ull-phytec-segin.dtsi"
+#include "imx6ull-phytec-segin-peb-eval-01.dtsi"
+
+/ {
+ model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with NAND";
+ compatible = "phytec,imx6ull-pbacd10-nand", "phytec,imx6ull-pbacd10",
+ "phytec,imx6ull-pcl063", "fsl,imx6ull";
+};
+
+&adc1 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&tlv320 {
+ status = "okay";
+};
+
+&ecspi3 {
+ status = "okay";
+};
+
+ðphy1 {
+ status = "okay";
+};
+
+ðphy2 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&fec2 {
+ status = "okay";
+};
+
+&gpmi {
+ status = "okay";
+};
+
+&i2c_rtc {
+ status = "okay";
+};
+
+®_can1_en {
+ status = "okay";
+};
+
+®_sound_1v8 {
+ status = "okay";
+};
+
+®_sound_3v3 {
+ status = "okay";
+};
+
+&sai2 {
+ status = "okay";
+};
+
+&sound {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbotg1 {
+ status = "okay";
+};
+
+&usbotg2 {
+ status = "okay";
+};
+
+&usdhc1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts
new file mode 100644
index 000000000000..e168494e0a6d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6ull.dtsi"
+#include "imx6ull-phytec-phycore-som.dtsi"
+#include "imx6ull-phytec-segin.dtsi"
+#include "imx6ull-phytec-segin-peb-eval-01.dtsi"
+
+/ {
+ model = "PHYTEC phyBOARD-Segin i.MX6 ULL Low Cost with NAND";
+ compatible = "phytec,imx6ull-pbacd10-nand", "phytec,imx6ull-pbacd10",
+ "phytec,imx6ull-pcl063", "fsl,imx6ull";
+};
+
+&adc1 {
+ status = "okay";
+};
+
+ðphy1 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&gpmi {
+ status = "okay";
+};
+
+&i2c_rtc {
+ status = "okay";
+};
+
+&usbotg1 {
+ status = "okay";
+};
+
+&usdhc1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi
new file mode 100644
index 000000000000..ff08d95a1aa2
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
+ */
+
+#include "imx6ul-phytec-segin-peb-eval-01.dtsi"
+
+&iomuxc {
+ /delete-node/ gpio_keysgrp;
+};
+
+&iomuxc_snvs {
+ pinctrl_gpio_keys: gpio_keysgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x79
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi
new file mode 100644
index 000000000000..c1595fc785f7
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
+ */
+
+#include "imx6ul-phytec-segin.dtsi"
+
+/ {
+ model = "PHYTEC phyBOARD-Segin i.MX6 ULL";
+ compatible = "phytec,imx6ull-pbacd-10", "phytec,imx6ull-pcl063","fsl,imx6ull";
+};
+
+&iomuxc {
+ /delete-node/ flexcan1engrp;
+ /delete-node/ rtcintgrp;
+ /delete-node/ stmpegrp;
+};
+
+&iomuxc_snvs {
+ princtrl_flexcan1_en: flexcan1engrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059
+ >;
+ };
+
+ pinctrl_rtc_int: rtcintgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059
+ >;
+ };
+
+ pinctrl_stmpe: stmpegrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059
+ >;
+ };
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 10/10] ARM: dts: imx6ull: Add support for PHYTEC phyBOARD-Segin with i.MX 6ULL
@ 2019-07-09 7:19 ` Stefan Riedmueller
0 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, martyn.welch, linux-kernel, linux-imx, kernel,
festevam, linux-arm-kernel
In addition to the PHYTEC phyCORE-i.MX 6UL the PHYTEC phyBOARD-Segin is
also available with the PHYTEC phyCORE-i.MX 6ULL. So this adds support
for this SOM and its baseboards.
It comes in a full featured option with either NAND flash or eMMC and in
a low cost option only available with NAND flash.
The hardware specs are:
- Full featured with NAND or eMMC:
* i.MX 6ULL Y2
* 512MB DDR3 memory
* 512MB NAND flash or 4GB/8GB eMMC
* Dual 10/100 Ethernet
* USB Host and USB OTG
* RS232
* MicroSD external storage
* Audio, RS232, I2C, SPI, CAN headers
* Further I/O options via A/V and Expansion headers
- Low cost with NAND:
* i.MX 6ULL Y0
* 256MB DDR3 memory
* 128MB NAND flash
* Single 10/100 Ethernet
* USB OTG
* RS232
* MicroSD external storage
* I2C
* Further I/O options via Expansion headers
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/Makefile | 3 +
arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi | 24 ++++++
.../boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts | 93 ++++++++++++++++++++++
.../boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts | 93 ++++++++++++++++++++++
.../boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts | 45 +++++++++++
.../boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi | 19 +++++
arch/arm/boot/dts/imx6ull-phytec-segin.dtsi | 38 +++++++++
7 files changed, 315 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 668b57c8cc57..16efd11cf20f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -580,6 +580,9 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ull-14x14-evk.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-colibri-wifi-eval-v3.dtb \
+ imx6ull-phytec-segin-ff-rdk-nand.dtb \
+ imx6ull-phytec-segin-ff-rdk-emmc.dtb \
+ imx6ull-phytec-segin-lc-rdk-nand.dtb \
imx6ulz-14x14-evk.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-cl-som-imx7.dtb \
diff --git a/arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi
new file mode 100644
index 000000000000..56cd16e5a77f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
+ */
+
+#include "imx6ul-phytec-phycore-som.dtsi"
+
+/ {
+ model = "PHYTEC phyCORE-i.MX6 ULL";
+ compatible = "phytec,imx6ull-pcl063", "fsl,imx6ull";
+};
+
+&iomuxc {
+ /delete-node/ gpioledssomgrp;
+};
+
+&iomuxc_snvs {
+ pinctrl_gpioleds_som: gpioledssomgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts
new file mode 100644
index 000000000000..9648d4ecaf58
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6ull.dtsi"
+#include "imx6ull-phytec-phycore-som.dtsi"
+#include "imx6ull-phytec-segin.dtsi"
+#include "imx6ull-phytec-segin-peb-eval-01.dtsi"
+
+/ {
+ model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with eMMC";
+ compatible = "phytec,imx6ull-pbacd10-emmc", "phytec,imx6ull-pbacd10",
+ "phytec,imx6ull-pcl063","fsl,imx6ull";
+};
+
+&adc1 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&tlv320 {
+ status = "okay";
+};
+
+&ecspi3 {
+ status = "okay";
+};
+
+ðphy1 {
+ status = "okay";
+};
+
+ðphy2 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&fec2 {
+ status = "okay";
+};
+
+&i2c_rtc {
+ status = "okay";
+};
+
+®_can1_en {
+ status = "okay";
+};
+
+®_sound_1v8 {
+ status = "okay";
+};
+
+®_sound_3v3 {
+ status = "okay";
+};
+
+&sai2 {
+ status = "okay";
+};
+
+&sound {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbotg1 {
+ status = "okay";
+};
+
+&usbotg2 {
+ status = "okay";
+};
+
+&usdhc1 {
+ status = "okay";
+};
+
+&usdhc2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
new file mode 100644
index 000000000000..656baf846453
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6ull.dtsi"
+#include "imx6ull-phytec-phycore-som.dtsi"
+#include "imx6ull-phytec-segin.dtsi"
+#include "imx6ull-phytec-segin-peb-eval-01.dtsi"
+
+/ {
+ model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with NAND";
+ compatible = "phytec,imx6ull-pbacd10-nand", "phytec,imx6ull-pbacd10",
+ "phytec,imx6ull-pcl063", "fsl,imx6ull";
+};
+
+&adc1 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&tlv320 {
+ status = "okay";
+};
+
+&ecspi3 {
+ status = "okay";
+};
+
+ðphy1 {
+ status = "okay";
+};
+
+ðphy2 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&fec2 {
+ status = "okay";
+};
+
+&gpmi {
+ status = "okay";
+};
+
+&i2c_rtc {
+ status = "okay";
+};
+
+®_can1_en {
+ status = "okay";
+};
+
+®_sound_1v8 {
+ status = "okay";
+};
+
+®_sound_3v3 {
+ status = "okay";
+};
+
+&sai2 {
+ status = "okay";
+};
+
+&sound {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbotg1 {
+ status = "okay";
+};
+
+&usbotg2 {
+ status = "okay";
+};
+
+&usdhc1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts
new file mode 100644
index 000000000000..e168494e0a6d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6ull.dtsi"
+#include "imx6ull-phytec-phycore-som.dtsi"
+#include "imx6ull-phytec-segin.dtsi"
+#include "imx6ull-phytec-segin-peb-eval-01.dtsi"
+
+/ {
+ model = "PHYTEC phyBOARD-Segin i.MX6 ULL Low Cost with NAND";
+ compatible = "phytec,imx6ull-pbacd10-nand", "phytec,imx6ull-pbacd10",
+ "phytec,imx6ull-pcl063", "fsl,imx6ull";
+};
+
+&adc1 {
+ status = "okay";
+};
+
+ðphy1 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&gpmi {
+ status = "okay";
+};
+
+&i2c_rtc {
+ status = "okay";
+};
+
+&usbotg1 {
+ status = "okay";
+};
+
+&usdhc1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi
new file mode 100644
index 000000000000..ff08d95a1aa2
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
+ */
+
+#include "imx6ul-phytec-segin-peb-eval-01.dtsi"
+
+&iomuxc {
+ /delete-node/ gpio_keysgrp;
+};
+
+&iomuxc_snvs {
+ pinctrl_gpio_keys: gpio_keysgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x79
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi
new file mode 100644
index 000000000000..c1595fc785f7
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
+ */
+
+#include "imx6ul-phytec-segin.dtsi"
+
+/ {
+ model = "PHYTEC phyBOARD-Segin i.MX6 ULL";
+ compatible = "phytec,imx6ull-pbacd-10", "phytec,imx6ull-pcl063","fsl,imx6ull";
+};
+
+&iomuxc {
+ /delete-node/ flexcan1engrp;
+ /delete-node/ rtcintgrp;
+ /delete-node/ stmpegrp;
+};
+
+&iomuxc_snvs {
+ princtrl_flexcan1_en: flexcan1engrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059
+ >;
+ };
+
+ pinctrl_rtc_int: rtcintgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059
+ >;
+ };
+
+ pinctrl_stmpe: stmpegrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059
+ >;
+ };
+};
--
2.7.4
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^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 10/10] ARM: dts: imx6ull: Add support for PHYTEC phyBOARD-Segin with i.MX 6ULL
@ 2019-07-09 7:19 ` Stefan Riedmueller
0 siblings, 0 replies; 37+ messages in thread
From: Stefan Riedmueller @ 2019-07-09 7:19 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, mark.rutland
Cc: devicetree, martyn.welch, linux-kernel, linux-imx, kernel,
festevam, linux-arm-kernel
In addition to the PHYTEC phyCORE-i.MX 6UL the PHYTEC phyBOARD-Segin is
also available with the PHYTEC phyCORE-i.MX 6ULL. So this adds support
for this SOM and its baseboards.
It comes in a full featured option with either NAND flash or eMMC and in
a low cost option only available with NAND flash.
The hardware specs are:
- Full featured with NAND or eMMC:
* i.MX 6ULL Y2
* 512MB DDR3 memory
* 512MB NAND flash or 4GB/8GB eMMC
* Dual 10/100 Ethernet
* USB Host and USB OTG
* RS232
* MicroSD external storage
* Audio, RS232, I2C, SPI, CAN headers
* Further I/O options via A/V and Expansion headers
- Low cost with NAND:
* i.MX 6ULL Y0
* 256MB DDR3 memory
* 128MB NAND flash
* Single 10/100 Ethernet
* USB OTG
* RS232
* MicroSD external storage
* I2C
* Further I/O options via Expansion headers
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boot/dts/Makefile | 3 +
arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi | 24 ++++++
.../boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts | 93 ++++++++++++++++++++++
.../boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts | 93 ++++++++++++++++++++++
.../boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts | 45 +++++++++++
.../boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi | 19 +++++
arch/arm/boot/dts/imx6ull-phytec-segin.dtsi | 38 +++++++++
7 files changed, 315 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 668b57c8cc57..16efd11cf20f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -580,6 +580,9 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ull-14x14-evk.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-colibri-wifi-eval-v3.dtb \
+ imx6ull-phytec-segin-ff-rdk-nand.dtb \
+ imx6ull-phytec-segin-ff-rdk-emmc.dtb \
+ imx6ull-phytec-segin-lc-rdk-nand.dtb \
imx6ulz-14x14-evk.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-cl-som-imx7.dtb \
diff --git a/arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi
new file mode 100644
index 000000000000..56cd16e5a77f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
+ */
+
+#include "imx6ul-phytec-phycore-som.dtsi"
+
+/ {
+ model = "PHYTEC phyCORE-i.MX6 ULL";
+ compatible = "phytec,imx6ull-pcl063", "fsl,imx6ull";
+};
+
+&iomuxc {
+ /delete-node/ gpioledssomgrp;
+};
+
+&iomuxc_snvs {
+ pinctrl_gpioleds_som: gpioledssomgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts
new file mode 100644
index 000000000000..9648d4ecaf58
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6ull.dtsi"
+#include "imx6ull-phytec-phycore-som.dtsi"
+#include "imx6ull-phytec-segin.dtsi"
+#include "imx6ull-phytec-segin-peb-eval-01.dtsi"
+
+/ {
+ model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with eMMC";
+ compatible = "phytec,imx6ull-pbacd10-emmc", "phytec,imx6ull-pbacd10",
+ "phytec,imx6ull-pcl063","fsl,imx6ull";
+};
+
+&adc1 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&tlv320 {
+ status = "okay";
+};
+
+&ecspi3 {
+ status = "okay";
+};
+
+ðphy1 {
+ status = "okay";
+};
+
+ðphy2 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&fec2 {
+ status = "okay";
+};
+
+&i2c_rtc {
+ status = "okay";
+};
+
+®_can1_en {
+ status = "okay";
+};
+
+®_sound_1v8 {
+ status = "okay";
+};
+
+®_sound_3v3 {
+ status = "okay";
+};
+
+&sai2 {
+ status = "okay";
+};
+
+&sound {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbotg1 {
+ status = "okay";
+};
+
+&usbotg2 {
+ status = "okay";
+};
+
+&usdhc1 {
+ status = "okay";
+};
+
+&usdhc2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
new file mode 100644
index 000000000000..656baf846453
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6ull.dtsi"
+#include "imx6ull-phytec-phycore-som.dtsi"
+#include "imx6ull-phytec-segin.dtsi"
+#include "imx6ull-phytec-segin-peb-eval-01.dtsi"
+
+/ {
+ model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with NAND";
+ compatible = "phytec,imx6ull-pbacd10-nand", "phytec,imx6ull-pbacd10",
+ "phytec,imx6ull-pcl063", "fsl,imx6ull";
+};
+
+&adc1 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&tlv320 {
+ status = "okay";
+};
+
+&ecspi3 {
+ status = "okay";
+};
+
+ðphy1 {
+ status = "okay";
+};
+
+ðphy2 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&fec2 {
+ status = "okay";
+};
+
+&gpmi {
+ status = "okay";
+};
+
+&i2c_rtc {
+ status = "okay";
+};
+
+®_can1_en {
+ status = "okay";
+};
+
+®_sound_1v8 {
+ status = "okay";
+};
+
+®_sound_3v3 {
+ status = "okay";
+};
+
+&sai2 {
+ status = "okay";
+};
+
+&sound {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbotg1 {
+ status = "okay";
+};
+
+&usbotg2 {
+ status = "okay";
+};
+
+&usdhc1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts
new file mode 100644
index 000000000000..e168494e0a6d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6ull.dtsi"
+#include "imx6ull-phytec-phycore-som.dtsi"
+#include "imx6ull-phytec-segin.dtsi"
+#include "imx6ull-phytec-segin-peb-eval-01.dtsi"
+
+/ {
+ model = "PHYTEC phyBOARD-Segin i.MX6 ULL Low Cost with NAND";
+ compatible = "phytec,imx6ull-pbacd10-nand", "phytec,imx6ull-pbacd10",
+ "phytec,imx6ull-pcl063", "fsl,imx6ull";
+};
+
+&adc1 {
+ status = "okay";
+};
+
+ðphy1 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&gpmi {
+ status = "okay";
+};
+
+&i2c_rtc {
+ status = "okay";
+};
+
+&usbotg1 {
+ status = "okay";
+};
+
+&usdhc1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi
new file mode 100644
index 000000000000..ff08d95a1aa2
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
+ */
+
+#include "imx6ul-phytec-segin-peb-eval-01.dtsi"
+
+&iomuxc {
+ /delete-node/ gpio_keysgrp;
+};
+
+&iomuxc_snvs {
+ pinctrl_gpio_keys: gpio_keysgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x79
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi
new file mode 100644
index 000000000000..c1595fc785f7
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
+ */
+
+#include "imx6ul-phytec-segin.dtsi"
+
+/ {
+ model = "PHYTEC phyBOARD-Segin i.MX6 ULL";
+ compatible = "phytec,imx6ull-pbacd-10", "phytec,imx6ull-pcl063","fsl,imx6ull";
+};
+
+&iomuxc {
+ /delete-node/ flexcan1engrp;
+ /delete-node/ rtcintgrp;
+ /delete-node/ stmpegrp;
+};
+
+&iomuxc_snvs {
+ princtrl_flexcan1_en: flexcan1engrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059
+ >;
+ };
+
+ pinctrl_rtc_int: rtcintgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059
+ >;
+ };
+
+ pinctrl_stmpe: stmpegrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059
+ >;
+ };
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [PATCH 00/10] Add further support for PHYTEC phyBOARD-Segin
2019-07-09 7:19 ` Stefan Riedmueller
@ 2019-07-23 5:39 ` Shawn Guo
-1 siblings, 0 replies; 37+ messages in thread
From: Shawn Guo @ 2019-07-23 5:39 UTC (permalink / raw)
To: Stefan Riedmueller
Cc: s.hauer, robh+dt, mark.rutland, devicetree, martyn.welch,
linux-kernel, linux-imx, kernel, festevam, linux-arm-kernel
On Tue, Jul 09, 2019 at 09:19:17AM +0200, Stefan Riedmueller wrote:
> This patchstack adjusts the already existing naming for the PHYTEC
> phyBOARD-Segin to the PHYTEC naming scheme that is already used with the
> phyCORE-i.MX 6 and the phyBOARD-Mira.
>
> Furthermore it introduces some small fixes and adds support for the PHYTEC
> phyCORE-i.MX 6ULL which also comes with the phyBORAD-Segin. It comes in a
> full featured option with either NAND flash or eMMC and a low cost option
> only with NAND flash.
>
> Stefan Riedmueller (10):
> ARM: dts: imx6ul: phyboard-segin: Rename dts to PHYTEC name scheme
> ARM: dts: imx6ul: segin: Add boot media to dts filename
> ARM: dts: imx6ul: segin: Reduce eth drive strength
> ARM: dts: imx6ul: segin: Fix LED naming for phyCORE and PEB-EVAL-01
> ARM: dts: imx6ul: segin: Make FEC and ethphy configurable in dts
> ARM: dts: imx6ul: segin: Only enable NAND if it is populated
> ARM: dts: imx6ul: phycore: Add eMMC at usdhc2
> ARM: dts: imx6ul: segin: Move ECSPI interface to board include file
> ARM: dts: imx6ul: segin: Move machine include to dts files
> ARM: dts: imx6ull: Add support for PHYTEC phyBOARD-Segin with i.MX
> 6ULL
I applied the series, but please send a follow-up patch for those
undocumented board compatibles.
Shawn
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 00/10] Add further support for PHYTEC phyBOARD-Segin
@ 2019-07-23 5:39 ` Shawn Guo
0 siblings, 0 replies; 37+ messages in thread
From: Shawn Guo @ 2019-07-23 5:39 UTC (permalink / raw)
To: Stefan Riedmueller
Cc: mark.rutland, devicetree, martyn.welch, s.hauer, linux-kernel,
robh+dt, linux-imx, kernel, festevam, linux-arm-kernel
On Tue, Jul 09, 2019 at 09:19:17AM +0200, Stefan Riedmueller wrote:
> This patchstack adjusts the already existing naming for the PHYTEC
> phyBOARD-Segin to the PHYTEC naming scheme that is already used with the
> phyCORE-i.MX 6 and the phyBOARD-Mira.
>
> Furthermore it introduces some small fixes and adds support for the PHYTEC
> phyCORE-i.MX 6ULL which also comes with the phyBORAD-Segin. It comes in a
> full featured option with either NAND flash or eMMC and a low cost option
> only with NAND flash.
>
> Stefan Riedmueller (10):
> ARM: dts: imx6ul: phyboard-segin: Rename dts to PHYTEC name scheme
> ARM: dts: imx6ul: segin: Add boot media to dts filename
> ARM: dts: imx6ul: segin: Reduce eth drive strength
> ARM: dts: imx6ul: segin: Fix LED naming for phyCORE and PEB-EVAL-01
> ARM: dts: imx6ul: segin: Make FEC and ethphy configurable in dts
> ARM: dts: imx6ul: segin: Only enable NAND if it is populated
> ARM: dts: imx6ul: phycore: Add eMMC at usdhc2
> ARM: dts: imx6ul: segin: Move ECSPI interface to board include file
> ARM: dts: imx6ul: segin: Move machine include to dts files
> ARM: dts: imx6ull: Add support for PHYTEC phyBOARD-Segin with i.MX
> 6ULL
I applied the series, but please send a follow-up patch for those
undocumented board compatibles.
Shawn
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^ permalink raw reply [flat|nested] 37+ messages in thread