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From: <tony.nguyen@bt.com>
To: <qemu-devel@nongnu.org>
Cc: peter.maydell@linaro.org, walling@linux.ibm.com, mst@redhat.com,
	palmer@sifive.com, mark.cave-ayland@ilande.co.uk,
	Alistair.Francis@wdc.com, arikalo@wavecomp.com, david@redhat.com,
	pasic@linux.ibm.com, borntraeger@de.ibm.com, rth@twiddle.net,
	atar4qemu@gmail.com, ehabkost@redhat.com, sw@weilnetz.de,
	qemu-s390x@nongnu.org, qemu-arm@nongnu.org,
	david@gibson.dropbear.id.au, qemu-riscv@nongnu.org,
	cohuck@redhat.com, claudio.fontana@huawei.com,
	alex.williamson@redhat.com, qemu-ppc@nongnu.org,
	amarkovic@wavecomp.com, pbonzini@redhat.com,
	aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH v2 06/20] tcg: Rename get_memop to get_tcgmemop
Date: Mon, 22 Jul 2019 15:44:24 +0000	[thread overview]
Message-ID: <1563810264064.38406@bt.com> (raw)
In-Reply-To: <e9c6e5310b1a4863be45d45bf087fc3d@tpw09926dag18e.domain1.systemhost.net>

Correct naming as there is now both MemOp and TCGMemOp.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
 accel/tcg/cputlb.c           |  6 +++---
 tcg/aarch64/tcg-target.inc.c |  8 ++++----
 tcg/arm/tcg-target.inc.c     |  8 ++++----
 tcg/i386/tcg-target.inc.c    |  8 ++++----
 tcg/mips/tcg-target.inc.c    | 10 +++++-----
 tcg/optimize.c               |  2 +-
 tcg/ppc/tcg-target.inc.c     |  8 ++++----
 tcg/riscv/tcg-target.inc.c   | 10 +++++-----
 tcg/s390/tcg-target.inc.c    |  8 ++++----
 tcg/sparc/tcg-target.inc.c   |  4 ++--
 tcg/tcg.c                    |  2 +-
 tcg/tcg.h                    |  4 ++--
 tcg/tci.c                    |  8 ++++----
 13 files changed, 43 insertions(+), 43 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index bb9897b..184fc54 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1133,7 +1133,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
     uintptr_t index = tlb_index(env, mmu_idx, addr);
     CPUTLBEntry *tlbe = tlb_entry(env, mmu_idx, addr);
     target_ulong tlb_addr = tlb_addr_write(tlbe);
-    TCGMemOp mop = get_memop(oi);
+    TCGMemOp mop = get_tcgmemop(oi);
     int a_bits = get_alignment_bits(mop);
     int s_bits = mop & MO_SIZE;
     void *hostaddr;
@@ -1257,7 +1257,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
         offsetof(CPUTLBEntry, addr_code) : offsetof(CPUTLBEntry, addr_read);
     const MMUAccessType access_type =
         code_read ? MMU_INST_FETCH : MMU_DATA_LOAD;
-    unsigned a_bits = get_alignment_bits(get_memop(oi));
+    unsigned a_bits = get_alignment_bits(get_tcgmemop(oi));
     void *haddr;
     uint64_t res;

@@ -1506,7 +1506,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
     CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
     target_ulong tlb_addr = tlb_addr_write(entry);
     const size_t tlb_off = offsetof(CPUTLBEntry, addr_write);
-    unsigned a_bits = get_alignment_bits(get_memop(oi));
+    unsigned a_bits = get_alignment_bits(get_tcgmemop(oi));
     void *haddr;

     /* Handle CPU specific unaligned behaviour */
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index d14afa9..886da51 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -1580,7 +1580,7 @@ static inline void tcg_out_adr(TCGContext *s, TCGReg rd, void *target)
 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
 {
     TCGMemOpIdx oi = lb->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     TCGMemOp size = opc & MO_SIZE;

     if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) {
@@ -1605,7 +1605,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
 {
     TCGMemOpIdx oi = lb->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     TCGMemOp size = opc & MO_SIZE;

     if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) {
@@ -1804,7 +1804,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp memop,
 static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
                             TCGMemOpIdx oi, TCGType ext)
 {
-    TCGMemOp memop = get_memop(oi);
+    TCGMemOp memop = get_tcgmemop(oi);
     const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
 #ifdef CONFIG_SOFTMMU
     unsigned mem_index = get_mmuidx(oi);
@@ -1829,7 +1829,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
 static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
                             TCGMemOpIdx oi)
 {
-    TCGMemOp memop = get_memop(oi);
+    TCGMemOp memop = get_tcgmemop(oi);
     const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
 #ifdef CONFIG_SOFTMMU
     unsigned mem_index = get_mmuidx(oi);
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index 70eeb8a..98c5b47 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -1348,7 +1348,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
 {
     TCGReg argreg, datalo, datahi;
     TCGMemOpIdx oi = lb->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     void *func;

     if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) {
@@ -1412,7 +1412,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
 {
     TCGReg argreg, datalo, datahi;
     TCGMemOpIdx oi = lb->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);

     if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) {
         return false;
@@ -1589,7 +1589,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
     addrlo = *args++;
     addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0);
     oi = *args++;
-    opc = get_memop(oi);
+    opc = get_tcgmemop(oi);

 #ifdef CONFIG_SOFTMMU
     mem_index = get_mmuidx(oi);
@@ -1720,7 +1720,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
     addrlo = *args++;
     addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0);
     oi = *args++;
-    opc = get_memop(oi);
+    opc = get_tcgmemop(oi);

 #ifdef CONFIG_SOFTMMU
     mem_index = get_mmuidx(oi);
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 3a73334..e4525ca 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -1810,7 +1810,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64,
 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
 {
     TCGMemOpIdx oi = l->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     TCGReg data_reg;
     tcg_insn_unit **label_ptr = &l->label_ptr[0];
     int rexw = (l->type == TCG_TYPE_I64 ? P_REXW : 0);
@@ -1895,7 +1895,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
 {
     TCGMemOpIdx oi = l->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     TCGMemOp s_bits = opc & MO_SIZE;
     tcg_insn_unit **label_ptr = &l->label_ptr[0];
     TCGReg retaddr;
@@ -2114,7 +2114,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
     addrlo = *args++;
     addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0);
     oi = *args++;
-    opc = get_memop(oi);
+    opc = get_tcgmemop(oi);

 #if defined(CONFIG_SOFTMMU)
     mem_index = get_mmuidx(oi);
@@ -2232,7 +2232,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
     addrlo = *args++;
     addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0);
     oi = *args++;
-    opc = get_memop(oi);
+    opc = get_tcgmemop(oi);

 #if defined(CONFIG_SOFTMMU)
     mem_index = get_mmuidx(oi);
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index ef31fc8..010afd0 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -1215,7 +1215,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
                              TCGReg addrh, TCGMemOpIdx oi,
                              tcg_insn_unit *label_ptr[2], bool is_load)
 {
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     unsigned s_bits = opc & MO_SIZE;
     unsigned a_bits = get_alignment_bits(opc);
     int mem_index = get_mmuidx(oi);
@@ -1313,7 +1313,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
 {
     TCGMemOpIdx oi = l->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     TCGReg v0;
     int i;

@@ -1363,7 +1363,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
 {
     TCGMemOpIdx oi = l->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     TCGMemOp s_bits = opc & MO_SIZE;
     int i;

@@ -1532,7 +1532,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
     addr_regl = *args++;
     addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
     oi = *args++;
-    opc = get_memop(oi);
+    opc = get_tcgmemop(oi);

 #if defined(CONFIG_SOFTMMU)
     tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1);
@@ -1635,7 +1635,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
     addr_regl = *args++;
     addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
     oi = *args++;
-    opc = get_memop(oi);
+    opc = get_tcgmemop(oi);

 #if defined(CONFIG_SOFTMMU)
     tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0);
diff --git a/tcg/optimize.c b/tcg/optimize.c
index d2424de..422bcbb 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -1014,7 +1014,7 @@ void tcg_optimize(TCGContext *s)
         CASE_OP_32_64(qemu_ld):
             {
                 TCGMemOpIdx oi = op->args[nb_oargs + nb_iargs];
-                TCGMemOp mop = get_memop(oi);
+                TCGMemOp mop = get_tcgmemop(oi);
                 if (!(mop & MO_SIGN)) {
                     mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;
                 }
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 13a2437..0ab4faa 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -1633,7 +1633,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
 {
     TCGMemOpIdx oi = lb->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     TCGReg hi, lo, arg = TCG_REG_R3;

     if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) {
@@ -1680,7 +1680,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
 {
     TCGMemOpIdx oi = lb->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     TCGMemOp s_bits = opc & MO_SIZE;
     TCGReg hi, lo, arg = TCG_REG_R3;

@@ -1755,7 +1755,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
     addrlo = *args++;
     addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
     oi = *args++;
-    opc = get_memop(oi);
+    opc = get_tcgmemop(oi);
     s_bits = opc & MO_SIZE;

 #ifdef CONFIG_SOFTMMU
@@ -1830,7 +1830,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
     addrlo = *args++;
     addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
     oi = *args++;
-    opc = get_memop(oi);
+    opc = get_tcgmemop(oi);
     s_bits = opc & MO_SIZE;

 #ifdef CONFIG_SOFTMMU
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 90363df..ab4e035 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -970,7 +970,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
                              TCGReg addrh, TCGMemOpIdx oi,
                              tcg_insn_unit **label_ptr, bool is_load)
 {
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     unsigned s_bits = opc & MO_SIZE;
     unsigned a_bits = get_alignment_bits(opc);
     tcg_target_long compare_mask;
@@ -1044,7 +1044,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
 {
     TCGMemOpIdx oi = l->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     TCGReg a0 = tcg_target_call_iarg_regs[0];
     TCGReg a1 = tcg_target_call_iarg_regs[1];
     TCGReg a2 = tcg_target_call_iarg_regs[2];
@@ -1077,7 +1077,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
 {
     TCGMemOpIdx oi = l->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     TCGMemOp s_bits = opc & MO_SIZE;
     TCGReg a0 = tcg_target_call_iarg_regs[0];
     TCGReg a1 = tcg_target_call_iarg_regs[1];
@@ -1183,7 +1183,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
     addr_regl = *args++;
     addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
     oi = *args++;
-    opc = get_memop(oi);
+    opc = get_tcgmemop(oi);

 #if defined(CONFIG_SOFTMMU)
     tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1);
@@ -1254,7 +1254,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
     addr_regl = *args++;
     addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
     oi = *args++;
-    opc = get_memop(oi);
+    opc = get_tcgmemop(oi);

 #if defined(CONFIG_SOFTMMU)
     tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0);
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index db1102e..4d8078b 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -1614,7 +1614,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
     TCGReg addr_reg = lb->addrlo_reg;
     TCGReg data_reg = lb->datalo_reg;
     TCGMemOpIdx oi = lb->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);

     if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
                      (intptr_t)s->code_ptr, 2)) {
@@ -1639,7 +1639,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
     TCGReg addr_reg = lb->addrlo_reg;
     TCGReg data_reg = lb->datalo_reg;
     TCGMemOpIdx oi = lb->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);

     if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
                      (intptr_t)s->code_ptr, 2)) {
@@ -1694,7 +1694,7 @@ static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg,
 static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
                             TCGMemOpIdx oi)
 {
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
 #ifdef CONFIG_SOFTMMU
     unsigned mem_index = get_mmuidx(oi);
     tcg_insn_unit *label_ptr;
@@ -1721,7 +1721,7 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
 static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
                             TCGMemOpIdx oi)
 {
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
 #ifdef CONFIG_SOFTMMU
     unsigned mem_index = get_mmuidx(oi);
     tcg_insn_unit *label_ptr;
diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c
index 7c50118..e6cf2c4 100644
--- a/tcg/sparc/tcg-target.inc.c
+++ b/tcg/sparc/tcg-target.inc.c
@@ -1164,7 +1164,7 @@ static const int qemu_st_opc[16] = {
 static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
                             TCGMemOpIdx oi, bool is_64)
 {
-    TCGMemOp memop = get_memop(oi);
+    TCGMemOp memop = get_tcgmemop(oi);
 #ifdef CONFIG_SOFTMMU
     unsigned memi = get_mmuidx(oi);
     TCGReg addrz, param;
@@ -1246,7 +1246,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
 static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr,
                             TCGMemOpIdx oi)
 {
-    TCGMemOp memop = get_memop(oi);
+    TCGMemOp memop = get_tcgmemop(oi);
 #ifdef CONFIG_SOFTMMU
     unsigned memi = get_mmuidx(oi);
     TCGReg addrz, param;
diff --git a/tcg/tcg.c b/tcg/tcg.c
index be2c33c..492d7c6 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -2056,7 +2056,7 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs)
             case INDEX_op_qemu_st_i64:
                 {
                     TCGMemOpIdx oi = op->args[k++];
-                    TCGMemOp op = get_memop(oi);
+                    TCGMemOp op = get_tcgmemop(oi);
                     unsigned ix = get_mmuidx(oi);

                     if (op & ~(MO_AMASK | MO_BSWAP | MO_SSIZE)) {
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 18b91fe..8a3f912 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -1197,12 +1197,12 @@ static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx)
 }

 /**
- * get_memop
+ * get_tcgmemop
  * @oi: combined op/idx parameter
  *
  * Extract the memory operation from the combined value.
  */
-static inline TCGMemOp get_memop(TCGMemOpIdx oi)
+static inline TCGMemOp get_tcgmemop(TCGMemOpIdx oi)
 {
     return oi >> 4;
 }
diff --git a/tcg/tci.c b/tcg/tci.c
index 33edca1..b3c5795 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -1109,7 +1109,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
             t0 = *tb_ptr++;
             taddr = tci_read_ulong(regs, &tb_ptr);
             oi = tci_read_i(&tb_ptr);
-            switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
+            switch (get_tcgmemop(oi) & (MO_BSWAP | MO_SSIZE)) {
             case MO_UB:
                 tmp32 = qemu_ld_ub;
                 break;
@@ -1146,7 +1146,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
             }
             taddr = tci_read_ulong(regs, &tb_ptr);
             oi = tci_read_i(&tb_ptr);
-            switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
+            switch (get_tcgmemop(oi) & (MO_BSWAP | MO_SSIZE)) {
             case MO_UB:
                 tmp64 = qemu_ld_ub;
                 break;
@@ -1195,7 +1195,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
             t0 = tci_read_r(regs, &tb_ptr);
             taddr = tci_read_ulong(regs, &tb_ptr);
             oi = tci_read_i(&tb_ptr);
-            switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
+            switch (get_tcgmemop(oi) & (MO_BSWAP | MO_SIZE)) {
             case MO_UB:
                 qemu_st_b(t0);
                 break;
@@ -1219,7 +1219,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
             tmp64 = tci_read_r64(regs, &tb_ptr);
             taddr = tci_read_ulong(regs, &tb_ptr);
             oi = tci_read_i(&tb_ptr);
-            switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
+            switch (get_tcgmemop(oi) & (MO_BSWAP | MO_SIZE)) {
             case MO_UB:
                 qemu_st_b(tmp64);
                 break;
--
1.8.3.1




WARNING: multiple messages have this Message-ID (diff)
From: <tony.nguyen@bt.com>
To: <qemu-devel@nongnu.org>
Cc: <peter.maydell@linaro.org>, <walling@linux.ibm.com>,
	<david@redhat.com>, <palmer@sifive.com>,
	<mark.cave-ayland@ilande.co.uk>, <Alistair.Francis@wdc.com>,
	<arikalo@wavecomp.com>, <mst@redhat.com>, <pasic@linux.ibm.com>,
	<borntraeger@de.ibm.com>, <rth@twiddle.net>,
	<atar4qemu@gmail.com>, <ehabkost@redhat.com>, <sw@weilnetz.de>,
	<alex.williamson@redhat.com>, <qemu-arm@nongnu.org>,
	<david@gibson.dropbear.id.au>, <qemu-riscv@nongnu.org>,
	<cohuck@redhat.com>, <claudio.fontana@huawei.com>,
	<qemu-s390x@nongnu.org>, <qemu-ppc@nongnu.org>,
	 <amarkovic@wavecomp.com>, <pbonzini@redhat.com>,
	<aurelien@aurel32.net>
Subject: [Qemu-riscv] [Qemu-devel] [PATCH v2 06/20] tcg: Rename get_memop to get_tcgmemop
Date: Mon, 22 Jul 2019 15:44:24 +0000	[thread overview]
Message-ID: <1563810264064.38406@bt.com> (raw)
In-Reply-To: <e9c6e5310b1a4863be45d45bf087fc3d@tpw09926dag18e.domain1.systemhost.net>

[-- Attachment #1: Type: text/plain, Size: 18888 bytes --]

Correct naming as there is now both MemOp and TCGMemOp.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
 accel/tcg/cputlb.c           |  6 +++---
 tcg/aarch64/tcg-target.inc.c |  8 ++++----
 tcg/arm/tcg-target.inc.c     |  8 ++++----
 tcg/i386/tcg-target.inc.c    |  8 ++++----
 tcg/mips/tcg-target.inc.c    | 10 +++++-----
 tcg/optimize.c               |  2 +-
 tcg/ppc/tcg-target.inc.c     |  8 ++++----
 tcg/riscv/tcg-target.inc.c   | 10 +++++-----
 tcg/s390/tcg-target.inc.c    |  8 ++++----
 tcg/sparc/tcg-target.inc.c   |  4 ++--
 tcg/tcg.c                    |  2 +-
 tcg/tcg.h                    |  4 ++--
 tcg/tci.c                    |  8 ++++----
 13 files changed, 43 insertions(+), 43 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index bb9897b..184fc54 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1133,7 +1133,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
     uintptr_t index = tlb_index(env, mmu_idx, addr);
     CPUTLBEntry *tlbe = tlb_entry(env, mmu_idx, addr);
     target_ulong tlb_addr = tlb_addr_write(tlbe);
-    TCGMemOp mop = get_memop(oi);
+    TCGMemOp mop = get_tcgmemop(oi);
     int a_bits = get_alignment_bits(mop);
     int s_bits = mop & MO_SIZE;
     void *hostaddr;
@@ -1257,7 +1257,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
         offsetof(CPUTLBEntry, addr_code) : offsetof(CPUTLBEntry, addr_read);
     const MMUAccessType access_type =
         code_read ? MMU_INST_FETCH : MMU_DATA_LOAD;
-    unsigned a_bits = get_alignment_bits(get_memop(oi));
+    unsigned a_bits = get_alignment_bits(get_tcgmemop(oi));
     void *haddr;
     uint64_t res;

@@ -1506,7 +1506,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
     CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
     target_ulong tlb_addr = tlb_addr_write(entry);
     const size_t tlb_off = offsetof(CPUTLBEntry, addr_write);
-    unsigned a_bits = get_alignment_bits(get_memop(oi));
+    unsigned a_bits = get_alignment_bits(get_tcgmemop(oi));
     void *haddr;

     /* Handle CPU specific unaligned behaviour */
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index d14afa9..886da51 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -1580,7 +1580,7 @@ static inline void tcg_out_adr(TCGContext *s, TCGReg rd, void *target)
 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
 {
     TCGMemOpIdx oi = lb->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     TCGMemOp size = opc & MO_SIZE;

     if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) {
@@ -1605,7 +1605,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
 {
     TCGMemOpIdx oi = lb->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     TCGMemOp size = opc & MO_SIZE;

     if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) {
@@ -1804,7 +1804,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp memop,
 static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
                             TCGMemOpIdx oi, TCGType ext)
 {
-    TCGMemOp memop = get_memop(oi);
+    TCGMemOp memop = get_tcgmemop(oi);
     const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
 #ifdef CONFIG_SOFTMMU
     unsigned mem_index = get_mmuidx(oi);
@@ -1829,7 +1829,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
 static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
                             TCGMemOpIdx oi)
 {
-    TCGMemOp memop = get_memop(oi);
+    TCGMemOp memop = get_tcgmemop(oi);
     const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
 #ifdef CONFIG_SOFTMMU
     unsigned mem_index = get_mmuidx(oi);
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index 70eeb8a..98c5b47 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -1348,7 +1348,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
 {
     TCGReg argreg, datalo, datahi;
     TCGMemOpIdx oi = lb->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     void *func;

     if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) {
@@ -1412,7 +1412,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
 {
     TCGReg argreg, datalo, datahi;
     TCGMemOpIdx oi = lb->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);

     if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) {
         return false;
@@ -1589,7 +1589,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
     addrlo = *args++;
     addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0);
     oi = *args++;
-    opc = get_memop(oi);
+    opc = get_tcgmemop(oi);

 #ifdef CONFIG_SOFTMMU
     mem_index = get_mmuidx(oi);
@@ -1720,7 +1720,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
     addrlo = *args++;
     addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0);
     oi = *args++;
-    opc = get_memop(oi);
+    opc = get_tcgmemop(oi);

 #ifdef CONFIG_SOFTMMU
     mem_index = get_mmuidx(oi);
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 3a73334..e4525ca 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -1810,7 +1810,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64,
 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
 {
     TCGMemOpIdx oi = l->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     TCGReg data_reg;
     tcg_insn_unit **label_ptr = &l->label_ptr[0];
     int rexw = (l->type == TCG_TYPE_I64 ? P_REXW : 0);
@@ -1895,7 +1895,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
 {
     TCGMemOpIdx oi = l->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     TCGMemOp s_bits = opc & MO_SIZE;
     tcg_insn_unit **label_ptr = &l->label_ptr[0];
     TCGReg retaddr;
@@ -2114,7 +2114,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
     addrlo = *args++;
     addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0);
     oi = *args++;
-    opc = get_memop(oi);
+    opc = get_tcgmemop(oi);

 #if defined(CONFIG_SOFTMMU)
     mem_index = get_mmuidx(oi);
@@ -2232,7 +2232,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
     addrlo = *args++;
     addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0);
     oi = *args++;
-    opc = get_memop(oi);
+    opc = get_tcgmemop(oi);

 #if defined(CONFIG_SOFTMMU)
     mem_index = get_mmuidx(oi);
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index ef31fc8..010afd0 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -1215,7 +1215,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
                              TCGReg addrh, TCGMemOpIdx oi,
                              tcg_insn_unit *label_ptr[2], bool is_load)
 {
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     unsigned s_bits = opc & MO_SIZE;
     unsigned a_bits = get_alignment_bits(opc);
     int mem_index = get_mmuidx(oi);
@@ -1313,7 +1313,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
 {
     TCGMemOpIdx oi = l->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     TCGReg v0;
     int i;

@@ -1363,7 +1363,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
 {
     TCGMemOpIdx oi = l->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     TCGMemOp s_bits = opc & MO_SIZE;
     int i;

@@ -1532,7 +1532,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
     addr_regl = *args++;
     addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
     oi = *args++;
-    opc = get_memop(oi);
+    opc = get_tcgmemop(oi);

 #if defined(CONFIG_SOFTMMU)
     tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1);
@@ -1635,7 +1635,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
     addr_regl = *args++;
     addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
     oi = *args++;
-    opc = get_memop(oi);
+    opc = get_tcgmemop(oi);

 #if defined(CONFIG_SOFTMMU)
     tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0);
diff --git a/tcg/optimize.c b/tcg/optimize.c
index d2424de..422bcbb 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -1014,7 +1014,7 @@ void tcg_optimize(TCGContext *s)
         CASE_OP_32_64(qemu_ld):
             {
                 TCGMemOpIdx oi = op->args[nb_oargs + nb_iargs];
-                TCGMemOp mop = get_memop(oi);
+                TCGMemOp mop = get_tcgmemop(oi);
                 if (!(mop & MO_SIGN)) {
                     mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;
                 }
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 13a2437..0ab4faa 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -1633,7 +1633,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
 {
     TCGMemOpIdx oi = lb->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     TCGReg hi, lo, arg = TCG_REG_R3;

     if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) {
@@ -1680,7 +1680,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
 {
     TCGMemOpIdx oi = lb->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     TCGMemOp s_bits = opc & MO_SIZE;
     TCGReg hi, lo, arg = TCG_REG_R3;

@@ -1755,7 +1755,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
     addrlo = *args++;
     addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
     oi = *args++;
-    opc = get_memop(oi);
+    opc = get_tcgmemop(oi);
     s_bits = opc & MO_SIZE;

 #ifdef CONFIG_SOFTMMU
@@ -1830,7 +1830,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
     addrlo = *args++;
     addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
     oi = *args++;
-    opc = get_memop(oi);
+    opc = get_tcgmemop(oi);
     s_bits = opc & MO_SIZE;

 #ifdef CONFIG_SOFTMMU
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 90363df..ab4e035 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -970,7 +970,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
                              TCGReg addrh, TCGMemOpIdx oi,
                              tcg_insn_unit **label_ptr, bool is_load)
 {
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     unsigned s_bits = opc & MO_SIZE;
     unsigned a_bits = get_alignment_bits(opc);
     tcg_target_long compare_mask;
@@ -1044,7 +1044,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
 {
     TCGMemOpIdx oi = l->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     TCGReg a0 = tcg_target_call_iarg_regs[0];
     TCGReg a1 = tcg_target_call_iarg_regs[1];
     TCGReg a2 = tcg_target_call_iarg_regs[2];
@@ -1077,7 +1077,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
 {
     TCGMemOpIdx oi = l->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
     TCGMemOp s_bits = opc & MO_SIZE;
     TCGReg a0 = tcg_target_call_iarg_regs[0];
     TCGReg a1 = tcg_target_call_iarg_regs[1];
@@ -1183,7 +1183,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
     addr_regl = *args++;
     addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
     oi = *args++;
-    opc = get_memop(oi);
+    opc = get_tcgmemop(oi);

 #if defined(CONFIG_SOFTMMU)
     tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1);
@@ -1254,7 +1254,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
     addr_regl = *args++;
     addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
     oi = *args++;
-    opc = get_memop(oi);
+    opc = get_tcgmemop(oi);

 #if defined(CONFIG_SOFTMMU)
     tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0);
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index db1102e..4d8078b 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -1614,7 +1614,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
     TCGReg addr_reg = lb->addrlo_reg;
     TCGReg data_reg = lb->datalo_reg;
     TCGMemOpIdx oi = lb->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);

     if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
                      (intptr_t)s->code_ptr, 2)) {
@@ -1639,7 +1639,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
     TCGReg addr_reg = lb->addrlo_reg;
     TCGReg data_reg = lb->datalo_reg;
     TCGMemOpIdx oi = lb->oi;
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);

     if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
                      (intptr_t)s->code_ptr, 2)) {
@@ -1694,7 +1694,7 @@ static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg,
 static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
                             TCGMemOpIdx oi)
 {
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
 #ifdef CONFIG_SOFTMMU
     unsigned mem_index = get_mmuidx(oi);
     tcg_insn_unit *label_ptr;
@@ -1721,7 +1721,7 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
 static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
                             TCGMemOpIdx oi)
 {
-    TCGMemOp opc = get_memop(oi);
+    TCGMemOp opc = get_tcgmemop(oi);
 #ifdef CONFIG_SOFTMMU
     unsigned mem_index = get_mmuidx(oi);
     tcg_insn_unit *label_ptr;
diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c
index 7c50118..e6cf2c4 100644
--- a/tcg/sparc/tcg-target.inc.c
+++ b/tcg/sparc/tcg-target.inc.c
@@ -1164,7 +1164,7 @@ static const int qemu_st_opc[16] = {
 static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
                             TCGMemOpIdx oi, bool is_64)
 {
-    TCGMemOp memop = get_memop(oi);
+    TCGMemOp memop = get_tcgmemop(oi);
 #ifdef CONFIG_SOFTMMU
     unsigned memi = get_mmuidx(oi);
     TCGReg addrz, param;
@@ -1246,7 +1246,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
 static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr,
                             TCGMemOpIdx oi)
 {
-    TCGMemOp memop = get_memop(oi);
+    TCGMemOp memop = get_tcgmemop(oi);
 #ifdef CONFIG_SOFTMMU
     unsigned memi = get_mmuidx(oi);
     TCGReg addrz, param;
diff --git a/tcg/tcg.c b/tcg/tcg.c
index be2c33c..492d7c6 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -2056,7 +2056,7 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs)
             case INDEX_op_qemu_st_i64:
                 {
                     TCGMemOpIdx oi = op->args[k++];
-                    TCGMemOp op = get_memop(oi);
+                    TCGMemOp op = get_tcgmemop(oi);
                     unsigned ix = get_mmuidx(oi);

                     if (op & ~(MO_AMASK | MO_BSWAP | MO_SSIZE)) {
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 18b91fe..8a3f912 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -1197,12 +1197,12 @@ static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx)
 }

 /**
- * get_memop
+ * get_tcgmemop
  * @oi: combined op/idx parameter
  *
  * Extract the memory operation from the combined value.
  */
-static inline TCGMemOp get_memop(TCGMemOpIdx oi)
+static inline TCGMemOp get_tcgmemop(TCGMemOpIdx oi)
 {
     return oi >> 4;
 }
diff --git a/tcg/tci.c b/tcg/tci.c
index 33edca1..b3c5795 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -1109,7 +1109,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
             t0 = *tb_ptr++;
             taddr = tci_read_ulong(regs, &tb_ptr);
             oi = tci_read_i(&tb_ptr);
-            switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
+            switch (get_tcgmemop(oi) & (MO_BSWAP | MO_SSIZE)) {
             case MO_UB:
                 tmp32 = qemu_ld_ub;
                 break;
@@ -1146,7 +1146,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
             }
             taddr = tci_read_ulong(regs, &tb_ptr);
             oi = tci_read_i(&tb_ptr);
-            switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
+            switch (get_tcgmemop(oi) & (MO_BSWAP | MO_SSIZE)) {
             case MO_UB:
                 tmp64 = qemu_ld_ub;
                 break;
@@ -1195,7 +1195,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
             t0 = tci_read_r(regs, &tb_ptr);
             taddr = tci_read_ulong(regs, &tb_ptr);
             oi = tci_read_i(&tb_ptr);
-            switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
+            switch (get_tcgmemop(oi) & (MO_BSWAP | MO_SIZE)) {
             case MO_UB:
                 qemu_st_b(t0);
                 break;
@@ -1219,7 +1219,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
             tmp64 = tci_read_r64(regs, &tb_ptr);
             taddr = tci_read_ulong(regs, &tb_ptr);
             oi = tci_read_i(&tb_ptr);
-            switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
+            switch (get_tcgmemop(oi) & (MO_BSWAP | MO_SIZE)) {
             case MO_UB:
                 qemu_st_b(tmp64);
                 break;
--
1.8.3.1




[-- Attachment #2: Type: text/html, Size: 31873 bytes --]

  parent reply	other threads:[~2019-07-22 15:45 UTC|newest]

Thread overview: 120+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-22 15:34 [Qemu-devel] [PATCH v2 00/20] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
2019-07-22 15:34 ` [Qemu-riscv] " tony.nguyen
2019-07-22 15:38 ` [Qemu-devel] [PATCH v2 01/20] tcg: Replace MO_8 with MO_UB alias tony.nguyen
2019-07-22 15:38   ` [Qemu-riscv] " tony.nguyen
2019-07-23  8:04   ` [Qemu-devel] [qemu-s390x] " David Hildenbrand
2019-07-23  8:04     ` [Qemu-riscv] [qemu-s390x] [Qemu-devel] " David Hildenbrand
2019-07-22 15:39 ` [Qemu-devel] [PATCH v2 02/20] tcg: Replace MO_16 with MO_UW alias tony.nguyen
2019-07-22 15:39   ` [Qemu-riscv] " tony.nguyen
2019-07-22 15:40 ` tony.nguyen
2019-07-22 15:40   ` [Qemu-riscv] " tony.nguyen
2019-07-22 15:41 ` [Qemu-devel] [PATCH v2 03/20] tcg: Replace MO_32 with MO_UL alias tony.nguyen
2019-07-22 15:41   ` [Qemu-riscv] " tony.nguyen
2019-07-22 15:42 ` [Qemu-devel] [PATCH v2 04/20] tcg: Replace MO_64 with MO_UQ alias tony.nguyen
2019-07-22 15:42   ` [Qemu-riscv] " tony.nguyen
2019-07-22 15:43 ` [Qemu-devel] [PATCH v2 05/20] tcg: Move size+sign+endian from TCGMemOp to MemOp tony.nguyen
2019-07-22 15:43   ` [Qemu-riscv] " tony.nguyen
2019-07-22 15:44 ` tony.nguyen [this message]
2019-07-22 15:44   ` [Qemu-riscv] [Qemu-devel] [PATCH v2 06/20] tcg: Rename get_memop to get_tcgmemop tony.nguyen
2019-07-22 15:45 ` [Qemu-devel] [PATCH v2 07/20] memory: Access MemoryRegion with MemOp tony.nguyen
2019-07-22 15:45   ` [Qemu-riscv] " tony.nguyen
2019-07-22 15:45 ` [Qemu-devel] [PATCH v2 08/20] target/mips: " tony.nguyen
2019-07-22 15:45   ` [Qemu-riscv] " tony.nguyen
2019-07-22 15:46 ` [Qemu-devel] [PATCH v2 09/20] hw/s390x: " tony.nguyen
2019-07-22 15:46   ` [Qemu-riscv] " tony.nguyen
2019-07-22 15:47 ` [Qemu-devel] [PATCH v2 10/20] hw/intc/armv7m_nic: " tony.nguyen
2019-07-22 15:47   ` [Qemu-riscv] " tony.nguyen
2019-07-22 15:48 ` [Qemu-devel] [PATCH v2 11/20] hw/virtio: " tony.nguyen
2019-07-22 15:48   ` [Qemu-riscv] " tony.nguyen
2019-07-22 15:48 ` [Qemu-devel] [PATCH v2 12/20] hw/vfio: " tony.nguyen
2019-07-22 15:48   ` [Qemu-riscv] " tony.nguyen
2019-07-22 15:49 ` [Qemu-devel] [PATCH v2 13/20] exec: " tony.nguyen
2019-07-22 15:49   ` [Qemu-riscv] " tony.nguyen
2019-07-22 15:50 ` [Qemu-devel] [PATCH v2 14/20] cputlb: " tony.nguyen
2019-07-22 15:50   ` [Qemu-riscv] " tony.nguyen
2019-07-22 15:50 ` [Qemu-devel] [PATCH v2 15/20] memory: Access MemoryRegion with MemOp semantics tony.nguyen
2019-07-22 15:50   ` [Qemu-riscv] " tony.nguyen
2019-07-22 15:51 ` [Qemu-devel] [PATCH v2 16/20] memory: Single byte swap along the I/O path tony.nguyen
2019-07-22 15:51   ` [Qemu-riscv] " tony.nguyen
2019-07-22 15:51 ` [Qemu-devel] [PATCH v2 17/20] cpu: TLB_FLAGS_MASK bit to force memory slow path tony.nguyen
2019-07-22 15:51   ` [Qemu-riscv] " tony.nguyen
2019-07-25  7:01   ` [Qemu-devel] [PATCH v3 00/15] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
2019-07-25  7:01     ` [Qemu-riscv] " tony.nguyen
2019-07-25  7:03     ` [Qemu-devel] [PATCH v3 01/15] tcg: TCGMemOp is now accelerator independent MemOp tony.nguyen
2019-07-25  7:03       ` [Qemu-riscv] " tony.nguyen
2019-07-25  7:03     ` [Qemu-devel] [PATCH v3 02/15] memory: Access MemoryRegion with MemOp tony.nguyen
2019-07-25  7:03       ` [Qemu-riscv] " tony.nguyen
2019-07-25  7:05     ` [Qemu-devel] [PATCH v3 03/15] target/mips: " tony.nguyen
2019-07-25  7:05       ` [Qemu-riscv] " tony.nguyen
2019-07-25  7:06     ` [Qemu-devel] [PATCH v3 04/15] hw/s390x: " tony.nguyen
2019-07-25  7:06       ` [Qemu-riscv] " tony.nguyen
2019-07-25  7:06     ` [Qemu-devel] [PATCH v3 05/15] hw/intc/armv7m_nic: " tony.nguyen
2019-07-25  7:06       ` [Qemu-riscv] " tony.nguyen
2019-07-25  7:07     ` [Qemu-devel] [PATCH v3 06/15] hw/virtio: " tony.nguyen
2019-07-25  7:07       ` [Qemu-riscv] " tony.nguyen
2019-07-25  7:08     ` [Qemu-devel] [PATCH v3 07/15] hw/vfio: " tony.nguyen
2019-07-25  7:08       ` [Qemu-riscv] " tony.nguyen
2019-07-25  7:08     ` [Qemu-devel] [PATCH v3 08/15] exec: " tony.nguyen
2019-07-25  7:08       ` [Qemu-riscv] " tony.nguyen
2019-07-25  7:08     ` [Qemu-devel] [PATCH v3 09/15] cputlb: " tony.nguyen
2019-07-25  7:08       ` [Qemu-riscv] " tony.nguyen
2019-07-25  7:09     ` [Qemu-devel] [PATCH v3 10/15] memory: Access MemoryRegion with MemOp semantics tony.nguyen
2019-07-25  7:09       ` [Qemu-riscv] " tony.nguyen
2019-07-25  7:10     ` [Qemu-devel] [PATCH v3 11/15] memory: Single byte swap along the I/O path tony.nguyen
2019-07-25  7:10       ` [Qemu-riscv] " tony.nguyen
2019-07-25  7:10     ` [Qemu-devel] [PATCH v3 12/15] cpu: TLB_FLAGS_MASK bit to force memory slow path tony.nguyen
2019-07-25  7:10       ` [Qemu-riscv] " tony.nguyen
2019-07-25  7:11     ` [Qemu-devel] [PATCH v3 13/15] cputlb: Byte swap memory transaction attribute tony.nguyen
2019-07-25  7:11       ` [Qemu-riscv] " tony.nguyen
2019-07-25  7:11     ` [Qemu-devel] [PATCH v3 14/15] target/sparc: Add TLB entry with attributes tony.nguyen
2019-07-25  7:11       ` [Qemu-riscv] " tony.nguyen
2019-07-25  7:12     ` [Qemu-devel] [PATCH v3 15/15] target/sparc: sun4u Invert Endian TTE bit tony.nguyen
2019-07-25  7:12       ` [Qemu-riscv] " tony.nguyen
2019-07-25  7:25     ` [Qemu-devel] [PATCH v3 00/15] Invert Endian bit in SPARCv9 MMU TTE no-reply
2019-07-25  7:25       ` [Qemu-riscv] " no-reply
2019-07-25  7:58     ` [Qemu-devel] [PATCH v4 " tony.nguyen
2019-07-25  7:58       ` [Qemu-riscv] " tony.nguyen
2019-07-25  8:00       ` [Qemu-devel] [PATCH v4 01/15] tcg: TCGMemOp is now accelerator independent MemOp tony.nguyen
2019-07-25  8:00         ` [Qemu-riscv] " tony.nguyen
2019-07-25  8:00       ` [Qemu-devel] [PATCH v4 02/15] memory: Access MemoryRegion with MemOp tony.nguyen
2019-07-25  8:00         ` [Qemu-riscv] " tony.nguyen
2019-07-25  8:01       ` [Qemu-devel] [PATCH v4 03/15] target/mips: " tony.nguyen
2019-07-25  8:01         ` [Qemu-riscv] " tony.nguyen
2019-07-25  8:01       ` [Qemu-devel] [PATCH v4 04/15] hw/s390x: " tony.nguyen
2019-07-25  8:01         ` [Qemu-riscv] " tony.nguyen
2019-07-25  8:02       ` [Qemu-devel] [PATCH v4 05/15] hw/intc/armv7m_nic: " tony.nguyen
2019-07-25  8:02         ` [Qemu-riscv] " tony.nguyen
2019-07-25  8:02       ` [Qemu-devel] [PATCH v4 06/15] hw/virtio: " tony.nguyen
2019-07-25  8:02         ` [Qemu-riscv] " tony.nguyen
2019-07-25  8:03       ` [Qemu-devel] [PATCH v4 07/15] hw/vfio: " tony.nguyen
2019-07-25  8:03         ` [Qemu-riscv] " tony.nguyen
2019-07-25  8:03       ` [Qemu-devel] [PATCH v4 08/15] exec: " tony.nguyen
2019-07-25  8:03         ` [Qemu-riscv] " tony.nguyen
2019-07-25  8:04       ` [Qemu-devel] [PATCH v4 09/15] cputlb: " tony.nguyen
2019-07-25  8:04         ` [Qemu-riscv] " tony.nguyen
2019-07-25  8:04       ` [Qemu-devel] [PATCH v4 10/15] memory: Access MemoryRegion with MemOp semantics tony.nguyen
2019-07-25  8:04         ` [Qemu-riscv] " tony.nguyen
2019-07-25  8:04       ` [Qemu-devel] [PATCH v4 11/15] memory: Single byte swap along the I/O path tony.nguyen
2019-07-25  8:04         ` [Qemu-riscv] " tony.nguyen
2019-07-25  8:05       ` [Qemu-devel] [PATCH v4 12/15] cpu: TLB_FLAGS_MASK bit to force memory slow path tony.nguyen
2019-07-25  8:05         ` [Qemu-riscv] " tony.nguyen
2019-07-25  8:05       ` [Qemu-devel] [PATCH v4 13/15] cputlb: Byte swap memory transaction attribute tony.nguyen
2019-07-25  8:05         ` [Qemu-riscv] " tony.nguyen
2019-07-25  8:06       ` [Qemu-devel] [PATCH v4 14/15] target/sparc: Add TLB entry with attributes tony.nguyen
2019-07-25  8:06         ` [Qemu-riscv] " tony.nguyen
2019-07-25  8:06       ` [Qemu-devel] [PATCH v4 15/15] target/sparc: sun4u Invert Endian TTE bit tony.nguyen
2019-07-25  8:06         ` [Qemu-riscv] " tony.nguyen
2019-07-22 15:52 ` [Qemu-devel] [PATCH v2 18/20] cputlb: Byte swap memory transaction attribute tony.nguyen
2019-07-22 15:52   ` [Qemu-riscv] " tony.nguyen
2019-07-22 15:53 ` [Qemu-devel] [PATCH v2 19/20] target/sparc: Add TLB entry with attributes tony.nguyen
2019-07-22 15:53   ` [Qemu-riscv] " tony.nguyen
2019-07-22 15:54 ` [Qemu-devel] [PATCH v2 20/20] target/sparc: sun4u Invert Endian TTE bit tony.nguyen
2019-07-22 15:54   ` [Qemu-riscv] " tony.nguyen
2019-07-22 15:59 ` [Qemu-devel] [PATCH v2 00/20] Invert Endian bit in SPARCv9 MMU TTE Richard Henderson
2019-07-22 15:59   ` [Qemu-riscv] " Richard Henderson
2019-07-22 16:22   ` Paolo Bonzini
2019-07-22 16:22     ` [Qemu-riscv] " Paolo Bonzini
2019-07-22 16:28   ` tony.nguyen
2019-07-22 16:28     ` [Qemu-riscv] " tony.nguyen
2019-07-22 18:58     ` Richard Henderson
2019-07-22 18:58       ` [Qemu-riscv] " Richard Henderson

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