From: <tony.nguyen@bt.com> To: <qemu-devel@nongnu.org> Cc: peter.maydell@linaro.org, walling@linux.ibm.com, mst@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, Alistair.Francis@wdc.com, arikalo@wavecomp.com, david@redhat.com, pasic@linux.ibm.com, borntraeger@de.ibm.com, rth@twiddle.net, atar4qemu@gmail.com, ehabkost@redhat.com, sw@weilnetz.de, qemu-s390x@nongnu.org, qemu-arm@nongnu.org, david@gibson.dropbear.id.au, qemu-riscv@nongnu.org, cohuck@redhat.com, claudio.fontana@huawei.com, alex.williamson@redhat.com, qemu-ppc@nongnu.org, amarkovic@wavecomp.com, pbonzini@redhat.com, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v2 18/20] cputlb: Byte swap memory transaction attribute Date: Mon, 22 Jul 2019 15:52:35 +0000 [thread overview] Message-ID: <1563810755207.16357@bt.com> (raw) In-Reply-To: <e9c6e5310b1a4863be45d45bf087fc3d@tpw09926dag18e.domain1.systemhost.net> Notice new attribute, byte swap, and force the transaction through the memory slow path. Required by architectures that can invert endianness of memory transaction, e.g. SPARC64 has the Invert Endian TTE bit. Signed-off-by: Tony Nguyen <tony.nguyen@bt.com> --- accel/tcg/cputlb.c | 11 +++++++++++ include/exec/memattrs.h | 2 ++ 2 files changed, 13 insertions(+) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 6f5262c..619787b 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -738,6 +738,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, */ address |= TLB_RECHECK; } + if (attrs.byte_swap) { + address |= TLB_FORCE_SLOW; + } if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) { /* IO memory case */ @@ -891,6 +894,10 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, bool locked = false; MemTxResult r; + if (iotlbentry->attrs.byte_swap) { + op ^= MO_BSWAP; + } + section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); mr = section->mr; mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; @@ -933,6 +940,10 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, bool locked = false; MemTxResult r; + if (iotlbentry->attrs.byte_swap) { + op ^= MO_BSWAP; + } + section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); mr = section->mr; mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index d4a3477..a0644eb 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -37,6 +37,8 @@ typedef struct MemTxAttrs { unsigned int user:1; /* Requester ID (for MSI for example) */ unsigned int requester_id:16; + /* SPARC64: TTE invert endianness */ + unsigned int byte_swap:1; /* * The following are target-specific page-table bits. These are not * related to actual memory transactions at all. However, this structure -- 1.8.3.1
WARNING: multiple messages have this Message-ID (diff)
From: <tony.nguyen@bt.com> To: <qemu-devel@nongnu.org> Cc: <peter.maydell@linaro.org>, <walling@linux.ibm.com>, <david@redhat.com>, <palmer@sifive.com>, <mark.cave-ayland@ilande.co.uk>, <Alistair.Francis@wdc.com>, <arikalo@wavecomp.com>, <mst@redhat.com>, <pasic@linux.ibm.com>, <borntraeger@de.ibm.com>, <rth@twiddle.net>, <atar4qemu@gmail.com>, <ehabkost@redhat.com>, <sw@weilnetz.de>, <alex.williamson@redhat.com>, <qemu-arm@nongnu.org>, <david@gibson.dropbear.id.au>, <qemu-riscv@nongnu.org>, <cohuck@redhat.com>, <claudio.fontana@huawei.com>, <qemu-s390x@nongnu.org>, <qemu-ppc@nongnu.org>, <amarkovic@wavecomp.com>, <pbonzini@redhat.com>, <aurelien@aurel32.net> Subject: [Qemu-riscv] [Qemu-devel] [PATCH v2 18/20] cputlb: Byte swap memory transaction attribute Date: Mon, 22 Jul 2019 15:52:35 +0000 [thread overview] Message-ID: <1563810755207.16357@bt.com> (raw) In-Reply-To: <e9c6e5310b1a4863be45d45bf087fc3d@tpw09926dag18e.domain1.systemhost.net> [-- Attachment #1: Type: text/plain, Size: 2205 bytes --] Notice new attribute, byte swap, and force the transaction through the memory slow path. Required by architectures that can invert endianness of memory transaction, e.g. SPARC64 has the Invert Endian TTE bit. Signed-off-by: Tony Nguyen <tony.nguyen@bt.com> --- accel/tcg/cputlb.c | 11 +++++++++++ include/exec/memattrs.h | 2 ++ 2 files changed, 13 insertions(+) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 6f5262c..619787b 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -738,6 +738,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, */ address |= TLB_RECHECK; } + if (attrs.byte_swap) { + address |= TLB_FORCE_SLOW; + } if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) { /* IO memory case */ @@ -891,6 +894,10 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, bool locked = false; MemTxResult r; + if (iotlbentry->attrs.byte_swap) { + op ^= MO_BSWAP; + } + section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); mr = section->mr; mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; @@ -933,6 +940,10 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, bool locked = false; MemTxResult r; + if (iotlbentry->attrs.byte_swap) { + op ^= MO_BSWAP; + } + section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); mr = section->mr; mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index d4a3477..a0644eb 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -37,6 +37,8 @@ typedef struct MemTxAttrs { unsigned int user:1; /* Requester ID (for MSI for example) */ unsigned int requester_id:16; + /* SPARC64: TTE invert endianness */ + unsigned int byte_swap:1; /* * The following are target-specific page-table bits. These are not * related to actual memory transactions at all. However, this structure -- 1.8.3.1 [-- Attachment #2: Type: text/html, Size: 4277 bytes --]
next prev parent reply other threads:[~2019-07-22 15:52 UTC|newest] Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-07-22 15:34 [Qemu-devel] [PATCH v2 00/20] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen 2019-07-22 15:34 ` [Qemu-riscv] " tony.nguyen 2019-07-22 15:38 ` [Qemu-devel] [PATCH v2 01/20] tcg: Replace MO_8 with MO_UB alias tony.nguyen 2019-07-22 15:38 ` [Qemu-riscv] " tony.nguyen 2019-07-23 8:04 ` [Qemu-devel] [qemu-s390x] " David Hildenbrand 2019-07-23 8:04 ` [Qemu-riscv] [qemu-s390x] [Qemu-devel] " David Hildenbrand 2019-07-22 15:39 ` [Qemu-devel] [PATCH v2 02/20] tcg: Replace MO_16 with MO_UW alias tony.nguyen 2019-07-22 15:39 ` [Qemu-riscv] " tony.nguyen 2019-07-22 15:40 ` tony.nguyen 2019-07-22 15:40 ` [Qemu-riscv] " tony.nguyen 2019-07-22 15:41 ` [Qemu-devel] [PATCH v2 03/20] tcg: Replace MO_32 with MO_UL alias tony.nguyen 2019-07-22 15:41 ` [Qemu-riscv] " tony.nguyen 2019-07-22 15:42 ` [Qemu-devel] [PATCH v2 04/20] tcg: Replace MO_64 with MO_UQ alias tony.nguyen 2019-07-22 15:42 ` [Qemu-riscv] " tony.nguyen 2019-07-22 15:43 ` [Qemu-devel] [PATCH v2 05/20] tcg: Move size+sign+endian from TCGMemOp to MemOp tony.nguyen 2019-07-22 15:43 ` [Qemu-riscv] " tony.nguyen 2019-07-22 15:44 ` [Qemu-devel] [PATCH v2 06/20] tcg: Rename get_memop to get_tcgmemop tony.nguyen 2019-07-22 15:44 ` [Qemu-riscv] " tony.nguyen 2019-07-22 15:45 ` [Qemu-devel] [PATCH v2 07/20] memory: Access MemoryRegion with MemOp tony.nguyen 2019-07-22 15:45 ` [Qemu-riscv] " tony.nguyen 2019-07-22 15:45 ` [Qemu-devel] [PATCH v2 08/20] target/mips: " tony.nguyen 2019-07-22 15:45 ` [Qemu-riscv] " tony.nguyen 2019-07-22 15:46 ` [Qemu-devel] [PATCH v2 09/20] hw/s390x: " tony.nguyen 2019-07-22 15:46 ` [Qemu-riscv] " tony.nguyen 2019-07-22 15:47 ` [Qemu-devel] [PATCH v2 10/20] hw/intc/armv7m_nic: " tony.nguyen 2019-07-22 15:47 ` [Qemu-riscv] " tony.nguyen 2019-07-22 15:48 ` [Qemu-devel] [PATCH v2 11/20] hw/virtio: " tony.nguyen 2019-07-22 15:48 ` [Qemu-riscv] " tony.nguyen 2019-07-22 15:48 ` [Qemu-devel] [PATCH v2 12/20] hw/vfio: " tony.nguyen 2019-07-22 15:48 ` [Qemu-riscv] " tony.nguyen 2019-07-22 15:49 ` [Qemu-devel] [PATCH v2 13/20] exec: " tony.nguyen 2019-07-22 15:49 ` [Qemu-riscv] " tony.nguyen 2019-07-22 15:50 ` [Qemu-devel] [PATCH v2 14/20] cputlb: " tony.nguyen 2019-07-22 15:50 ` [Qemu-riscv] " tony.nguyen 2019-07-22 15:50 ` [Qemu-devel] [PATCH v2 15/20] memory: Access MemoryRegion with MemOp semantics tony.nguyen 2019-07-22 15:50 ` [Qemu-riscv] " tony.nguyen 2019-07-22 15:51 ` [Qemu-devel] [PATCH v2 16/20] memory: Single byte swap along the I/O path tony.nguyen 2019-07-22 15:51 ` [Qemu-riscv] " tony.nguyen 2019-07-22 15:51 ` [Qemu-devel] [PATCH v2 17/20] cpu: TLB_FLAGS_MASK bit to force memory slow path tony.nguyen 2019-07-22 15:51 ` [Qemu-riscv] " tony.nguyen 2019-07-25 7:01 ` [Qemu-devel] [PATCH v3 00/15] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen 2019-07-25 7:01 ` [Qemu-riscv] " tony.nguyen 2019-07-25 7:03 ` [Qemu-devel] [PATCH v3 01/15] tcg: TCGMemOp is now accelerator independent MemOp tony.nguyen 2019-07-25 7:03 ` [Qemu-riscv] " tony.nguyen 2019-07-25 7:03 ` [Qemu-devel] [PATCH v3 02/15] memory: Access MemoryRegion with MemOp tony.nguyen 2019-07-25 7:03 ` [Qemu-riscv] " tony.nguyen 2019-07-25 7:05 ` [Qemu-devel] [PATCH v3 03/15] target/mips: " tony.nguyen 2019-07-25 7:05 ` [Qemu-riscv] " tony.nguyen 2019-07-25 7:06 ` [Qemu-devel] [PATCH v3 04/15] hw/s390x: " tony.nguyen 2019-07-25 7:06 ` [Qemu-riscv] " tony.nguyen 2019-07-25 7:06 ` [Qemu-devel] [PATCH v3 05/15] hw/intc/armv7m_nic: " tony.nguyen 2019-07-25 7:06 ` [Qemu-riscv] " tony.nguyen 2019-07-25 7:07 ` [Qemu-devel] [PATCH v3 06/15] hw/virtio: " tony.nguyen 2019-07-25 7:07 ` [Qemu-riscv] " tony.nguyen 2019-07-25 7:08 ` [Qemu-devel] [PATCH v3 07/15] hw/vfio: " tony.nguyen 2019-07-25 7:08 ` [Qemu-riscv] " tony.nguyen 2019-07-25 7:08 ` [Qemu-devel] [PATCH v3 08/15] exec: " tony.nguyen 2019-07-25 7:08 ` [Qemu-riscv] " tony.nguyen 2019-07-25 7:08 ` [Qemu-devel] [PATCH v3 09/15] cputlb: " tony.nguyen 2019-07-25 7:08 ` [Qemu-riscv] " tony.nguyen 2019-07-25 7:09 ` [Qemu-devel] [PATCH v3 10/15] memory: Access MemoryRegion with MemOp semantics tony.nguyen 2019-07-25 7:09 ` [Qemu-riscv] " tony.nguyen 2019-07-25 7:10 ` [Qemu-devel] [PATCH v3 11/15] memory: Single byte swap along the I/O path tony.nguyen 2019-07-25 7:10 ` [Qemu-riscv] " tony.nguyen 2019-07-25 7:10 ` [Qemu-devel] [PATCH v3 12/15] cpu: TLB_FLAGS_MASK bit to force memory slow path tony.nguyen 2019-07-25 7:10 ` [Qemu-riscv] " tony.nguyen 2019-07-25 7:11 ` [Qemu-devel] [PATCH v3 13/15] cputlb: Byte swap memory transaction attribute tony.nguyen 2019-07-25 7:11 ` [Qemu-riscv] " tony.nguyen 2019-07-25 7:11 ` [Qemu-devel] [PATCH v3 14/15] target/sparc: Add TLB entry with attributes tony.nguyen 2019-07-25 7:11 ` [Qemu-riscv] " tony.nguyen 2019-07-25 7:12 ` [Qemu-devel] [PATCH v3 15/15] target/sparc: sun4u Invert Endian TTE bit tony.nguyen 2019-07-25 7:12 ` [Qemu-riscv] " tony.nguyen 2019-07-25 7:25 ` [Qemu-devel] [PATCH v3 00/15] Invert Endian bit in SPARCv9 MMU TTE no-reply 2019-07-25 7:25 ` [Qemu-riscv] " no-reply 2019-07-25 7:58 ` [Qemu-devel] [PATCH v4 " tony.nguyen 2019-07-25 7:58 ` [Qemu-riscv] " tony.nguyen 2019-07-25 8:00 ` [Qemu-devel] [PATCH v4 01/15] tcg: TCGMemOp is now accelerator independent MemOp tony.nguyen 2019-07-25 8:00 ` [Qemu-riscv] " tony.nguyen 2019-07-25 8:00 ` [Qemu-devel] [PATCH v4 02/15] memory: Access MemoryRegion with MemOp tony.nguyen 2019-07-25 8:00 ` [Qemu-riscv] " tony.nguyen 2019-07-25 8:01 ` [Qemu-devel] [PATCH v4 03/15] target/mips: " tony.nguyen 2019-07-25 8:01 ` [Qemu-riscv] " tony.nguyen 2019-07-25 8:01 ` [Qemu-devel] [PATCH v4 04/15] hw/s390x: " tony.nguyen 2019-07-25 8:01 ` [Qemu-riscv] " tony.nguyen 2019-07-25 8:02 ` [Qemu-devel] [PATCH v4 05/15] hw/intc/armv7m_nic: " tony.nguyen 2019-07-25 8:02 ` [Qemu-riscv] " tony.nguyen 2019-07-25 8:02 ` [Qemu-devel] [PATCH v4 06/15] hw/virtio: " tony.nguyen 2019-07-25 8:02 ` [Qemu-riscv] " tony.nguyen 2019-07-25 8:03 ` [Qemu-devel] [PATCH v4 07/15] hw/vfio: " tony.nguyen 2019-07-25 8:03 ` [Qemu-riscv] " tony.nguyen 2019-07-25 8:03 ` [Qemu-devel] [PATCH v4 08/15] exec: " tony.nguyen 2019-07-25 8:03 ` [Qemu-riscv] " tony.nguyen 2019-07-25 8:04 ` [Qemu-devel] [PATCH v4 09/15] cputlb: " tony.nguyen 2019-07-25 8:04 ` [Qemu-riscv] " tony.nguyen 2019-07-25 8:04 ` [Qemu-devel] [PATCH v4 10/15] memory: Access MemoryRegion with MemOp semantics tony.nguyen 2019-07-25 8:04 ` [Qemu-riscv] " tony.nguyen 2019-07-25 8:04 ` [Qemu-devel] [PATCH v4 11/15] memory: Single byte swap along the I/O path tony.nguyen 2019-07-25 8:04 ` [Qemu-riscv] " tony.nguyen 2019-07-25 8:05 ` [Qemu-devel] [PATCH v4 12/15] cpu: TLB_FLAGS_MASK bit to force memory slow path tony.nguyen 2019-07-25 8:05 ` [Qemu-riscv] " tony.nguyen 2019-07-25 8:05 ` [Qemu-devel] [PATCH v4 13/15] cputlb: Byte swap memory transaction attribute tony.nguyen 2019-07-25 8:05 ` [Qemu-riscv] " tony.nguyen 2019-07-25 8:06 ` [Qemu-devel] [PATCH v4 14/15] target/sparc: Add TLB entry with attributes tony.nguyen 2019-07-25 8:06 ` [Qemu-riscv] " tony.nguyen 2019-07-25 8:06 ` [Qemu-devel] [PATCH v4 15/15] target/sparc: sun4u Invert Endian TTE bit tony.nguyen 2019-07-25 8:06 ` [Qemu-riscv] " tony.nguyen 2019-07-22 15:52 ` tony.nguyen [this message] 2019-07-22 15:52 ` [Qemu-riscv] [Qemu-devel] [PATCH v2 18/20] cputlb: Byte swap memory transaction attribute tony.nguyen 2019-07-22 15:53 ` [Qemu-devel] [PATCH v2 19/20] target/sparc: Add TLB entry with attributes tony.nguyen 2019-07-22 15:53 ` [Qemu-riscv] " tony.nguyen 2019-07-22 15:54 ` [Qemu-devel] [PATCH v2 20/20] target/sparc: sun4u Invert Endian TTE bit tony.nguyen 2019-07-22 15:54 ` [Qemu-riscv] " tony.nguyen 2019-07-22 15:59 ` [Qemu-devel] [PATCH v2 00/20] Invert Endian bit in SPARCv9 MMU TTE Richard Henderson 2019-07-22 15:59 ` [Qemu-riscv] " Richard Henderson 2019-07-22 16:22 ` Paolo Bonzini 2019-07-22 16:22 ` [Qemu-riscv] " Paolo Bonzini 2019-07-22 16:28 ` tony.nguyen 2019-07-22 16:28 ` [Qemu-riscv] " tony.nguyen 2019-07-22 18:58 ` Richard Henderson 2019-07-22 18:58 ` [Qemu-riscv] " Richard Henderson
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