From: Robert Chiras <robert.chiras@nxp.com> To: "Guido Günther" <agx@sigxcpu.org>, "Marek Vasut" <marex@denx.de>, "Stefan Agner" <stefan@agner.ch>, "David Airlie" <airlied@linux.ie>, "Daniel Vetter" <daniel@ffwll.ch>, "Rob Herring" <robh+dt@kernel.org>, "Mark Rutland" <mark.rutland@arm.com>, "Shawn Guo" <shawnguo@kernel.org>, "Sascha Hauer" <s.hauer@pengutronix.de>, "Fabio Estevam" <festevam@gmail.com> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>, NXP Linux Team <linux-imx@nxp.com>, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 04/15] drm/mxsfb: Reset vital registers for a proper initialization Date: Wed, 21 Aug 2019 13:15:44 +0300 [thread overview] Message-ID: <1566382555-12102-5-git-send-email-robert.chiras@nxp.com> (raw) In-Reply-To: <1566382555-12102-1-git-send-email-robert.chiras@nxp.com> Some of the registers, like LCDC_CTRL, CTRL2_OUTSTANDING_REQS and CTRL1_RECOVERY_ON_UNDERFLOW needs to be properly cleared/initialized for a better start and stop routine. Signed-off-by: Robert Chiras <robert.chiras@nxp.com> --- drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c index b69ace8..5e44f57 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c @@ -127,6 +127,10 @@ static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb) clk_prepare_enable(mxsfb->clk_disp_axi); clk_prepare_enable(mxsfb->clk); + if (mxsfb->devdata->ipversion >= 4) + writel(CTRL2_OUTSTANDING_REQS(REQ_16), + mxsfb->base + LCDC_V4_CTRL2 + REG_SET); + /* If it was disabled, re-enable the mode again */ writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET); @@ -136,12 +140,19 @@ static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb) writel(reg, mxsfb->base + LCDC_VDCTRL4); writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_SET); + writel(CTRL1_RECOVERY_ON_UNDERFLOW, mxsfb->base + LCDC_CTRL1 + REG_SET); } static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb) { u32 reg; + if (mxsfb->devdata->ipversion >= 4) + writel(CTRL2_OUTSTANDING_REQS(0x7), + mxsfb->base + LCDC_V4_CTRL2 + REG_CLR); + + writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_CLR); + /* * Even if we disable the controller here, it will still continue * until its FIFOs are running out of data @@ -295,6 +306,7 @@ void mxsfb_crtc_enable(struct mxsfb_drm_private *mxsfb) dma_addr_t paddr; mxsfb_enable_axi_clk(mxsfb); + writel(0, mxsfb->base + LCDC_CTRL); mxsfb_crtc_mode_set_nofb(mxsfb); /* Write cur_buf as well to avoid an initial corrupt frame */ -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Robert Chiras <robert.chiras@nxp.com> To: "Guido Günther" <agx@sigxcpu.org>, "Marek Vasut" <marex@denx.de>, "Stefan Agner" <stefan@agner.ch>, "David Airlie" <airlied@linux.ie>, "Daniel Vetter" <daniel@ffwll.ch>, "Rob Herring" <robh+dt@kernel.org>, "Mark Rutland" <mark.rutland@arm.com>, "Shawn Guo" <shawnguo@kernel.org>, "Sascha Hauer" <s.hauer@pengutronix.de>, "Fabio Estevam" <festevam@gmail.com> Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, NXP Linux Team <linux-imx@nxp.com>, Pengutronix Kernel Team <kernel@pengutronix.de>, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 04/15] drm/mxsfb: Reset vital registers for a proper initialization Date: Wed, 21 Aug 2019 13:15:44 +0300 [thread overview] Message-ID: <1566382555-12102-5-git-send-email-robert.chiras@nxp.com> (raw) In-Reply-To: <1566382555-12102-1-git-send-email-robert.chiras@nxp.com> Some of the registers, like LCDC_CTRL, CTRL2_OUTSTANDING_REQS and CTRL1_RECOVERY_ON_UNDERFLOW needs to be properly cleared/initialized for a better start and stop routine. Signed-off-by: Robert Chiras <robert.chiras@nxp.com> --- drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c index b69ace8..5e44f57 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c @@ -127,6 +127,10 @@ static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb) clk_prepare_enable(mxsfb->clk_disp_axi); clk_prepare_enable(mxsfb->clk); + if (mxsfb->devdata->ipversion >= 4) + writel(CTRL2_OUTSTANDING_REQS(REQ_16), + mxsfb->base + LCDC_V4_CTRL2 + REG_SET); + /* If it was disabled, re-enable the mode again */ writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET); @@ -136,12 +140,19 @@ static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb) writel(reg, mxsfb->base + LCDC_VDCTRL4); writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_SET); + writel(CTRL1_RECOVERY_ON_UNDERFLOW, mxsfb->base + LCDC_CTRL1 + REG_SET); } static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb) { u32 reg; + if (mxsfb->devdata->ipversion >= 4) + writel(CTRL2_OUTSTANDING_REQS(0x7), + mxsfb->base + LCDC_V4_CTRL2 + REG_CLR); + + writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_CLR); + /* * Even if we disable the controller here, it will still continue * until its FIFOs are running out of data @@ -295,6 +306,7 @@ void mxsfb_crtc_enable(struct mxsfb_drm_private *mxsfb) dma_addr_t paddr; mxsfb_enable_axi_clk(mxsfb); + writel(0, mxsfb->base + LCDC_CTRL); mxsfb_crtc_mode_set_nofb(mxsfb); /* Write cur_buf as well to avoid an initial corrupt frame */ -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-08-21 10:17 UTC|newest] Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-08-21 10:15 [PATCH v3 00/15] Improvements and fixes for mxsfb DRM driver Robert Chiras 2019-08-21 10:15 ` Robert Chiras 2019-08-21 10:15 ` [PATCH v3 01/15] drm/mxsfb: Update mxsfb to support a bridge Robert Chiras 2019-08-21 10:15 ` Robert Chiras 2019-08-21 10:15 ` [PATCH v3 02/15] drm/mxsfb: Read bus flags from bridge if present Robert Chiras 2019-08-21 10:15 ` Robert Chiras 2019-08-21 10:15 ` [PATCH v3 03/15] drm/mxsfb: Add defines for the rest of registers Robert Chiras 2019-08-21 10:15 ` Robert Chiras 2019-08-21 10:15 ` Robert Chiras [this message] 2019-08-21 10:15 ` [PATCH v3 04/15] drm/mxsfb: Reset vital registers for a proper initialization Robert Chiras 2019-08-21 10:15 ` [PATCH v3 05/15] drm/mxsfb: Update register definitions using bit manipulation defines Robert Chiras 2019-08-21 10:15 ` Robert Chiras 2019-08-21 10:15 ` [PATCH v3 06/15] drm/mxsfb: Update mxsfb with additional pixel formats Robert Chiras 2019-08-21 10:15 ` Robert Chiras 2019-08-21 10:15 ` [PATCH v3 07/15] drm/mxsfb: Fix the vblank events Robert Chiras 2019-08-21 10:15 ` Robert Chiras 2019-08-21 10:15 ` [PATCH v3 08/15] drm/mxsfb: Signal mode changed when bpp changed Robert Chiras 2019-08-21 10:15 ` Robert Chiras 2019-08-21 10:15 ` [PATCH v3 09/15] drm/mxsfb: Add max-memory-bandwidth property for MXSFB Robert Chiras 2019-08-21 10:15 ` Robert Chiras 2019-08-21 10:15 ` [PATCH v3 10/15] dt-bindings: display: Add max-memory-bandwidth property for mxsfb Robert Chiras 2019-08-21 10:15 ` Robert Chiras 2019-08-27 17:25 ` Rob Herring 2019-08-27 17:25 ` Rob Herring 2019-08-21 10:15 ` [PATCH v3 11/15] drm/mxsfb: Update mxsfb to support LCD reset Robert Chiras 2019-08-21 10:15 ` Robert Chiras 2019-08-21 10:15 ` [PATCH v3 12/15] drm/mxsfb: Improve the axi clock usage Robert Chiras 2019-08-21 10:15 ` Robert Chiras 2019-08-21 10:15 ` [PATCH v3 13/15] drm/mxsfb: Clear OUTSTANDING_REQS bits Robert Chiras 2019-08-21 10:15 ` Robert Chiras 2019-08-21 10:15 ` [PATCH v3 14/15] drm/mxsfb: Add support for horizontal stride Robert Chiras 2019-08-21 10:15 ` Robert Chiras 2019-08-21 10:15 ` [PATCH v3 15/15] drm/mxsfb: Add support for live pixel format change Robert Chiras 2019-08-21 10:15 ` Robert Chiras 2019-08-26 12:05 ` [PATCH v3 00/15] Improvements and fixes for mxsfb DRM driver Guido Günther 2019-08-26 12:05 ` Guido Günther 2019-08-26 14:35 ` Stefan Agner 2019-08-26 14:35 ` Stefan Agner 2019-08-26 16:34 ` Guido Günther 2019-08-26 16:34 ` Guido Günther 2019-08-26 19:19 ` Leonard Crestez 2019-08-26 19:19 ` Leonard Crestez 2019-08-28 6:49 ` Robert Chiras 2019-08-28 6:49 ` Robert Chiras
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