From: Bin Meng <bmeng.cn@gmail.com> To: Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@sifive.com>, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [Qemu-devel] [PATCH v5 29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet Date: Thu, 22 Aug 2019 22:11:08 -0700 [thread overview] Message-ID: <1566537069-22741-30-git-send-email-bmeng.cn@gmail.com> (raw) In-Reply-To: <1566537069-22741-1-git-send-email-bmeng.cn@gmail.com> In the past we did not have a model for PRCI, hence two handcrafted clock nodes ("/soc/ethclk" and "/soc/uartclk") were created for the purpose of supplying hard-coded clock frequencies. But now since we have added the PRCI support in QEMU, we don't need them any more. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- Changes in v5: None Changes in v4: - new patch to remove handcrafted clock nodes for UART and ethernet Changes in v3: None Changes in v2: None hw/riscv/sifive_u.c | 24 +----------------------- include/hw/riscv/sifive_u.h | 3 +-- 2 files changed, 2 insertions(+), 25 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 503db4b..1140c38 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -88,8 +88,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, uint32_t *cells; char *nodename; char ethclk_names[] = "pclk\0hclk"; - uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1; - uint32_t uartclk_phandle; + uint32_t plic_phandle, prci_phandle, phandle = 1; uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; fdt = s->fdt = create_device_tree(&s->fdt_size); @@ -249,17 +248,6 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, g_free(cells); g_free(nodename); - ethclk_phandle = phandle++; - nodename = g_strdup_printf("/soc/ethclk"); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); - qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", - SIFIVE_U_GEM_CLOCK_FREQ); - qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle); - ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename); - g_free(nodename); - phy_phandle = phandle++; nodename = g_strdup_printf("/soc/ethernet@%lx", (long)memmap[SIFIVE_U_GEM].base); @@ -293,16 +281,6 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); g_free(nodename); - uartclk_phandle = phandle++; - nodename = g_strdup_printf("/soc/uartclk"); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); - qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400); - qemu_fdt_setprop_cell(fdt, nodename, "phandle", uartclk_phandle); - uartclk_phandle = qemu_fdt_get_phandle(fdt, nodename); - g_free(nodename); - nodename = g_strdup_printf("/soc/serial@%lx", (long)memmap[SIFIVE_U_UART0].base); qemu_fdt_add_subnode(fdt, nodename); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index d2b9d99..3bb87cb 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -76,8 +76,7 @@ enum { enum { SIFIVE_U_CLOCK_FREQ = 1000000000, SIFIVE_U_HFCLK_FREQ = 33333333, - SIFIVE_U_RTCCLK_FREQ = 1000000, - SIFIVE_U_GEM_CLOCK_FREQ = 125000000 + SIFIVE_U_RTCCLK_FREQ = 1000000 }; #define SIFIVE_U_MANAGEMENT_CPU_COUNT 1 -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Bin Meng <bmeng.cn@gmail.com> To: Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@sifive.com>, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [Qemu-riscv] [PATCH v5 29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet Date: Thu, 22 Aug 2019 22:11:08 -0700 [thread overview] Message-ID: <1566537069-22741-30-git-send-email-bmeng.cn@gmail.com> (raw) In-Reply-To: <1566537069-22741-1-git-send-email-bmeng.cn@gmail.com> In the past we did not have a model for PRCI, hence two handcrafted clock nodes ("/soc/ethclk" and "/soc/uartclk") were created for the purpose of supplying hard-coded clock frequencies. But now since we have added the PRCI support in QEMU, we don't need them any more. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- Changes in v5: None Changes in v4: - new patch to remove handcrafted clock nodes for UART and ethernet Changes in v3: None Changes in v2: None hw/riscv/sifive_u.c | 24 +----------------------- include/hw/riscv/sifive_u.h | 3 +-- 2 files changed, 2 insertions(+), 25 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 503db4b..1140c38 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -88,8 +88,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, uint32_t *cells; char *nodename; char ethclk_names[] = "pclk\0hclk"; - uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1; - uint32_t uartclk_phandle; + uint32_t plic_phandle, prci_phandle, phandle = 1; uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; fdt = s->fdt = create_device_tree(&s->fdt_size); @@ -249,17 +248,6 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, g_free(cells); g_free(nodename); - ethclk_phandle = phandle++; - nodename = g_strdup_printf("/soc/ethclk"); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); - qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", - SIFIVE_U_GEM_CLOCK_FREQ); - qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle); - ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename); - g_free(nodename); - phy_phandle = phandle++; nodename = g_strdup_printf("/soc/ethernet@%lx", (long)memmap[SIFIVE_U_GEM].base); @@ -293,16 +281,6 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); g_free(nodename); - uartclk_phandle = phandle++; - nodename = g_strdup_printf("/soc/uartclk"); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); - qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400); - qemu_fdt_setprop_cell(fdt, nodename, "phandle", uartclk_phandle); - uartclk_phandle = qemu_fdt_get_phandle(fdt, nodename); - g_free(nodename); - nodename = g_strdup_printf("/soc/serial@%lx", (long)memmap[SIFIVE_U_UART0].base); qemu_fdt_add_subnode(fdt, nodename); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index d2b9d99..3bb87cb 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -76,8 +76,7 @@ enum { enum { SIFIVE_U_CLOCK_FREQ = 1000000000, SIFIVE_U_HFCLK_FREQ = 33333333, - SIFIVE_U_RTCCLK_FREQ = 1000000, - SIFIVE_U_GEM_CLOCK_FREQ = 125000000 + SIFIVE_U_RTCCLK_FREQ = 1000000 }; #define SIFIVE_U_MANAGEMENT_CPU_COUNT 1 -- 2.7.4
next prev parent reply other threads:[~2019-08-23 5:41 UTC|newest] Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-08-23 5:10 [Qemu-devel] [PATCH v5 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Bin Meng 2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng 2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 01/30] riscv: hw: Remove superfluous "linux, phandle" property Bin Meng 2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng 2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 02/30] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell Bin Meng 2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng 2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 03/30] riscv: hw: Remove not needed PLIC properties in device tree Bin Meng 2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng 2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 04/30] riscv: hw: Change create_fdt() to return void Bin Meng 2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng 2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead Bin Meng 2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng 2019-08-23 17:38 ` [Qemu-devel] " Alistair Francis 2019-08-23 17:38 ` [Qemu-riscv] " Alistair Francis 2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h Bin Meng 2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng 2019-08-23 17:38 ` [Qemu-devel] " Alistair Francis 2019-08-23 17:38 ` [Qemu-riscv] " Alistair Francis 2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 07/30] riscv: roms: Remove executable attribute of opensbi images Bin Meng 2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng 2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 08/30] riscv: sifive_u: Remove the unnecessary include of prci header Bin Meng 2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng 2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} Bin Meng 2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng 2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming Bin Meng 2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng 2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 11/30] riscv: sifive_e: prci: Update the PRCI register block size Bin Meng 2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng 2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines Bin Meng 2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng 2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 14/30] riscv: hart: Extract hart realize to a separate routine Bin Meng 2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng 2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array Bin Meng 2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng 2019-08-23 18:31 ` [Qemu-devel] " Alistair Francis 2019-08-23 18:31 ` [Qemu-riscv] " Alistair Francis 2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 16/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC Bin Meng 2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng 2019-08-23 17:36 ` [Qemu-devel] " Alistair Francis 2019-08-23 17:36 ` [Qemu-riscv] " Alistair Francis 2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 17/30] riscv: sifive_u: Set the minimum number of cpus to 2 Bin Meng 2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng 2019-08-23 18:34 ` [Qemu-devel] " Alistair Francis 2019-08-23 18:34 ` [Qemu-riscv] " Alistair Francis 2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 18/30] riscv: sifive_u: Update PLIC hart topology configuration string Bin Meng 2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng 2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 19/30] riscv: sifive: Implement PRCI model for FU540 Bin Meng 2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng 2019-08-23 23:45 ` [Qemu-devel] " Alistair Francis 2019-08-23 23:45 ` [Qemu-riscv] " Alistair Francis 2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes Bin Meng 2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng 2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 21/30] riscv: sifive_u: Add PRCI block to the SoC Bin Meng 2019-08-23 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-23 23:52 ` [Qemu-devel] " Alistair Francis 2019-08-23 23:52 ` [Qemu-riscv] " Alistair Francis 2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes Bin Meng 2019-08-23 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 23/30] riscv: sifive_u: Update UART base addresses and IRQs Bin Meng 2019-08-23 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 24/30] riscv: sifive_u: Change UART node name in device tree Bin Meng 2019-08-23 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 25/30] riscv: roms: Update default bios for sifive_u machine Bin Meng 2019-08-23 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 26/30] riscv: sifive: Implement a model for SiFive FU540 OTP Bin Meng 2019-08-23 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 28/30] riscv: sifive_u: Fix broken GEM support Bin Meng 2019-08-23 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-23 5:11 ` Bin Meng [this message] 2019-08-23 5:11 ` [Qemu-riscv] [PATCH v5 29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet Bin Meng 2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 30/30] riscv: sifive_u: Update model and compatible strings in device tree Bin Meng 2019-08-23 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-23 17:24 ` [Qemu-devel] [PATCH v5 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Alistair Francis 2019-08-23 17:24 ` [Qemu-riscv] " Alistair Francis 2019-08-24 5:07 ` Bin Meng 2019-08-24 5:07 ` [Qemu-riscv] " Bin Meng 2019-08-26 21:33 ` Alistair Francis 2019-08-26 21:33 ` [Qemu-riscv] " Alistair Francis 2019-08-23 17:40 ` Alistair Francis 2019-08-23 17:40 ` [Qemu-riscv] " Alistair Francis [not found] ` <1566537069-22741-13-git-send-email-bmeng.cn@gmail.com> 2019-08-26 21:36 ` [Qemu-devel] [PATCH v5 12/30] riscv: sifive_e: Drop sifive_mmio_emulate() Alistair Francis 2019-08-26 21:36 ` [Qemu-riscv] " Alistair Francis
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