From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@sifive.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [Qemu-devel] [PATCH v5 08/30] riscv: sifive_u: Remove the unnecessary include of prci header
Date: Thu, 22 Aug 2019 22:10:47 -0700 [thread overview]
Message-ID: <1566537069-22741-9-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1566537069-22741-1-git-send-email-bmeng.cn@gmail.com>
sifive_u machine does not use PRCI as of today. Remove the prci
header inclusion.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_u.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index e22803b..3f58f61 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -39,7 +39,6 @@
#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_uart.h"
-#include "hw/riscv/sifive_prci.h"
#include "hw/riscv/sifive_u.h"
#include "hw/riscv/boot.h"
#include "chardev/char.h"
--
2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@sifive.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [Qemu-riscv] [PATCH v5 08/30] riscv: sifive_u: Remove the unnecessary include of prci header
Date: Thu, 22 Aug 2019 22:10:47 -0700 [thread overview]
Message-ID: <1566537069-22741-9-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1566537069-22741-1-git-send-email-bmeng.cn@gmail.com>
sifive_u machine does not use PRCI as of today. Remove the prci
header inclusion.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_u.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index e22803b..3f58f61 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -39,7 +39,6 @@
#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_uart.h"
-#include "hw/riscv/sifive_prci.h"
#include "hw/riscv/sifive_u.h"
#include "hw/riscv/boot.h"
#include "chardev/char.h"
--
2.7.4
next prev parent reply other threads:[~2019-08-23 5:19 UTC|newest]
Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-23 5:10 [Qemu-devel] [PATCH v5 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Bin Meng
2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 01/30] riscv: hw: Remove superfluous "linux, phandle" property Bin Meng
2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 02/30] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell Bin Meng
2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 03/30] riscv: hw: Remove not needed PLIC properties in device tree Bin Meng
2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 04/30] riscv: hw: Change create_fdt() to return void Bin Meng
2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead Bin Meng
2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng
2019-08-23 17:38 ` [Qemu-devel] " Alistair Francis
2019-08-23 17:38 ` [Qemu-riscv] " Alistair Francis
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h Bin Meng
2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng
2019-08-23 17:38 ` [Qemu-devel] " Alistair Francis
2019-08-23 17:38 ` [Qemu-riscv] " Alistair Francis
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 07/30] riscv: roms: Remove executable attribute of opensbi images Bin Meng
2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng
2019-08-23 5:10 ` Bin Meng [this message]
2019-08-23 5:10 ` [Qemu-riscv] [PATCH v5 08/30] riscv: sifive_u: Remove the unnecessary include of prci header Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} Bin Meng
2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming Bin Meng
2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 11/30] riscv: sifive_e: prci: Update the PRCI register block size Bin Meng
2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines Bin Meng
2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 14/30] riscv: hart: Extract hart realize to a separate routine Bin Meng
2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array Bin Meng
2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng
2019-08-23 18:31 ` [Qemu-devel] " Alistair Francis
2019-08-23 18:31 ` [Qemu-riscv] " Alistair Francis
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 16/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC Bin Meng
2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng
2019-08-23 17:36 ` [Qemu-devel] " Alistair Francis
2019-08-23 17:36 ` [Qemu-riscv] " Alistair Francis
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 17/30] riscv: sifive_u: Set the minimum number of cpus to 2 Bin Meng
2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng
2019-08-23 18:34 ` [Qemu-devel] " Alistair Francis
2019-08-23 18:34 ` [Qemu-riscv] " Alistair Francis
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 18/30] riscv: sifive_u: Update PLIC hart topology configuration string Bin Meng
2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 19/30] riscv: sifive: Implement PRCI model for FU540 Bin Meng
2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng
2019-08-23 23:45 ` [Qemu-devel] " Alistair Francis
2019-08-23 23:45 ` [Qemu-riscv] " Alistair Francis
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes Bin Meng
2019-08-23 5:10 ` [Qemu-riscv] " Bin Meng
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 21/30] riscv: sifive_u: Add PRCI block to the SoC Bin Meng
2019-08-23 5:11 ` [Qemu-riscv] " Bin Meng
2019-08-23 23:52 ` [Qemu-devel] " Alistair Francis
2019-08-23 23:52 ` [Qemu-riscv] " Alistair Francis
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes Bin Meng
2019-08-23 5:11 ` [Qemu-riscv] " Bin Meng
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 23/30] riscv: sifive_u: Update UART base addresses and IRQs Bin Meng
2019-08-23 5:11 ` [Qemu-riscv] " Bin Meng
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 24/30] riscv: sifive_u: Change UART node name in device tree Bin Meng
2019-08-23 5:11 ` [Qemu-riscv] " Bin Meng
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 25/30] riscv: roms: Update default bios for sifive_u machine Bin Meng
2019-08-23 5:11 ` [Qemu-riscv] " Bin Meng
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 26/30] riscv: sifive: Implement a model for SiFive FU540 OTP Bin Meng
2019-08-23 5:11 ` [Qemu-riscv] " Bin Meng
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 28/30] riscv: sifive_u: Fix broken GEM support Bin Meng
2019-08-23 5:11 ` [Qemu-riscv] " Bin Meng
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet Bin Meng
2019-08-23 5:11 ` [Qemu-riscv] " Bin Meng
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 30/30] riscv: sifive_u: Update model and compatible strings in device tree Bin Meng
2019-08-23 5:11 ` [Qemu-riscv] " Bin Meng
2019-08-23 17:24 ` [Qemu-devel] [PATCH v5 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Alistair Francis
2019-08-23 17:24 ` [Qemu-riscv] " Alistair Francis
2019-08-24 5:07 ` Bin Meng
2019-08-24 5:07 ` [Qemu-riscv] " Bin Meng
2019-08-26 21:33 ` Alistair Francis
2019-08-26 21:33 ` [Qemu-riscv] " Alistair Francis
2019-08-23 17:40 ` Alistair Francis
2019-08-23 17:40 ` [Qemu-riscv] " Alistair Francis
[not found] ` <1566537069-22741-13-git-send-email-bmeng.cn@gmail.com>
2019-08-26 21:36 ` [Qemu-devel] [PATCH v5 12/30] riscv: sifive_e: Drop sifive_mmio_emulate() Alistair Francis
2019-08-26 21:36 ` [Qemu-riscv] " Alistair Francis
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