* [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0
@ 2019-08-28 16:26 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 01/30] target/mips: Clean up handling of CP0 register 0 Aleksandar Markovic
` (30 more replies)
0 siblings, 31 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
v1->v2:
- added cleanup of handling six more registers
- misc improvements
This series is a spin-off of a former "Misc MIPS fixes for 4.2" series.
The goal of the series is to clean up CP0-related code, and prepare
it for (near) future extensions and amendments.
The series is mostly of refactoring nature, however it may contain
simple fixes (for example, fixes for obvious bugs, or additions of
simple subregister handling). The more complex fixes and improvements
(for example, additions of VPE-related functionalities) are, for now,
outside the scope of this series.
Aleksandar Markovic (30):
target/mips: Clean up handling of CP0 register 0
target/mips: Clean up handling of CP0 register 1
target/mips: Clean up handling of CP0 register 2
target/mips: Clean up handling of CP0 register 3
target/mips: Clean up handling of CP0 register 4
target/mips: Clean up handling of CP0 register 5
target/mips: Clean up handling of CP0 register 6
target/mips: Clean up handling of CP0 register 7
target/mips: Clean up handling of CP0 register 8
target/mips: Clean up handling of CP0 register 9
target/mips: Clean up handling of CP0 register 10
target/mips: Clean up handling of CP0 register 11
target/mips: Clean up handling of CP0 register 12
target/mips: Clean up handling of CP0 register 13
target/mips: Clean up handling of CP0 register 14
target/mips: Clean up handling of CP0 register 15
target/mips: Clean up handling of CP0 register 16
target/mips: Clean up handling of CP0 register 17
target/mips: Clean up handling of CP0 register 18
target/mips: Clean up handling of CP0 register 19
target/mips: Clean up handling of CP0 register 20
target/mips: Clean up handling of CP0 register 23
target/mips: Clean up handling of CP0 register 24
target/mips: Clean up handling of CP0 register 25
target/mips: Clean up handling of CP0 register 26
target/mips: Clean up handling of CP0 register 27
target/mips: Clean up handling of CP0 register 28
target/mips: Clean up handling of CP0 register 29
target/mips: Clean up handling of CP0 register 30
target/mips: Clean up handling of CP0 register 31
target/mips/cpu.h | 113 ++++-
target/mips/translate.c | 1150 ++++++++++++++++++++++++-----------------------
2 files changed, 681 insertions(+), 582 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 01/30] target/mips: Clean up handling of CP0 register 0
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 02/30] target/mips: Clean up handling of CP0 register 1 Aleksandar Markovic
` (29 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 0.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 3 +++
target/mips/translate.c | 40 ++++++++++++++++++++--------------------
2 files changed, 23 insertions(+), 20 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index eda8350..e2f6844 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -279,6 +279,9 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 00 */
#define CP0_REG00__INDEX 0
+#define CP0_REG00__MVPCONTROL 1
+#define CP0_REG00__MVPCONF0 2
+#define CP0_REG00__MVPCONF1 3
#define CP0_REG00__VPCONTROL 4
/* CP0 Register 01 */
/* CP0 Register 02 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index fe4a05c..06a1646 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6853,26 +6853,26 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
- case 0:
+ case CP0_REG00__INDEX:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
register_name = "Index";
break;
- case 1:
+ case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpcontrol(arg, cpu_env);
register_name = "MVPControl";
break;
- case 2:
+ case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf0(arg, cpu_env);
register_name = "MVPConf0";
break;
- case 3:
+ case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf1(arg, cpu_env);
register_name = "MVPConf1";
break;
- case 4:
+ case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
register_name = "VPControl";
@@ -7621,26 +7621,26 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
- case 0:
+ case CP0_REG00__INDEX:
gen_helper_mtc0_index(cpu_env, arg);
register_name = "Index";
break;
- case 1:
+ case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_mvpcontrol(cpu_env, arg);
register_name = "MVPControl";
break;
- case 2:
+ case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf0";
break;
- case 3:
+ case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf1";
break;
- case 4:
+ case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
/* ignored */
register_name = "VPControl";
@@ -8373,26 +8373,26 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
- case 0:
+ case CP0_REG00__INDEX:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
register_name = "Index";
break;
- case 1:
+ case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpcontrol(arg, cpu_env);
register_name = "MVPControl";
break;
- case 2:
+ case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf0(arg, cpu_env);
register_name = "MVPConf0";
break;
- case 3:
+ case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf1(arg, cpu_env);
register_name = "MVPConf1";
break;
- case 4:
+ case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
register_name = "VPControl";
@@ -9095,26 +9095,26 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
- case 0:
+ case CP0_REG00__INDEX:
gen_helper_mtc0_index(cpu_env, arg);
register_name = "Index";
break;
- case 1:
+ case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_mvpcontrol(cpu_env, arg);
register_name = "MVPControl";
break;
- case 2:
+ case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf0";
break;
- case 3:
+ case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf1";
break;
- case 4:
+ case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
/* ignored */
register_name = "VPControl";
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 02/30] target/mips: Clean up handling of CP0 register 1
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 01/30] target/mips: Clean up handling of CP0 register 0 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 03/30] target/mips: Clean up handling of CP0 register 2 Aleksandar Markovic
` (28 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 1.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 8 +++++++
target/mips/translate.c | 64 ++++++++++++++++++++++++-------------------------
2 files changed, 40 insertions(+), 32 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index e2f6844..597afa8 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -284,6 +284,14 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG00__MVPCONF1 3
#define CP0_REG00__VPCONTROL 4
/* CP0 Register 01 */
+#define CP0_REG01__RANDOM 0
+#define CP0_REG01__VPECONTROL 1
+#define CP0_REG01__VPECONF0 2
+#define CP0_REG01__VPECONF1 3
+#define CP0_REG01__YQMASK 4
+#define CP0_REG01__VPESCHEDULE 5
+#define CP0_REG01__VPESCHEFBACK 6
+#define CP0_REG01__VPEOPT 7
/* CP0 Register 02 */
#define CP0_REG02__ENTRYLO0 0
/* CP0 Register 03 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 06a1646..e350545 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6883,42 +6883,42 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_01:
switch (sel) {
- case 0:
+ case CP0_REG01__RANDOM:
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
gen_helper_mfc0_random(arg, cpu_env);
register_name = "Random";
break;
- case 1:
+ case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
register_name = "VPEControl";
break;
- case 2:
+ case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
register_name = "VPEConf0";
break;
- case 3:
+ case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
register_name = "VPEConf1";
break;
- case 4:
+ case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_YQMask));
register_name = "YQMask";
break;
- case 5:
+ case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
- case 6:
+ case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
- case 7:
+ case CP0_REG01__VPEOPT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
register_name = "VPEOpt";
@@ -7651,43 +7651,43 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_01:
switch (sel) {
- case 0:
+ case CP0_REG01__RANDOM:
/* ignored */
register_name = "Random";
break;
- case 1:
+ case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpecontrol(cpu_env, arg);
register_name = "VPEControl";
break;
- case 2:
+ case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf0(cpu_env, arg);
register_name = "VPEConf0";
break;
- case 3:
+ case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf1(cpu_env, arg);
register_name = "VPEConf1";
break;
- case 4:
+ case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_yqmask(cpu_env, arg);
register_name = "YQMask";
break;
- case 5:
+ case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
- case 6:
+ case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
- case 7:
+ case CP0_REG01__VPEOPT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeopt(cpu_env, arg);
register_name = "VPEOpt";
@@ -8403,42 +8403,42 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_01:
switch (sel) {
- case 0:
+ case CP0_REG01__RANDOM:
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
gen_helper_mfc0_random(arg, cpu_env);
register_name = "Random";
break;
- case 1:
+ case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
register_name = "VPEControl";
break;
- case 2:
+ case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
register_name = "VPEConf0";
break;
- case 3:
+ case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
register_name = "VPEConf1";
break;
- case 4:
+ case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_YQMask));
register_name = "YQMask";
break;
- case 5:
+ case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
- case 6:
+ case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
- case 7:
+ case CP0_REG01__VPEOPT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
register_name = "VPEOpt";
@@ -9125,41 +9125,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_01:
switch (sel) {
- case 0:
+ case CP0_REG01__RANDOM:
/* ignored */
register_name = "Random";
break;
- case 1:
+ case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpecontrol(cpu_env, arg);
register_name = "VPEControl";
break;
- case 2:
+ case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf0(cpu_env, arg);
register_name = "VPEConf0";
break;
- case 3:
+ case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf1(cpu_env, arg);
register_name = "VPEConf1";
break;
- case 4:
+ case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_yqmask(cpu_env, arg);
register_name = "YQMask";
break;
- case 5:
+ case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
- case 6:
+ case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
- case 7:
+ case CP0_REG01__VPEOPT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeopt(cpu_env, arg);
register_name = "VPEOpt";
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 03/30] target/mips: Clean up handling of CP0 register 2
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 01/30] target/mips: Clean up handling of CP0 register 0 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 02/30] target/mips: Clean up handling of CP0 register 1 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 04/30] target/mips: Clean up handling of CP0 register 3 Aleksandar Markovic
` (27 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 2.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 7 ++++++
target/mips/translate.c | 64 ++++++++++++++++++++++++-------------------------
2 files changed, 39 insertions(+), 32 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 597afa8..eebdc9f 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -294,6 +294,13 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG01__VPEOPT 7
/* CP0 Register 02 */
#define CP0_REG02__ENTRYLO0 0
+#define CP0_REG02__TCSTATUS 1
+#define CP0_REG02__TCBIND 2
+#define CP0_REG02__TCRESTART 3
+#define CP0_REG02__TCHALT 4
+#define CP0_REG02__TCCONTEXT 5
+#define CP0_REG02__TCSCHEDULE 6
+#define CP0_REG02__TCSCHEFBACK 7
/* CP0 Register 03 */
#define CP0_REG03__ENTRYLO1 0
#define CP0_REG03__GLOBALNUM 1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index e350545..6e65312 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6929,7 +6929,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
- case 0:
+ case CP0_REG02__ENTRYLO0:
{
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp, cpu_env,
@@ -6946,37 +6946,37 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
}
register_name = "EntryLo0";
break;
- case 1:
+ case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcstatus(arg, cpu_env);
register_name = "TCStatus";
break;
- case 2:
+ case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcbind(arg, cpu_env);
register_name = "TCBind";
break;
- case 3:
+ case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcrestart(arg, cpu_env);
register_name = "TCRestart";
break;
- case 4:
+ case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tchalt(arg, cpu_env);
register_name = "TCHalt";
break;
- case 5:
+ case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tccontext(arg, cpu_env);
register_name = "TCContext";
break;
- case 6:
+ case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcschedule(arg, cpu_env);
register_name = "TCSchedule";
break;
- case 7:
+ case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcschefback(arg, cpu_env);
register_name = "TCScheFBack";
@@ -7698,41 +7698,41 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
- case 0:
+ case CP0_REG02__ENTRYLO0:
gen_helper_mtc0_entrylo0(cpu_env, arg);
register_name = "EntryLo0";
break;
- case 1:
+ case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcstatus(cpu_env, arg);
register_name = "TCStatus";
break;
- case 2:
+ case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcbind(cpu_env, arg);
register_name = "TCBind";
break;
- case 3:
+ case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcrestart(cpu_env, arg);
register_name = "TCRestart";
break;
- case 4:
+ case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tchalt(cpu_env, arg);
register_name = "TCHalt";
break;
- case 5:
+ case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tccontext(cpu_env, arg);
register_name = "TCContext";
break;
- case 6:
+ case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschedule(cpu_env, arg);
register_name = "TCSchedule";
break;
- case 7:
+ case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschefback(cpu_env, arg);
register_name = "TCScheFBack";
@@ -8449,41 +8449,41 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
- case 0:
+ case CP0_REG02__ENTRYLO0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
register_name = "EntryLo0";
break;
- case 1:
+ case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcstatus(arg, cpu_env);
register_name = "TCStatus";
break;
- case 2:
+ case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcbind(arg, cpu_env);
register_name = "TCBind";
break;
- case 3:
+ case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tcrestart(arg, cpu_env);
register_name = "TCRestart";
break;
- case 4:
+ case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tchalt(arg, cpu_env);
register_name = "TCHalt";
break;
- case 5:
+ case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tccontext(arg, cpu_env);
register_name = "TCContext";
break;
- case 6:
+ case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tcschedule(arg, cpu_env);
register_name = "TCSchedule";
break;
- case 7:
+ case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tcschefback(arg, cpu_env);
register_name = "TCScheFBack";
@@ -9170,41 +9170,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
- case 0:
+ case CP0_REG02__ENTRYLO0:
gen_helper_dmtc0_entrylo0(cpu_env, arg);
register_name = "EntryLo0";
break;
- case 1:
+ case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcstatus(cpu_env, arg);
register_name = "TCStatus";
break;
- case 2:
+ case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcbind(cpu_env, arg);
register_name = "TCBind";
break;
- case 3:
+ case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcrestart(cpu_env, arg);
register_name = "TCRestart";
break;
- case 4:
+ case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tchalt(cpu_env, arg);
register_name = "TCHalt";
break;
- case 5:
+ case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tccontext(cpu_env, arg);
register_name = "TCContext";
break;
- case 6:
+ case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschedule(cpu_env, arg);
register_name = "TCSchedule";
break;
- case 7:
+ case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschefback(cpu_env, arg);
register_name = "TCScheFBack";
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 04/30] target/mips: Clean up handling of CP0 register 3
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (2 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 03/30] target/mips: Clean up handling of CP0 register 2 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 05/30] target/mips: Clean up handling of CP0 register 4 Aleksandar Markovic
` (26 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 3.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 1 +
target/mips/translate.c | 20 ++++++++++----------
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index eebdc9f..c2ef942 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -304,6 +304,7 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 03 */
#define CP0_REG03__ENTRYLO1 0
#define CP0_REG03__GLOBALNUM 1
+#define CP0_REG03__TCOPT 7
/* CP0 Register 04 */
#define CP0_REG04__CONTEXT 0
#define CP0_REG04__USERLOCAL 2
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 6e65312..013dd53 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6649,7 +6649,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_03:
switch (sel) {
- case 0:
+ case CP0_REG03__ENTRYLO1:
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
register_name = "EntryLo1";
@@ -6749,7 +6749,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_03:
switch (sel) {
- case 0:
+ case CP0_REG03__ENTRYLO1:
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
tcg_gen_andi_tl(arg, arg, mask);
gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
@@ -6987,7 +6987,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_03:
switch (sel) {
- case 0:
+ case CP0_REG03__ENTRYLO1:
{
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp, cpu_env,
@@ -7004,7 +7004,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
}
register_name = "EntryLo1";
break;
- case 1:
+ case CP0_REG03__GLOBALNUM:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber));
register_name = "GlobalNumber";
@@ -7743,11 +7743,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_03:
switch (sel) {
- case 0:
+ case CP0_REG03__ENTRYLO1:
gen_helper_mtc0_entrylo1(cpu_env, arg);
register_name = "EntryLo1";
break;
- case 1:
+ case CP0_REG03__GLOBALNUM:
CP0_CHECK(ctx->vp);
/* ignored */
register_name = "GlobalNumber";
@@ -8494,11 +8494,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_03:
switch (sel) {
- case 0:
+ case CP0_REG03__ENTRYLO1:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1));
register_name = "EntryLo1";
break;
- case 1:
+ case CP0_REG03__GLOBALNUM:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber));
register_name = "GlobalNumber";
@@ -9215,11 +9215,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_03:
switch (sel) {
- case 0:
+ case CP0_REG03__ENTRYLO1:
gen_helper_dmtc0_entrylo1(cpu_env, arg);
register_name = "EntryLo1";
break;
- case 1:
+ case CP0_REG03__GLOBALNUM:
CP0_CHECK(ctx->vp);
/* ignored */
register_name = "GlobalNumber";
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 05/30] target/mips: Clean up handling of CP0 register 4
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (3 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 04/30] target/mips: Clean up handling of CP0 register 3 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 06/30] target/mips: Clean up handling of CP0 register 5 Aleksandar Markovic
` (25 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 4.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 2 ++
target/mips/translate.c | 44 ++++++++++++++++++++++++--------------------
2 files changed, 26 insertions(+), 20 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index c2ef942..04d4b09 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -307,7 +307,9 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG03__TCOPT 7
/* CP0 Register 04 */
#define CP0_REG04__CONTEXT 0
+#define CP0_REG04__CONTEXTCONFIG 1
#define CP0_REG04__USERLOCAL 2
+#define CP0_REG04__XCONTEXTCONFIG 3
#define CP0_REG04__DBGCONTEXTID 4
#define CP0_REG04__MEMORYMAPID 5
/* CP0 Register 05 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 013dd53..677a2d0 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7015,23 +7015,24 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_04:
switch (sel) {
- case 0:
+ case CP0_REG04__CONTEXT:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
tcg_gen_ext32s_tl(arg, arg);
register_name = "Context";
break;
- case 1:
- /* gen_helper_mfc0_contextconfig(arg); - SmartMIPS ASE */
+ case CP0_REG04__CONTEXTCONFIG:
+ /* SmartMIPS ASE */
+ /* gen_helper_mfc0_contextconfig(arg); */
register_name = "ContextConfig";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
tcg_gen_ext32s_tl(arg, arg);
register_name = "UserLocal";
break;
- case 5:
+ case CP0_REG04__MEMORYMAPID:
CP0_CHECK(ctx->mi);
gen_helper_mtc0_memorymapid(cpu_env, arg);
register_name = "MemoryMapID";
@@ -7758,21 +7759,22 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_04:
switch (sel) {
- case 0:
+ case CP0_REG04__CONTEXT:
gen_helper_mtc0_context(cpu_env, arg);
register_name = "Context";
break;
- case 1:
-// gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
+ case CP0_REG04__CONTEXTCONFIG:
+ /* SmartMIPS ASE */
+ /* gen_helper_mtc0_contextconfig(cpu_env, arg); */
register_name = "ContextConfig";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
register_name = "UserLocal";
break;
- case 5:
+ case CP0_REG04__MEMORYMAPID:
CP0_CHECK(ctx->mi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MemoryMapID));
register_name = "MemoryMapID";
@@ -8509,21 +8511,22 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_04:
switch (sel) {
- case 0:
+ case CP0_REG04__CONTEXT:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
register_name = "Context";
break;
- case 1:
-// gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
+ case CP0_REG04__CONTEXTCONFIG:
+ /* SmartMIPS ASE */
+ /* gen_helper_dmfc0_contextconfig(arg); */
register_name = "ContextConfig";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
register_name = "UserLocal";
break;
- case 5:
+ case CP0_REG04__MEMORYMAPID:
CP0_CHECK(ctx->mi);
gen_helper_mtc0_memorymapid(cpu_env, arg);
register_name = "MemoryMapID";
@@ -9230,21 +9233,22 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_04:
switch (sel) {
- case 0:
+ case CP0_REG04__CONTEXT:
gen_helper_mtc0_context(cpu_env, arg);
register_name = "Context";
break;
- case 1:
-// gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
+ case CP0_REG04__CONTEXTCONFIG:
+ /* SmartMIPS ASE */
+ /* gen_helper_mtc0_contextconfig(cpu_env, arg); */
register_name = "ContextConfig";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
register_name = "UserLocal";
break;
- case 5:
+ case CP0_REG04__MEMORYMAPID:
CP0_CHECK(ctx->mi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MemoryMapID));
register_name = "MemoryMapID";
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 06/30] target/mips: Clean up handling of CP0 register 5
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (4 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 05/30] target/mips: Clean up handling of CP0 register 4 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 07/30] target/mips: Clean up handling of CP0 register 6 Aleksandar Markovic
` (24 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 5.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 6 +++++
target/mips/translate.c | 64 ++++++++++++++++++++++++-------------------------
2 files changed, 38 insertions(+), 32 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 04d4b09..248f7df 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -315,6 +315,12 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 05 */
#define CP0_REG05__PAGEMASK 0
#define CP0_REG05__PAGEGRAIN 1
+#define CP0_REG05__SEGCTL0 2
+#define CP0_REG05__SEGCTL1 3
+#define CP0_REG05__SEGCTL2 4
+#define CP0_REG05__PWBASE 5
+#define CP0_REG05__PWFIELD 6
+#define CP0_REG05__PWSIZE 7
/* CP0 Register 06 */
#define CP0_REG06__WIRED 0
/* CP0 Register 07 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 677a2d0..4395345 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7043,44 +7043,44 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_05:
switch (sel) {
- case 0:
+ case CP0_REG05__PAGEMASK:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
register_name = "PageMask";
break;
- case 1:
+ case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
register_name = "PageGrain";
break;
- case 2:
+ case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl0";
break;
- case 3:
+ case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl1";
break;
- case 4:
+ case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl2";
break;
- case 5:
+ case CP0_REG05__PWBASE:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
- case 6:
+ case CP0_REG05__PWFIELD:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField));
register_name = "PWField";
break;
- case 7:
+ case CP0_REG05__PWSIZE:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWSize));
register_name = "PWSize";
@@ -7785,42 +7785,42 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_05:
switch (sel) {
- case 0:
+ case CP0_REG05__PAGEMASK:
gen_helper_mtc0_pagemask(cpu_env, arg);
register_name = "PageMask";
break;
- case 1:
+ case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_pagegrain(cpu_env, arg);
register_name = "PageGrain";
ctx->base.is_jmp = DISAS_STOP;
break;
- case 2:
+ case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl0(cpu_env, arg);
register_name = "SegCtl0";
break;
- case 3:
+ case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl1(cpu_env, arg);
register_name = "SegCtl1";
break;
- case 4:
+ case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl2(cpu_env, arg);
register_name = "SegCtl2";
break;
- case 5:
+ case CP0_REG05__PWBASE:
check_pw(ctx);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
- case 6:
+ case CP0_REG05__PWFIELD:
check_pw(ctx);
gen_helper_mtc0_pwfield(cpu_env, arg);
register_name = "PWField";
break;
- case 7:
+ case CP0_REG05__PWSIZE:
check_pw(ctx);
gen_helper_mtc0_pwsize(cpu_env, arg);
register_name = "PWSize";
@@ -8537,41 +8537,41 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_05:
switch (sel) {
- case 0:
+ case CP0_REG05__PAGEMASK:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
register_name = "PageMask";
break;
- case 1:
+ case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
register_name = "PageGrain";
break;
- case 2:
+ case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
register_name = "SegCtl0";
break;
- case 3:
+ case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
register_name = "SegCtl1";
break;
- case 4:
+ case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
register_name = "SegCtl2";
break;
- case 5:
+ case CP0_REG05__PWBASE:
check_pw(ctx);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
- case 6:
+ case CP0_REG05__PWFIELD:
check_pw(ctx);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWField));
register_name = "PWField";
break;
- case 7:
+ case CP0_REG05__PWSIZE:
check_pw(ctx);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWSize));
register_name = "PWSize";
@@ -9259,41 +9259,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_05:
switch (sel) {
- case 0:
+ case CP0_REG05__PAGEMASK:
gen_helper_mtc0_pagemask(cpu_env, arg);
register_name = "PageMask";
break;
- case 1:
+ case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_pagegrain(cpu_env, arg);
register_name = "PageGrain";
break;
- case 2:
+ case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl0(cpu_env, arg);
register_name = "SegCtl0";
break;
- case 3:
+ case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl1(cpu_env, arg);
register_name = "SegCtl1";
break;
- case 4:
+ case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl2(cpu_env, arg);
register_name = "SegCtl2";
break;
- case 5:
+ case CP0_REG05__PWBASE:
check_pw(ctx);
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
- case 6:
+ case CP0_REG05__PWFIELD:
check_pw(ctx);
gen_helper_mtc0_pwfield(cpu_env, arg);
register_name = "PWField";
break;
- case 7:
+ case CP0_REG05__PWSIZE:
check_pw(ctx);
gen_helper_mtc0_pwsize(cpu_env, arg);
register_name = "PWSize";
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 07/30] target/mips: Clean up handling of CP0 register 6
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (5 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 06/30] target/mips: Clean up handling of CP0 register 5 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 08/30] target/mips: Clean up handling of CP0 register 7 Aleksandar Markovic
` (23 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 6.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 6 ++++++
target/mips/translate.c | 56 ++++++++++++++++++++++++-------------------------
2 files changed, 34 insertions(+), 28 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 248f7df..74a760e 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -323,6 +323,12 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG05__PWSIZE 7
/* CP0 Register 06 */
#define CP0_REG06__WIRED 0
+#define CP0_REG06__SRSCONF0 1
+#define CP0_REG06__SRSCONF1 2
+#define CP0_REG06__SRSCONF2 3
+#define CP0_REG06__SRSCONF3 4
+#define CP0_REG06__SRSCONF4 5
+#define CP0_REG06__PWCTL 6
/* CP0 Register 07 */
#define CP0_REG07__HWRENA 0
/* CP0 Register 08 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4395345..451805f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7091,36 +7091,36 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_06:
switch (sel) {
- case 0:
+ case CP0_REG06__WIRED:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
register_name = "Wired";
break;
- case 1:
+ case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
register_name = "SRSConf0";
break;
- case 2:
+ case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
register_name = "SRSConf1";
break;
- case 3:
+ case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
register_name = "SRSConf2";
break;
- case 4:
+ case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
register_name = "SRSConf3";
break;
- case 5:
+ case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
register_name = "SRSConf4";
break;
- case 6:
+ case CP0_REG06__PWCTL:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
register_name = "PWCtl";
@@ -7831,36 +7831,36 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_06:
switch (sel) {
- case 0:
+ case CP0_REG06__WIRED:
gen_helper_mtc0_wired(cpu_env, arg);
register_name = "Wired";
break;
- case 1:
+ case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf0(cpu_env, arg);
register_name = "SRSConf0";
break;
- case 2:
+ case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf1(cpu_env, arg);
register_name = "SRSConf1";
break;
- case 3:
+ case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf2(cpu_env, arg);
register_name = "SRSConf2";
break;
- case 4:
+ case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf3(cpu_env, arg);
register_name = "SRSConf3";
break;
- case 5:
+ case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf4(cpu_env, arg);
register_name = "SRSConf4";
break;
- case 6:
+ case CP0_REG06__PWCTL:
check_pw(ctx);
gen_helper_mtc0_pwctl(cpu_env, arg);
register_name = "PWCtl";
@@ -8582,36 +8582,36 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_06:
switch (sel) {
- case 0:
+ case CP0_REG06__WIRED:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
register_name = "Wired";
break;
- case 1:
+ case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
register_name = "SRSConf0";
break;
- case 2:
+ case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
register_name = "SRSConf1";
break;
- case 3:
+ case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
register_name = "SRSConf2";
break;
- case 4:
+ case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
register_name = "SRSConf3";
break;
- case 5:
+ case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
register_name = "SRSConf4";
break;
- case 6:
+ case CP0_REG06__PWCTL:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
register_name = "PWCtl";
@@ -9304,36 +9304,36 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_06:
switch (sel) {
- case 0:
+ case CP0_REG06__WIRED:
gen_helper_mtc0_wired(cpu_env, arg);
register_name = "Wired";
break;
- case 1:
+ case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf0(cpu_env, arg);
register_name = "SRSConf0";
break;
- case 2:
+ case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf1(cpu_env, arg);
register_name = "SRSConf1";
break;
- case 3:
+ case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf2(cpu_env, arg);
register_name = "SRSConf2";
break;
- case 4:
+ case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf3(cpu_env, arg);
register_name = "SRSConf3";
break;
- case 5:
+ case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf4(cpu_env, arg);
register_name = "SRSConf4";
break;
- case 6:
+ case CP0_REG06__PWCTL:
check_pw(ctx);
gen_helper_mtc0_pwctl(cpu_env, arg);
register_name = "PWCtl";
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 08/30] target/mips: Clean up handling of CP0 register 7
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (6 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 07/30] target/mips: Clean up handling of CP0 register 6 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 09/30] target/mips: Clean up handling of CP0 register 8 Aleksandar Markovic
` (22 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 7.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 451805f..1222241 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7131,7 +7131,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_07:
switch (sel) {
- case 0:
+ case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
register_name = "HWREna";
@@ -7871,7 +7871,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_07:
switch (sel) {
- case 0:
+ case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_hwrena(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
@@ -8622,7 +8622,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_07:
switch (sel) {
- case 0:
+ case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
register_name = "HWREna";
@@ -9344,7 +9344,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_07:
switch (sel) {
- case 0:
+ case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_hwrena(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 09/30] target/mips: Clean up handling of CP0 register 8
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (7 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 08/30] target/mips: Clean up handling of CP0 register 7 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 10/30] target/mips: Clean up handling of CP0 register 9 Aleksandar Markovic
` (21 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 8.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 1 +
target/mips/translate.c | 32 ++++++++++++++++----------------
2 files changed, 17 insertions(+), 16 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 74a760e..68a2104 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -335,6 +335,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG08__BADVADDR 0
#define CP0_REG08__BADINSTR 1
#define CP0_REG08__BADINSTRP 2
+#define CP0_REG08__BADINSTRX 3
/* CP0 Register 09 */
#define CP0_REG09__COUNT 0
#define CP0_REG09__SAARI 6
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 1222241..cf8be8f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7142,22 +7142,22 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_08:
switch (sel) {
- case 0:
+ case CP0_REG08__BADVADDR:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
tcg_gen_ext32s_tl(arg, arg);
register_name = "BadVAddr";
break;
- case 1:
+ case CP0_REG08__BADINSTR:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr));
register_name = "BadInstr";
break;
- case 2:
+ case CP0_REG08__BADINSTRP:
CP0_CHECK(ctx->bp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
register_name = "BadInstrP";
break;
- case 3:
+ case CP0_REG08__BADINSTRX:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
tcg_gen_andi_tl(arg, arg, ~0xffff);
@@ -7883,19 +7883,19 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_08:
switch (sel) {
- case 0:
+ case CP0_REG08__BADVADDR:
/* ignored */
register_name = "BadVAddr";
break;
- case 1:
+ case CP0_REG08__BADINSTR:
/* ignored */
register_name = "BadInstr";
break;
- case 2:
+ case CP0_REG08__BADINSTRP:
/* ignored */
register_name = "BadInstrP";
break;
- case 3:
+ case CP0_REG08__BADINSTRX:
/* ignored */
register_name = "BadInstrX";
break;
@@ -8633,21 +8633,21 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_08:
switch (sel) {
- case 0:
+ case CP0_REG08__BADVADDR:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
register_name = "BadVAddr";
break;
- case 1:
+ case CP0_REG08__BADINSTR:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr));
register_name = "BadInstr";
break;
- case 2:
+ case CP0_REG08__BADINSTRP:
CP0_CHECK(ctx->bp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
register_name = "BadInstrP";
break;
- case 3:
+ case CP0_REG08__BADINSTRX:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
tcg_gen_andi_tl(arg, arg, ~0xffff);
@@ -9356,19 +9356,19 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_08:
switch (sel) {
- case 0:
+ case CP0_REG08__BADVADDR:
/* ignored */
register_name = "BadVAddr";
break;
- case 1:
+ case CP0_REG08__BADINSTR:
/* ignored */
register_name = "BadInstr";
break;
- case 2:
+ case CP0_REG08__BADINSTRP:
/* ignored */
register_name = "BadInstrP";
break;
- case 3:
+ case CP0_REG08__BADINSTRX:
/* ignored */
register_name = "BadInstrX";
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 10/30] target/mips: Clean up handling of CP0 register 9
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (8 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 09/30] target/mips: Clean up handling of CP0 register 8 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 11/30] target/mips: Clean up handling of CP0 register 10 Aleksandar Markovic
` (20 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 9.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index cf8be8f..33a882c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6660,7 +6660,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_09:
switch (sel) {
- case 7:
+ case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
gen_helper_mfhc0_saar(arg, cpu_env);
register_name = "SAAR";
@@ -6761,7 +6761,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_09:
switch (sel) {
- case 7:
+ case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
gen_helper_mthc0_saar(cpu_env, arg);
register_name = "SAAR";
@@ -7169,7 +7169,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_09:
switch (sel) {
- case 0:
+ case CP0_REG09__COUNT:
/* Mark as an IO operation because we read the time. */
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -7187,12 +7187,12 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Count";
break;
- case 6:
+ case CP0_REG09__SAARI:
CP0_CHECK(ctx->saar);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI));
register_name = "SAARI";
break;
- case 7:
+ case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
gen_helper_mfc0_saar(arg, cpu_env);
register_name = "SAAR";
@@ -7905,16 +7905,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_09:
switch (sel) {
- case 0:
+ case CP0_REG09__COUNT:
gen_helper_mtc0_count(cpu_env, arg);
register_name = "Count";
break;
- case 6:
+ case CP0_REG09__SAARI:
CP0_CHECK(ctx->saar);
gen_helper_mtc0_saari(cpu_env, arg);
register_name = "SAARI";
break;
- case 7:
+ case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
gen_helper_mtc0_saar(cpu_env, arg);
register_name = "SAAR";
@@ -8659,7 +8659,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_09:
switch (sel) {
- case 0:
+ case CP0_REG09__COUNT:
/* Mark as an IO operation because we read the time. */
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -8677,12 +8677,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Count";
break;
- case 6:
+ case CP0_REG09__SAARI:
CP0_CHECK(ctx->saar);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI));
register_name = "SAARI";
break;
- case 7:
+ case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
gen_helper_dmfc0_saar(arg, cpu_env);
register_name = "SAAR";
@@ -9378,16 +9378,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_09:
switch (sel) {
- case 0:
+ case CP0_REG09__COUNT:
gen_helper_mtc0_count(cpu_env, arg);
register_name = "Count";
break;
- case 6:
+ case CP0_REG09__SAARI:
CP0_CHECK(ctx->saar);
gen_helper_mtc0_saari(cpu_env, arg);
register_name = "SAARI";
break;
- case 7:
+ case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
gen_helper_mtc0_saar(cpu_env, arg);
register_name = "SAAR";
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 11/30] target/mips: Clean up handling of CP0 register 10
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (9 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 10/30] target/mips: Clean up handling of CP0 register 9 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 12/30] target/mips: Clean up handling of CP0 register 11 Aleksandar Markovic
` (19 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 10.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 1 +
target/mips/translate.c | 8 ++++----
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 68a2104..42f3c77 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -344,6 +344,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG10__ENTRYHI 0
#define CP0_REG10__GUESTCTL1 4
#define CP0_REG10__GUESTCTL2 5
+#define CP0_REG10__GUESTCTL3 6
/* CP0 Register 11 */
#define CP0_REG11__COMPARE 0
#define CP0_REG11__GUESTCTL0EXT 4
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 33a882c..1a97072 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7203,7 +7203,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_10:
switch (sel) {
- case 0:
+ case CP0_REG10__ENTRYHI:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EntryHi";
@@ -7925,7 +7925,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_10:
switch (sel) {
- case 0:
+ case CP0_REG10__ENTRYHI:
gen_helper_mtc0_entryhi(cpu_env, arg);
register_name = "EntryHi";
break;
@@ -8693,7 +8693,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_10:
switch (sel) {
- case 0:
+ case CP0_REG10__ENTRYHI:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
register_name = "EntryHi";
break;
@@ -9400,7 +9400,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_10:
switch (sel) {
- case 0:
+ case CP0_REG10__ENTRYHI:
gen_helper_mtc0_entryhi(cpu_env, arg);
register_name = "EntryHi";
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 12/30] target/mips: Clean up handling of CP0 register 11
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (10 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 11/30] target/mips: Clean up handling of CP0 register 10 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 13/30] target/mips: Clean up handling of CP0 register 12 Aleksandar Markovic
` (18 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 11.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 1a97072..d92bb07 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7214,7 +7214,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_11:
switch (sel) {
- case 0:
+ case CP0_REG11__COMPARE:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
register_name = "Compare";
break;
@@ -7935,7 +7935,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_11:
switch (sel) {
- case 0:
+ case CP0_REG11__COMPARE:
gen_helper_mtc0_compare(cpu_env, arg);
register_name = "Compare";
break;
@@ -8703,7 +8703,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_11:
switch (sel) {
- case 0:
+ case CP0_REG11__COMPARE:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
register_name = "Compare";
break;
@@ -9410,7 +9410,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_11:
switch (sel) {
- case 0:
+ case CP0_REG11__COMPARE:
gen_helper_mtc0_compare(cpu_env, arg);
register_name = "Compare";
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 13/30] target/mips: Clean up handling of CP0 register 12
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (11 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 12/30] target/mips: Clean up handling of CP0 register 11 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 14/30] target/mips: Clean up handling of CP0 register 13 Aleksandar Markovic
` (17 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 12.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 3 +++
target/mips/translate.c | 32 ++++++++++++++++----------------
2 files changed, 19 insertions(+), 16 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 42f3c77..ec7285d 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -352,6 +352,9 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG12__STATUS 0
#define CP0_REG12__INTCTL 1
#define CP0_REG12__SRSCTL 2
+#define CP0_REG12__SRSMAP 3
+#define CP0_REG12__VIEW_IPL 4
+#define CP0_REG12__SRSMAP2 5
#define CP0_REG12__GUESTCTL0 6
#define CP0_REG12__GTOFFSET 7
/* CP0 Register 13 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index d92bb07..3240d25 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7225,21 +7225,21 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_12:
switch (sel) {
- case 0:
+ case CP0_REG12__STATUS:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
register_name = "Status";
break;
- case 1:
+ case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
register_name = "IntCtl";
break;
- case 2:
+ case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
register_name = "SRSCtl";
break;
- case 3:
+ case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
register_name = "SRSMap";
@@ -7946,7 +7946,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_12:
switch (sel) {
- case 0:
+ case CP0_REG12__STATUS:
save_cpu_state(ctx, 1);
gen_helper_mtc0_status(cpu_env, arg);
/* DISAS_STOP isn't good enough here, hflags may have changed. */
@@ -7954,21 +7954,21 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Status";
break;
- case 1:
+ case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_intctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "IntCtl";
break;
- case 2:
+ case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "SRSCtl";
break;
- case 3:
+ case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
@@ -8714,21 +8714,21 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_12:
switch (sel) {
- case 0:
+ case CP0_REG12__STATUS:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
register_name = "Status";
break;
- case 1:
+ case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
register_name = "IntCtl";
break;
- case 2:
+ case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
register_name = "SRSCtl";
break;
- case 3:
+ case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
register_name = "SRSMap";
@@ -9423,7 +9423,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_12:
switch (sel) {
- case 0:
+ case CP0_REG12__STATUS:
save_cpu_state(ctx, 1);
gen_helper_mtc0_status(cpu_env, arg);
/* DISAS_STOP isn't good enough here, hflags may have changed. */
@@ -9431,21 +9431,21 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Status";
break;
- case 1:
+ case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_intctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "IntCtl";
break;
- case 2:
+ case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "SRSCtl";
break;
- case 3:
+ case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 14/30] target/mips: Clean up handling of CP0 register 13
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (12 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 13/30] target/mips: Clean up handling of CP0 register 12 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 15/30] target/mips: Clean up handling of CP0 register 14 Aleksandar Markovic
` (16 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 13.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 2 ++
target/mips/translate.c | 8 ++++----
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index ec7285d..512e36e 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -359,6 +359,8 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG12__GTOFFSET 7
/* CP0 Register 13 */
#define CP0_REG13__CAUSE 0
+#define CP0_REG13__VIEW_RIPL 4
+#define CP0_REG13__NESTEDEXC 5
/* CP0 Register 14 */
#define CP0_REG14__EPC 0
/* CP0 Register 15 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 3240d25..1373447 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7250,7 +7250,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_13:
switch (sel) {
- case 0:
+ case CP0_REG13__CAUSE:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
register_name = "Cause";
break;
@@ -7981,7 +7981,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_13:
switch (sel) {
- case 0:
+ case CP0_REG13__CAUSE:
save_cpu_state(ctx, 1);
gen_helper_mtc0_cause(cpu_env, arg);
/*
@@ -8739,7 +8739,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_13:
switch (sel) {
- case 0:
+ case CP0_REG13__CAUSE:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
register_name = "Cause";
break;
@@ -9458,7 +9458,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_13:
switch (sel) {
- case 0:
+ case CP0_REG13__CAUSE:
save_cpu_state(ctx, 1);
gen_helper_mtc0_cause(cpu_env, arg);
/*
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 15/30] target/mips: Clean up handling of CP0 register 14
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (13 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 14/30] target/mips: Clean up handling of CP0 register 13 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 16/30] target/mips: Clean up handling of CP0 register 15 Aleksandar Markovic
` (15 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 14.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 1 +
target/mips/translate.c | 8 ++++----
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 512e36e..8e6376a 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -363,6 +363,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG13__NESTEDEXC 5
/* CP0 Register 14 */
#define CP0_REG14__EPC 0
+#define CP0_REG14__NESTEDEPC 2
/* CP0 Register 15 */
#define CP0_REG15__PRID 0
#define CP0_REG15__EBASE 1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 1373447..7644dda 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7260,7 +7260,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_14:
switch (sel) {
- case 0:
+ case CP0_REG14__EPC:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EPC";
@@ -7999,7 +7999,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_14:
switch (sel) {
- case 0:
+ case CP0_REG14__EPC:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
register_name = "EPC";
break;
@@ -8749,7 +8749,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_14:
switch (sel) {
- case 0:
+ case CP0_REG14__EPC:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
register_name = "EPC";
break;
@@ -9476,7 +9476,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_14:
switch (sel) {
- case 0:
+ case CP0_REG14__EPC:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
register_name = "EPC";
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 16/30] target/mips: Clean up handling of CP0 register 15
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (14 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 15/30] target/mips: Clean up handling of CP0 register 14 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 17/30] target/mips: Clean up handling of CP0 register 16 Aleksandar Markovic
` (14 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 15.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 1 +
target/mips/translate.c | 20 ++++++++++----------
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 8e6376a..f709a92 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -369,6 +369,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG15__EBASE 1
#define CP0_REG15__CDMMBASE 2
#define CP0_REG15__CMGCRBASE 3
+#define CP0_REG15__BEVVA 4
/* CP0 Register 16 */
#define CP0_REG16__CONFIG 0
#define CP0_REG16__CONFIG1 1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 7644dda..a0a2d43 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7271,17 +7271,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
- case 0:
+ case CP0_REG15__PRID:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
register_name = "PRid";
break;
- case 1:
+ case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EBase";
break;
- case 3:
+ case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS32R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
@@ -8009,11 +8009,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
- case 0:
+ case CP0_REG15__PRID:
/* ignored */
register_name = "PRid";
break;
- case 1:
+ case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase";
@@ -8759,16 +8759,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
- case 0:
+ case CP0_REG15__PRID:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
register_name = "PRid";
break;
- case 1:
+ case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
register_name = "EBase";
break;
- case 3:
+ case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS32R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
@@ -9486,11 +9486,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
- case 0:
+ case CP0_REG15__PRID:
/* ignored */
register_name = "PRid";
break;
- case 1:
+ case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase";
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 17/30] target/mips: Clean up handling of CP0 register 16
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (15 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 16/30] target/mips: Clean up handling of CP0 register 15 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 18/30] target/mips: Clean up handling of CP0 register 17 Aleksandar Markovic
` (13 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 16.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 3 ++-
target/mips/translate.c | 60 ++++++++++++++++++++++++-------------------------
2 files changed, 32 insertions(+), 31 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index f709a92..7855de8 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -377,7 +377,8 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG16__CONFIG3 3
#define CP0_REG16__CONFIG4 4
#define CP0_REG16__CONFIG5 5
-#define CP0_REG00__CONFIG7 7
+#define CP0_REG16__CONFIG6 6
+#define CP0_REG16__CONFIG7 7
/* CP0 Register 17 */
#define CP0_REG17__LLADDR 0
#define CP0_REG17__MAAR 1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a0a2d43..a3df2a5 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7294,36 +7294,36 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
- case 0:
+ case CP0_REG16__CONFIG:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
register_name = "Config";
break;
- case 1:
+ case CP0_REG16__CONFIG1:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
register_name = "Config1";
break;
- case 2:
+ case CP0_REG16__CONFIG2:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
register_name = "Config2";
break;
- case 3:
+ case CP0_REG16__CONFIG3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
register_name = "Config3";
break;
- case 4:
+ case CP0_REG16__CONFIG4:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
register_name = "Config4";
break;
- case 5:
+ case CP0_REG16__CONFIG5:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
register_name = "Config5";
break;
/* 6,7 are implementation dependent */
- case 6:
+ case CP0_REG16__CONFIG6:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
register_name = "Config6";
break;
- case 7:
+ case CP0_REG16__CONFIG7:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
register_name = "Config7";
break;
@@ -8024,45 +8024,45 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
- case 0:
+ case CP0_REG16__CONFIG:
gen_helper_mtc0_config0(cpu_env, arg);
register_name = "Config";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 1:
+ case CP0_REG16__CONFIG1:
/* ignored, read only */
register_name = "Config1";
break;
- case 2:
+ case CP0_REG16__CONFIG2:
gen_helper_mtc0_config2(cpu_env, arg);
register_name = "Config2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 3:
+ case CP0_REG16__CONFIG3:
gen_helper_mtc0_config3(cpu_env, arg);
register_name = "Config3";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 4:
+ case CP0_REG16__CONFIG4:
gen_helper_mtc0_config4(cpu_env, arg);
register_name = "Config4";
ctx->base.is_jmp = DISAS_STOP;
break;
- case 5:
+ case CP0_REG16__CONFIG5:
gen_helper_mtc0_config5(cpu_env, arg);
register_name = "Config5";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
/* 6,7 are implementation dependent */
- case 6:
+ case CP0_REG16__CONFIG6:
/* ignored */
register_name = "Config6";
break;
- case 7:
+ case CP0_REG16__CONFIG7:
/* ignored */
register_name = "Config7";
break;
@@ -8780,36 +8780,36 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
- case 0:
+ case CP0_REG16__CONFIG:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
register_name = "Config";
break;
- case 1:
+ case CP0_REG16__CONFIG1:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
register_name = "Config1";
break;
- case 2:
+ case CP0_REG16__CONFIG2:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
register_name = "Config2";
break;
- case 3:
+ case CP0_REG16__CONFIG3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
register_name = "Config3";
break;
- case 4:
+ case CP0_REG16__CONFIG4:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
register_name = "Config4";
break;
- case 5:
+ case CP0_REG16__CONFIG5:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
register_name = "Config5";
break;
/* 6,7 are implementation dependent */
- case 6:
+ case CP0_REG16__CONFIG6:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
register_name = "Config6";
break;
- case 7:
+ case CP0_REG16__CONFIG7:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
register_name = "Config7";
break;
@@ -9501,33 +9501,33 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
- case 0:
+ case CP0_REG16__CONFIG:
gen_helper_mtc0_config0(cpu_env, arg);
register_name = "Config";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 1:
+ case CP0_REG16__CONFIG1:
/* ignored, read only */
register_name = "Config1";
break;
- case 2:
+ case CP0_REG16__CONFIG2:
gen_helper_mtc0_config2(cpu_env, arg);
register_name = "Config2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 3:
+ case CP0_REG16__CONFIG3:
gen_helper_mtc0_config3(cpu_env, arg);
register_name = "Config3";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 4:
+ case CP0_REG16__CONFIG4:
/* currently ignored */
register_name = "Config4";
break;
- case 5:
+ case CP0_REG16__CONFIG5:
gen_helper_mtc0_config5(cpu_env, arg);
register_name = "Config5";
/* Stop translation as we may have switched the execution mode */
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 18/30] target/mips: Clean up handling of CP0 register 17
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (16 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 17/30] target/mips: Clean up handling of CP0 register 16 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 19/30] target/mips: Clean up handling of CP0 register 18 Aleksandar Markovic
` (12 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 17.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a3df2a5..6842531 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6671,12 +6671,12 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_LLAddr),
ctx->CP0_LLAddr_shift);
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mfhc0_maar(arg, cpu_env);
register_name = "MAAR";
@@ -6772,7 +6772,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
/*
* LLAddr is read-only (the only exception is bit 0 if LLB is
* supported); the CP0_LLAddr_rw_bitmask does not seem to be
@@ -6781,7 +6781,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
*/
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mthc0_maar(cpu_env, arg);
register_name = "MAAR";
@@ -7333,16 +7333,16 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
gen_helper_mfc0_lladdr(arg, cpu_env);
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mfc0_maar(arg, cpu_env);
register_name = "MAAR";
break;
- case 2:
+ case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
register_name = "MAARI";
@@ -8073,16 +8073,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
gen_helper_mtc0_lladdr(cpu_env, arg);
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maar(cpu_env, arg);
register_name = "MAAR";
break;
- case 2:
+ case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maari(cpu_env, arg);
register_name = "MAARI";
@@ -8819,16 +8819,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
gen_helper_dmfc0_lladdr(arg, cpu_env);
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_dmfc0_maar(arg, cpu_env);
register_name = "MAAR";
break;
- case 2:
+ case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
register_name = "MAARI";
@@ -9541,16 +9541,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
gen_helper_mtc0_lladdr(cpu_env, arg);
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maar(cpu_env, arg);
register_name = "MAAR";
break;
- case 2:
+ case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maari(cpu_env, arg);
register_name = "MAARI";
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 19/30] target/mips: Clean up handling of CP0 register 18
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (17 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 18/30] target/mips: Clean up handling of CP0 register 17 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 20/30] target/mips: Clean up handling of CP0 register 19 Aleksandar Markovic
` (11 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 18.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 20 +++++++++-------
target/mips/translate.c | 64 ++++++++++++++++++++++++-------------------------
2 files changed, 44 insertions(+), 40 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 7855de8..6881e96 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -194,14 +194,14 @@ typedef struct mips_def_t mips_def_t;
* Register 16 Register 17 Register 18 Register 19
* ----------- ----------- ----------- -----------
*
- * 0 Config LLAddr WatchLo WatchHi
- * 1 Config1 MAAR WatchLo WatchHi
- * 2 Config2 MAARI WatchLo WatchHi
- * 3 Config3 WatchLo WatchHi
- * 4 Config4 WatchLo WatchHi
- * 5 Config5 WatchLo WatchHi
- * 6 WatchLo WatchHi
- * 7 WatchLo WatchHi
+ * 0 Config LLAddr WatchLo0 WatchHi
+ * 1 Config1 MAAR WatchLo1 WatchHi
+ * 2 Config2 MAARI WatchLo2 WatchHi
+ * 3 Config3 WatchLo3 WatchHi
+ * 4 Config4 WatchLo4 WatchHi
+ * 5 Config5 WatchLo5 WatchHi
+ * 6 WatchLo6 WatchHi
+ * 7 WatchLo7 WatchHi
*
*
* Register 20 Register 21 Register 22 Register 23
@@ -388,6 +388,10 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG18__WATCHLO1 1
#define CP0_REG18__WATCHLO2 2
#define CP0_REG18__WATCHLO3 3
+#define CP0_REG18__WATCHLO4 4
+#define CP0_REG18__WATCHLO5 5
+#define CP0_REG18__WATCHLO6 6
+#define CP0_REG18__WATCHLO7 7
/* CP0 Register 19 */
#define CP0_REG19__WATCHHI0 0
#define CP0_REG19__WATCHHI1 1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 6842531..adc1049 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7353,14 +7353,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG18__WATCHLO0:
+ case CP0_REG18__WATCHLO1:
+ case CP0_REG18__WATCHLO2:
+ case CP0_REG18__WATCHLO3:
+ case CP0_REG18__WATCHLO4:
+ case CP0_REG18__WATCHLO5:
+ case CP0_REG18__WATCHLO6:
+ case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchlo, arg, sel);
register_name = "WatchLo";
@@ -8093,14 +8093,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG18__WATCHLO0:
+ case CP0_REG18__WATCHLO1:
+ case CP0_REG18__WATCHLO2:
+ case CP0_REG18__WATCHLO3:
+ case CP0_REG18__WATCHLO4:
+ case CP0_REG18__WATCHLO5:
+ case CP0_REG18__WATCHLO6:
+ case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchlo, arg, sel);
register_name = "WatchLo";
@@ -8839,14 +8839,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG18__WATCHLO0:
+ case CP0_REG18__WATCHLO1:
+ case CP0_REG18__WATCHLO2:
+ case CP0_REG18__WATCHLO3:
+ case CP0_REG18__WATCHLO4:
+ case CP0_REG18__WATCHLO5:
+ case CP0_REG18__WATCHLO6:
+ case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(dmfc0_watchlo, arg, sel);
register_name = "WatchLo";
@@ -9561,14 +9561,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG18__WATCHLO0:
+ case CP0_REG18__WATCHLO1:
+ case CP0_REG18__WATCHLO2:
+ case CP0_REG18__WATCHLO3:
+ case CP0_REG18__WATCHLO4:
+ case CP0_REG18__WATCHLO5:
+ case CP0_REG18__WATCHLO6:
+ case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchlo, arg, sel);
register_name = "WatchLo";
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 20/30] target/mips: Clean up handling of CP0 register 19
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (18 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 19/30] target/mips: Clean up handling of CP0 register 18 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 21/30] target/mips: Clean up handling of CP0 register 20 Aleksandar Markovic
` (10 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 19.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 4 ++++
target/mips/translate.c | 64 ++++++++++++++++++++++++-------------------------
2 files changed, 36 insertions(+), 32 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 6881e96..f809759 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -397,6 +397,10 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG19__WATCHHI1 1
#define CP0_REG19__WATCHHI2 2
#define CP0_REG19__WATCHHI3 3
+#define CP0_REG19__WATCHHI4 4
+#define CP0_REG19__WATCHHI5 5
+#define CP0_REG19__WATCHHI6 6
+#define CP0_REG19__WATCHHI7 7
/* CP0 Register 20 */
#define CP0_REG20__XCONTEXT 0
/* CP0 Register 21 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index adc1049..20c90a7 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7371,14 +7371,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_19:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG19__WATCHHI0:
+ case CP0_REG19__WATCHHI1:
+ case CP0_REG19__WATCHHI2:
+ case CP0_REG19__WATCHHI3:
+ case CP0_REG19__WATCHHI4:
+ case CP0_REG19__WATCHHI5:
+ case CP0_REG19__WATCHHI6:
+ case CP0_REG19__WATCHHI7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchhi, arg, sel);
register_name = "WatchHi";
@@ -8111,14 +8111,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_19:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG19__WATCHHI0:
+ case CP0_REG19__WATCHHI1:
+ case CP0_REG19__WATCHHI2:
+ case CP0_REG19__WATCHHI3:
+ case CP0_REG19__WATCHHI4:
+ case CP0_REG19__WATCHHI5:
+ case CP0_REG19__WATCHHI6:
+ case CP0_REG19__WATCHHI7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchhi, arg, sel);
register_name = "WatchHi";
@@ -8857,14 +8857,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_19:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG19__WATCHHI0:
+ case CP0_REG19__WATCHHI1:
+ case CP0_REG19__WATCHHI2:
+ case CP0_REG19__WATCHHI3:
+ case CP0_REG19__WATCHHI4:
+ case CP0_REG19__WATCHHI5:
+ case CP0_REG19__WATCHHI6:
+ case CP0_REG19__WATCHHI7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(dmfc0_watchhi, arg, sel);
register_name = "WatchHi";
@@ -9579,14 +9579,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_19:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG19__WATCHHI0:
+ case CP0_REG19__WATCHHI1:
+ case CP0_REG19__WATCHHI2:
+ case CP0_REG19__WATCHHI3:
+ case CP0_REG19__WATCHHI4:
+ case CP0_REG19__WATCHHI5:
+ case CP0_REG19__WATCHHI6:
+ case CP0_REG19__WATCHHI7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchhi, arg, sel);
register_name = "WatchHi";
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 21/30] target/mips: Clean up handling of CP0 register 20
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (19 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 20/30] target/mips: Clean up handling of CP0 register 19 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 22/30] target/mips: Clean up handling of CP0 register 23 Aleksandar Markovic
` (9 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 20.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 20c90a7..8c560d8 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7389,7 +7389,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_20:
switch (sel) {
- case 0:
+ case CP0_REG20__XCONTEXT:
#if defined(TARGET_MIPS64)
check_insn(ctx, ISA_MIPS3);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
@@ -8129,7 +8129,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_20:
switch (sel) {
- case 0:
+ case CP0_REG20__XCONTEXT:
#if defined(TARGET_MIPS64)
check_insn(ctx, ISA_MIPS3);
gen_helper_mtc0_xcontext(cpu_env, arg);
@@ -8875,7 +8875,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_20:
switch (sel) {
- case 0:
+ case CP0_REG20__XCONTEXT:
check_insn(ctx, ISA_MIPS3);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
register_name = "XContext";
@@ -9597,7 +9597,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_20:
switch (sel) {
- case 0:
+ case CP0_REG20__XCONTEXT:
check_insn(ctx, ISA_MIPS3);
gen_helper_mtc0_xcontext(cpu_env, arg);
register_name = "XContext";
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 22/30] target/mips: Clean up handling of CP0 register 23
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (20 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 21/30] target/mips: Clean up handling of CP0 register 20 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 23/30] target/mips: Clean up handling of CP0 register 24 Aleksandar Markovic
` (8 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 23.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 6 +++
target/mips/translate.c | 126 +++++++++++++++++++++++++++++++-----------------
2 files changed, 89 insertions(+), 43 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index f809759..19a1b78 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -407,6 +407,12 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 22 */
/* CP0 Register 23 */
#define CP0_REG23__DEBUG 0
+#define CP0_REG23__TRACECONTROL 1
+#define CP0_REG23__TRACECONTROL2 2
+#define CP0_REG23__USERTRACEDATA1 3
+#define CP0_REG23__TRACEIBPC 4
+#define CP0_REG23__TRACEDBPC 5
+#define CP0_REG23__DEBUG2 6
/* CP0 Register 24 */
#define CP0_REG24__DEPC 0
/* CP0 Register 25 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 8c560d8..0605721 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7419,25 +7419,34 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_23:
switch (sel) {
- case 0:
+ case CP0_REG23__DEBUG:
gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
register_name = "Debug";
break;
- case 1:
-// gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
+ case CP0_REG23__TRACECONTROL:
+ /* PDtrace support */
+ /* gen_helper_mfc0_tracecontrol(arg); */
register_name = "TraceControl";
goto cp0_unimplemented;
- case 2:
-// gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
+ case CP0_REG23__TRACECONTROL2:
+ /* PDtrace support */
+ /* gen_helper_mfc0_tracecontrol2(arg); */
register_name = "TraceControl2";
goto cp0_unimplemented;
- case 3:
-// gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
- register_name = "UserTraceData";
+ case CP0_REG23__USERTRACEDATA1:
+ /* PDtrace support */
+ /* gen_helper_mfc0_usertracedata1(arg);*/
+ register_name = "UserTraceData1";
goto cp0_unimplemented;
- case 4:
-// gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
- register_name = "TraceBPC";
+ case CP0_REG23__TRACEIBPC:
+ /* PDtrace support */
+ /* gen_helper_mfc0_traceibpc(arg); */
+ register_name = "TraceIBPC";
+ goto cp0_unimplemented;
+ case CP0_REG23__TRACEDBPC:
+ /* PDtrace support */
+ /* gen_helper_mfc0_tracedbpc(arg); */
+ register_name = "TraceDBPC";
goto cp0_unimplemented;
default:
goto cp0_unimplemented;
@@ -8158,38 +8167,49 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_23:
switch (sel) {
- case 0:
+ case CP0_REG23__DEBUG:
gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
/* DISAS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Debug";
break;
- case 1:
-// gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
+ case CP0_REG23__TRACECONTROL:
+ /* PDtrace support */
+ /* gen_helper_mtc0_tracecontrol(cpu_env, arg); */
register_name = "TraceControl";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
goto cp0_unimplemented;
- case 2:
-// gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
+ case CP0_REG23__TRACECONTROL2:
+ /* PDtrace support */
+ /* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */
register_name = "TraceControl2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
goto cp0_unimplemented;
- case 3:
+ case CP0_REG23__USERTRACEDATA1:
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
-// gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
+ /* PDtrace support */
+ /* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/
register_name = "UserTraceData";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
goto cp0_unimplemented;
- case 4:
-// gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
+ case CP0_REG23__TRACEIBPC:
+ /* PDtrace support */
+ /* gen_helper_mtc0_traceibpc(cpu_env, arg); */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
- register_name = "TraceBPC";
+ register_name = "TraceIBPC";
+ goto cp0_unimplemented;
+ case CP0_REG23__TRACEDBPC:
+ /* PDtrace support */
+ /* gen_helper_mtc0_tracedbpc(cpu_env, arg); */
+ /* Stop translation as we may have switched the execution mode */
+ ctx->base.is_jmp = DISAS_STOP;
+ register_name = "TraceDBPC";
goto cp0_unimplemented;
default:
goto cp0_unimplemented;
@@ -8902,25 +8922,34 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_23:
switch (sel) {
- case 0:
+ case CP0_REG23__DEBUG:
gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
register_name = "Debug";
break;
- case 1:
-// gen_helper_dmfc0_tracecontrol(arg, cpu_env); /* PDtrace support */
+ case CP0_REG23__TRACECONTROL:
+ /* PDtrace support */
+ /* gen_helper_dmfc0_tracecontrol(arg, cpu_env); */
register_name = "TraceControl";
goto cp0_unimplemented;
- case 2:
-// gen_helper_dmfc0_tracecontrol2(arg, cpu_env); /* PDtrace support */
+ case CP0_REG23__TRACECONTROL2:
+ /* PDtrace support */
+ /* gen_helper_dmfc0_tracecontrol2(arg, cpu_env); */
register_name = "TraceControl2";
goto cp0_unimplemented;
- case 3:
-// gen_helper_dmfc0_usertracedata(arg, cpu_env); /* PDtrace support */
- register_name = "UserTraceData";
+ case CP0_REG23__USERTRACEDATA1:
+ /* PDtrace support */
+ /* gen_helper_dmfc0_usertracedata1(arg, cpu_env);*/
+ register_name = "UserTraceData1";
goto cp0_unimplemented;
- case 4:
-// gen_helper_dmfc0_tracebpc(arg, cpu_env); /* PDtrace support */
- register_name = "TraceBPC";
+ case CP0_REG23__TRACEIBPC:
+ /* PDtrace support */
+ /* gen_helper_dmfc0_traceibpc(arg, cpu_env); */
+ register_name = "TraceIBPC";
+ goto cp0_unimplemented;
+ case CP0_REG23__TRACEDBPC:
+ /* PDtrace support */
+ /* gen_helper_dmfc0_tracedbpc(arg, cpu_env); */
+ register_name = "TraceDBPC";
goto cp0_unimplemented;
default:
goto cp0_unimplemented;
@@ -9624,36 +9653,47 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_23:
switch (sel) {
- case 0:
+ case CP0_REG23__DEBUG:
gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
/* DISAS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Debug";
break;
- case 1:
-// gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
+ case CP0_REG23__TRACECONTROL:
+ /* PDtrace support */
+ /* gen_helper_mtc0_tracecontrol(cpu_env, arg); */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "TraceControl";
goto cp0_unimplemented;
- case 2:
-// gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
+ case CP0_REG23__TRACECONTROL2:
+ /* PDtrace support */
+ /* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "TraceControl2";
goto cp0_unimplemented;
- case 3:
-// gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
+ case CP0_REG23__USERTRACEDATA1:
+ /* PDtrace support */
+ /* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
- register_name = "UserTraceData";
+ register_name = "UserTraceData1";
goto cp0_unimplemented;
- case 4:
-// gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
+ case CP0_REG23__TRACEIBPC:
+ /* PDtrace support */
+ /* gen_helper_mtc0_traceibpc(cpu_env, arg); */
+ /* Stop translation as we may have switched the execution mode */
+ ctx->base.is_jmp = DISAS_STOP;
+ register_name = "TraceIBPC";
+ goto cp0_unimplemented;
+ case CP0_REG23__TRACEDBPC:
+ /* PDtrace support */
+ /* gen_helper_mtc0_tracedbpc(cpu_env, arg); */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
- register_name = "TraceBPC";
+ register_name = "TraceDBPC";
goto cp0_unimplemented;
default:
goto cp0_unimplemented;
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 23/30] target/mips: Clean up handling of CP0 register 24
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (21 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 22/30] target/mips: Clean up handling of CP0 register 23 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 24/30] target/mips: Clean up handling of CP0 register 25 Aleksandar Markovic
` (7 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 24.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 0605721..732b38d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7454,7 +7454,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_24:
switch (sel) {
- case 0:
+ case CP0_REG24__DEPC:
/* EJTAG support */
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
tcg_gen_ext32s_tl(arg, arg);
@@ -8217,7 +8217,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_24:
switch (sel) {
- case 0:
+ case CP0_REG24__DEPC:
/* EJTAG support */
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
register_name = "DEPC";
@@ -8957,7 +8957,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_24:
switch (sel) {
- case 0:
+ case CP0_REG24__DEPC:
/* EJTAG support */
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
register_name = "DEPC";
@@ -9701,7 +9701,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_24:
switch (sel) {
- case 0:
+ case CP0_REG24__DEPC:
/* EJTAG support */
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
register_name = "DEPC";
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 24/30] target/mips: Clean up handling of CP0 register 25
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (22 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 23/30] target/mips: Clean up handling of CP0 register 24 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 25/30] target/mips: Clean up handling of CP0 register 26 Aleksandar Markovic
` (6 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 25.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 64 ++++++++++++++++++++++++-------------------------
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 732b38d..df6aa9e 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7466,35 +7466,35 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_25:
switch (sel) {
- case 0:
+ case CP0_REG25__PERFCTL0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
register_name = "Performance0";
break;
- case 1:
+ case CP0_REG25__PERFCNT0:
/* gen_helper_mfc0_performance1(arg); */
register_name = "Performance1";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG25__PERFCTL1:
/* gen_helper_mfc0_performance2(arg); */
register_name = "Performance2";
goto cp0_unimplemented;
- case 3:
+ case CP0_REG25__PERFCNT1:
/* gen_helper_mfc0_performance3(arg); */
register_name = "Performance3";
goto cp0_unimplemented;
- case 4:
+ case CP0_REG25__PERFCTL2:
/* gen_helper_mfc0_performance4(arg); */
register_name = "Performance4";
goto cp0_unimplemented;
- case 5:
+ case CP0_REG25__PERFCNT2:
/* gen_helper_mfc0_performance5(arg); */
register_name = "Performance5";
goto cp0_unimplemented;
- case 6:
+ case CP0_REG25__PERFCTL3:
/* gen_helper_mfc0_performance6(arg); */
register_name = "Performance6";
goto cp0_unimplemented;
- case 7:
+ case CP0_REG25__PERFCNT3:
/* gen_helper_mfc0_performance7(arg); */
register_name = "Performance7";
goto cp0_unimplemented;
@@ -8228,35 +8228,35 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_25:
switch (sel) {
- case 0:
+ case CP0_REG25__PERFCTL0:
gen_helper_mtc0_performance0(cpu_env, arg);
register_name = "Performance0";
break;
- case 1:
+ case CP0_REG25__PERFCNT0:
/* gen_helper_mtc0_performance1(arg); */
register_name = "Performance1";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG25__PERFCTL1:
/* gen_helper_mtc0_performance2(arg); */
register_name = "Performance2";
goto cp0_unimplemented;
- case 3:
+ case CP0_REG25__PERFCNT1:
/* gen_helper_mtc0_performance3(arg); */
register_name = "Performance3";
goto cp0_unimplemented;
- case 4:
+ case CP0_REG25__PERFCTL2:
/* gen_helper_mtc0_performance4(arg); */
register_name = "Performance4";
goto cp0_unimplemented;
- case 5:
+ case CP0_REG25__PERFCNT2:
/* gen_helper_mtc0_performance5(arg); */
register_name = "Performance5";
goto cp0_unimplemented;
- case 6:
+ case CP0_REG25__PERFCTL3:
/* gen_helper_mtc0_performance6(arg); */
register_name = "Performance6";
goto cp0_unimplemented;
- case 7:
+ case CP0_REG25__PERFCNT3:
/* gen_helper_mtc0_performance7(arg); */
register_name = "Performance7";
goto cp0_unimplemented;
@@ -8968,35 +8968,35 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_25:
switch (sel) {
- case 0:
+ case CP0_REG25__PERFCTL0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
register_name = "Performance0";
break;
- case 1:
+ case CP0_REG25__PERFCNT0:
/* gen_helper_dmfc0_performance1(arg); */
register_name = "Performance1";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG25__PERFCTL1:
/* gen_helper_dmfc0_performance2(arg); */
register_name = "Performance2";
goto cp0_unimplemented;
- case 3:
+ case CP0_REG25__PERFCNT1:
/* gen_helper_dmfc0_performance3(arg); */
register_name = "Performance3";
goto cp0_unimplemented;
- case 4:
+ case CP0_REG25__PERFCTL2:
/* gen_helper_dmfc0_performance4(arg); */
register_name = "Performance4";
goto cp0_unimplemented;
- case 5:
+ case CP0_REG25__PERFCNT2:
/* gen_helper_dmfc0_performance5(arg); */
register_name = "Performance5";
goto cp0_unimplemented;
- case 6:
+ case CP0_REG25__PERFCTL3:
/* gen_helper_dmfc0_performance6(arg); */
register_name = "Performance6";
goto cp0_unimplemented;
- case 7:
+ case CP0_REG25__PERFCNT3:
/* gen_helper_dmfc0_performance7(arg); */
register_name = "Performance7";
goto cp0_unimplemented;
@@ -9712,35 +9712,35 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_25:
switch (sel) {
- case 0:
+ case CP0_REG25__PERFCTL0:
gen_helper_mtc0_performance0(cpu_env, arg);
register_name = "Performance0";
break;
- case 1:
+ case CP0_REG25__PERFCNT0:
/* gen_helper_mtc0_performance1(cpu_env, arg); */
register_name = "Performance1";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG25__PERFCTL1:
/* gen_helper_mtc0_performance2(cpu_env, arg); */
register_name = "Performance2";
goto cp0_unimplemented;
- case 3:
+ case CP0_REG25__PERFCNT1:
/* gen_helper_mtc0_performance3(cpu_env, arg); */
register_name = "Performance3";
goto cp0_unimplemented;
- case 4:
+ case CP0_REG25__PERFCTL2:
/* gen_helper_mtc0_performance4(cpu_env, arg); */
register_name = "Performance4";
goto cp0_unimplemented;
- case 5:
+ case CP0_REG25__PERFCNT2:
/* gen_helper_mtc0_performance5(cpu_env, arg); */
register_name = "Performance5";
goto cp0_unimplemented;
- case 6:
+ case CP0_REG25__PERFCTL3:
/* gen_helper_mtc0_performance6(cpu_env, arg); */
register_name = "Performance6";
goto cp0_unimplemented;
- case 7:
+ case CP0_REG25__PERFCNT3:
/* gen_helper_mtc0_performance7(cpu_env, arg); */
register_name = "Performance7";
goto cp0_unimplemented;
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 25/30] target/mips: Clean up handling of CP0 register 26
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (23 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 24/30] target/mips: Clean up handling of CP0 register 25 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 26/30] target/mips: Clean up handling of CP0 register 27 Aleksandar Markovic
` (5 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 26.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 2 +-
target/mips/translate.c | 8 ++++----
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 19a1b78..9b15b09 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -425,7 +425,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG25__PERFCTL3 6
#define CP0_REG25__PERFCNT3 7
/* CP0 Register 26 */
-#define CP0_REG00__ERRCTL 0
+#define CP0_REG26__ERRCTL 0
/* CP0 Register 27 */
#define CP0_REG27__CACHERR 0
/* CP0 Register 28 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index df6aa9e..d7776fa 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7504,7 +7504,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_26:
switch (sel) {
- case 0:
+ case CP0_REG26__ERRCTL:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
register_name = "ErrCtl";
break;
@@ -8266,7 +8266,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_26:
switch (sel) {
- case 0:
+ case CP0_REG26__ERRCTL:
gen_helper_mtc0_errctl(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
register_name = "ErrCtl";
@@ -9006,7 +9006,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_26:
switch (sel) {
- case 0:
+ case CP0_REG26__ERRCTL:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
register_name = "ErrCtl";
break;
@@ -9750,7 +9750,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_26:
switch (sel) {
- case 0:
+ case CP0_REG26__ERRCTL:
gen_helper_mtc0_errctl(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
register_name = "ErrCtl";
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 26/30] target/mips: Clean up handling of CP0 register 27
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (24 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 25/30] target/mips: Clean up handling of CP0 register 26 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 27/30] target/mips: Clean up handling of CP0 register 28 Aleksandar Markovic
` (4 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 27.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 20 ++++----------------
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index d7776fa..2e5df0b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7514,10 +7514,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_27:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
+ case CP0_REG27__CACHERR:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
register_name = "CacheErr";
break;
@@ -8277,10 +8274,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_27:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
+ case CP0_REG27__CACHERR:
/* ignored */
register_name = "CacheErr";
break;
@@ -9017,10 +9011,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_27:
switch (sel) {
/* ignored */
- case 0:
- case 1:
- case 2:
- case 3:
+ case CP0_REG27__CACHERR:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
register_name = "CacheErr";
break;
@@ -9761,10 +9752,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_27:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
+ case CP0_REG27__CACHERR:
/* ignored */
register_name = "CacheErr";
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 27/30] target/mips: Clean up handling of CP0 register 28
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (25 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 26/30] target/mips: Clean up handling of CP0 register 27 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 28/30] target/mips: Clean up handling of CP0 register 29 Aleksandar Markovic
` (3 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 28.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 24 +++++++++++--------
target/mips/translate.c | 64 ++++++++++++++++++++++++-------------------------
2 files changed, 46 insertions(+), 42 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 9b15b09..b71b6f4 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -235,12 +235,12 @@ typedef struct mips_def_t mips_def_t;
*
* 0 DataLo DataHi ErrorEPC DESAVE
* 1 TagLo TagHi
- * 2 DataLo DataHi KScratch<n>
- * 3 TagLo TagHi KScratch<n>
- * 4 DataLo DataHi KScratch<n>
- * 5 TagLo TagHi KScratch<n>
- * 6 DataLo DataHi KScratch<n>
- * 7 TagLo TagHi KScratch<n>
+ * 2 DataLo1 DataHi KScratch<n>
+ * 3 TagLo1 TagHi KScratch<n>
+ * 4 DataLo2 DataHi KScratch<n>
+ * 5 TagLo2 TagHi KScratch<n>
+ * 6 DataLo3 DataHi KScratch<n>
+ * 7 TagLo3 TagHi KScratch<n>
*
*/
#define CP0_REGISTER_00 0
@@ -429,10 +429,14 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 27 */
#define CP0_REG27__CACHERR 0
/* CP0 Register 28 */
-#define CP0_REG28__ITAGLO 0
-#define CP0_REG28__IDATALO 1
-#define CP0_REG28__DTAGLO 2
-#define CP0_REG28__DDATALO 3
+#define CP0_REG28__TAGLO 0
+#define CP0_REG28__DATALO 1
+#define CP0_REG28__TAGLO1 2
+#define CP0_REG28__DATALO1 3
+#define CP0_REG28__TAGLO2 4
+#define CP0_REG28__DATALO2 5
+#define CP0_REG28__TAGLO3 6
+#define CP0_REG28__DATALO3 7
/* CP0 Register 29 */
#define CP0_REG29__IDATAHI 1
#define CP0_REG29__DDATAHI 3
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 2e5df0b..807151b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7524,10 +7524,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_28:
switch (sel) {
- case 0:
- case 2:
- case 4:
- case 6:
+ case CP0_REG28__TAGLO:
+ case CP0_REG28__TAGLO1:
+ case CP0_REG28__TAGLO2:
+ case CP0_REG28__TAGLO3:
{
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUMIPSState, CP0_TagLo));
@@ -7536,10 +7536,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
}
register_name = "TagLo";
break;
- case 1:
- case 3:
- case 5:
- case 7:
+ case CP0_REG28__DATALO:
+ case CP0_REG28__DATALO1:
+ case CP0_REG28__DATALO2:
+ case CP0_REG28__DATALO3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
register_name = "DataLo";
break;
@@ -8284,17 +8284,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_28:
switch (sel) {
- case 0:
- case 2:
- case 4:
- case 6:
+ case CP0_REG28__TAGLO:
+ case CP0_REG28__TAGLO1:
+ case CP0_REG28__TAGLO2:
+ case CP0_REG28__TAGLO3:
gen_helper_mtc0_taglo(cpu_env, arg);
register_name = "TagLo";
break;
- case 1:
- case 3:
- case 5:
- case 7:
+ case CP0_REG28__DATALO:
+ case CP0_REG28__DATALO1:
+ case CP0_REG28__DATALO2:
+ case CP0_REG28__DATALO3:
gen_helper_mtc0_datalo(cpu_env, arg);
register_name = "DataLo";
break;
@@ -9021,17 +9021,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_28:
switch (sel) {
- case 0:
- case 2:
- case 4:
- case 6:
+ case CP0_REG28__TAGLO:
+ case CP0_REG28__TAGLO1:
+ case CP0_REG28__TAGLO2:
+ case CP0_REG28__TAGLO3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagLo));
register_name = "TagLo";
break;
- case 1:
- case 3:
- case 5:
- case 7:
+ case CP0_REG28__DATALO:
+ case CP0_REG28__DATALO1:
+ case CP0_REG28__DATALO2:
+ case CP0_REG28__DATALO3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
register_name = "DataLo";
break;
@@ -9762,17 +9762,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_28:
switch (sel) {
- case 0:
- case 2:
- case 4:
- case 6:
+ case CP0_REG28__TAGLO:
+ case CP0_REG28__TAGLO1:
+ case CP0_REG28__TAGLO2:
+ case CP0_REG28__TAGLO3:
gen_helper_mtc0_taglo(cpu_env, arg);
register_name = "TagLo";
break;
- case 1:
- case 3:
- case 5:
- case 7:
+ case CP0_REG28__DATALO:
+ case CP0_REG28__DATALO1:
+ case CP0_REG28__DATALO2:
+ case CP0_REG28__DATALO3:
gen_helper_mtc0_datalo(cpu_env, arg);
register_name = "DataLo";
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 28/30] target/mips: Clean up handling of CP0 register 29
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (26 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 27/30] target/mips: Clean up handling of CP0 register 28 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 29/30] target/mips: Clean up handling of CP0 register 30 Aleksandar Markovic
` (2 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 29.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 22 ++++++++++-------
target/mips/translate.c | 64 ++++++++++++++++++++++++-------------------------
2 files changed, 46 insertions(+), 40 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index b71b6f4..d309ad8 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -235,12 +235,12 @@ typedef struct mips_def_t mips_def_t;
*
* 0 DataLo DataHi ErrorEPC DESAVE
* 1 TagLo TagHi
- * 2 DataLo1 DataHi KScratch<n>
- * 3 TagLo1 TagHi KScratch<n>
- * 4 DataLo2 DataHi KScratch<n>
- * 5 TagLo2 TagHi KScratch<n>
- * 6 DataLo3 DataHi KScratch<n>
- * 7 TagLo3 TagHi KScratch<n>
+ * 2 DataLo1 DataHi1 KScratch<n>
+ * 3 TagLo1 TagHi1 KScratch<n>
+ * 4 DataLo2 DataHi2 KScratch<n>
+ * 5 TagLo2 TagHi2 KScratch<n>
+ * 6 DataLo3 DataHi3 KScratch<n>
+ * 7 TagLo3 TagHi3 KScratch<n>
*
*/
#define CP0_REGISTER_00 0
@@ -438,8 +438,14 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG28__TAGLO3 6
#define CP0_REG28__DATALO3 7
/* CP0 Register 29 */
-#define CP0_REG29__IDATAHI 1
-#define CP0_REG29__DDATAHI 3
+#define CP0_REG29__TAGHI 0
+#define CP0_REG29__DATAHI 1
+#define CP0_REG29__TAGHI1 2
+#define CP0_REG29__DATAHI1 3
+#define CP0_REG29__TAGHI2 4
+#define CP0_REG29__DATAHI2 5
+#define CP0_REG29__TAGHI3 6
+#define CP0_REG29__DATAHI3 7
/* CP0 Register 30 */
#define CP0_REG30__ERROREPC 0
/* CP0 Register 31 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 807151b..2cb132a 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7549,17 +7549,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_29:
switch (sel) {
- case 0:
- case 2:
- case 4:
- case 6:
+ case CP0_REG29__TAGHI:
+ case CP0_REG29__TAGHI1:
+ case CP0_REG29__TAGHI2:
+ case CP0_REG29__TAGHI3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
register_name = "TagHi";
break;
- case 1:
- case 3:
- case 5:
- case 7:
+ case CP0_REG29__DATAHI:
+ case CP0_REG29__DATAHI1:
+ case CP0_REG29__DATAHI2:
+ case CP0_REG29__DATAHI3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
register_name = "DataHi";
break;
@@ -8304,17 +8304,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_29:
switch (sel) {
- case 0:
- case 2:
- case 4:
- case 6:
+ case CP0_REG29__TAGHI:
+ case CP0_REG29__TAGHI1:
+ case CP0_REG29__TAGHI2:
+ case CP0_REG29__TAGHI3:
gen_helper_mtc0_taghi(cpu_env, arg);
register_name = "TagHi";
break;
- case 1:
- case 3:
- case 5:
- case 7:
+ case CP0_REG29__DATAHI:
+ case CP0_REG29__DATAHI1:
+ case CP0_REG29__DATAHI2:
+ case CP0_REG29__DATAHI3:
gen_helper_mtc0_datahi(cpu_env, arg);
register_name = "DataHi";
break;
@@ -9041,17 +9041,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_29:
switch (sel) {
- case 0:
- case 2:
- case 4:
- case 6:
+ case CP0_REG29__TAGHI:
+ case CP0_REG29__TAGHI1:
+ case CP0_REG29__TAGHI2:
+ case CP0_REG29__TAGHI3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
register_name = "TagHi";
break;
- case 1:
- case 3:
- case 5:
- case 7:
+ case CP0_REG29__DATAHI:
+ case CP0_REG29__DATAHI1:
+ case CP0_REG29__DATAHI2:
+ case CP0_REG29__DATAHI3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
register_name = "DataHi";
break;
@@ -9782,17 +9782,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_29:
switch (sel) {
- case 0:
- case 2:
- case 4:
- case 6:
+ case CP0_REG29__TAGHI:
+ case CP0_REG29__TAGHI1:
+ case CP0_REG29__TAGHI2:
+ case CP0_REG29__TAGHI3:
gen_helper_mtc0_taghi(cpu_env, arg);
register_name = "TagHi";
break;
- case 1:
- case 3:
- case 5:
- case 7:
+ case CP0_REG29__DATAHI:
+ case CP0_REG29__DATAHI1:
+ case CP0_REG29__DATAHI2:
+ case CP0_REG29__DATAHI3:
gen_helper_mtc0_datahi(cpu_env, arg);
register_name = "DataHi";
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 29/30] target/mips: Clean up handling of CP0 register 30
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (27 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 28/30] target/mips: Clean up handling of CP0 register 29 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 30/30] target/mips: Clean up handling of CP0 register 31 Aleksandar Markovic
2019-08-28 16:46 ` [Qemu-devel] [EXTERNAL][PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Rikalo
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 30.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 2cb132a..065f840 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7569,7 +7569,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_30:
switch (sel) {
- case 0:
+ case CP0_REG30__ERROREPC:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
tcg_gen_ext32s_tl(arg, arg);
register_name = "ErrorEPC";
@@ -8325,7 +8325,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_30:
switch (sel) {
- case 0:
+ case CP0_REG30__ERROREPC:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
register_name = "ErrorEPC";
break;
@@ -9061,7 +9061,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_30:
switch (sel) {
- case 0:
+ case CP0_REG30__ERROREPC:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
register_name = "ErrorEPC";
break;
@@ -9803,7 +9803,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_30:
switch (sel) {
- case 0:
+ case CP0_REG30__ERROREPC:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
register_name = "ErrorEPC";
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH v2 30/30] target/mips: Clean up handling of CP0 register 31
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (28 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 29/30] target/mips: Clean up handling of CP0 register 30 Aleksandar Markovic
@ 2019-08-28 16:26 ` Aleksandar Markovic
2019-08-28 16:46 ` [Qemu-devel] [EXTERNAL][PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Rikalo
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Markovic @ 2019-08-28 16:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 31.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 2 +-
target/mips/translate.c | 56 ++++++++++++++++++++++++-------------------------
2 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index d309ad8..62ad8c2 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -616,7 +616,6 @@ struct CPUMIPSState {
* CP0 Register 4
*/
target_ulong CP0_Context;
- target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
int32_t CP0_MemoryMapID;
/*
* CP0 Register 5
@@ -1027,6 +1026,7 @@ struct CPUMIPSState {
* CP0 Register 31
*/
int32_t CP0_DESAVE;
+ target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
/* We waste some space so we can handle shadow registers like TCs. */
TCState tcs[MIPS_SHADOW_SET_MAX];
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 065f840..1292918 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7580,17 +7580,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_31:
switch (sel) {
- case 0:
+ case CP0_REG31__DESAVE:
/* EJTAG support */
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
register_name = "DESAVE";
break;
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG31__KSCRATCH1:
+ case CP0_REG31__KSCRATCH2:
+ case CP0_REG31__KSCRATCH3:
+ case CP0_REG31__KSCRATCH4:
+ case CP0_REG31__KSCRATCH5:
+ case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -8335,17 +8335,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_31:
switch (sel) {
- case 0:
+ case CP0_REG31__DESAVE:
/* EJTAG support */
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
register_name = "DESAVE";
break;
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG31__KSCRATCH1:
+ case CP0_REG31__KSCRATCH2:
+ case CP0_REG31__KSCRATCH3:
+ case CP0_REG31__KSCRATCH4:
+ case CP0_REG31__KSCRATCH5:
+ case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -9071,17 +9071,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_31:
switch (sel) {
- case 0:
+ case CP0_REG31__DESAVE:
/* EJTAG support */
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
register_name = "DESAVE";
break;
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG31__KSCRATCH1:
+ case CP0_REG31__KSCRATCH2:
+ case CP0_REG31__KSCRATCH3:
+ case CP0_REG31__KSCRATCH4:
+ case CP0_REG31__KSCRATCH5:
+ case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -9813,17 +9813,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_31:
switch (sel) {
- case 0:
+ case CP0_REG31__DESAVE:
/* EJTAG support */
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
register_name = "DESAVE";
break;
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG31__KSCRATCH1:
+ case CP0_REG31__KSCRATCH2:
+ case CP0_REG31__KSCRATCH3:
+ case CP0_REG31__KSCRATCH4:
+ case CP0_REG31__KSCRATCH5:
+ case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
--
2.7.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [EXTERNAL][PATCH v2 00/30] Clean up handling of configuration register CP0
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
` (29 preceding siblings ...)
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 30/30] target/mips: Clean up handling of CP0 register 31 Aleksandar Markovic
@ 2019-08-28 16:46 ` Aleksandar Rikalo
30 siblings, 0 replies; 32+ messages in thread
From: Aleksandar Rikalo @ 2019-08-28 16:46 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel; +Cc: Stefan Brankovic, Aleksandar Markovic
> From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
> Sent: Wednesday, August 28, 2019 6:26 PM
> To: qemu-devel@nongnu.org <qemu-devel@nongnu.org>
> Cc: Aleksandar Markovic <amarkovic@wavecomp.com>; Aleksandar Rikalo <arikalo@wavecomp.com>
> Subject: [EXTERNAL][PATCH v2 00/30] Clean up handling of configuration register CP0
>
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> v1->v2:
>
> - added cleanup of handling six more registers
> - misc improvements
>
> This series is a spin-off of a former "Misc MIPS fixes for 4.2" series.
>
> The goal of the series is to clean up CP0-related code, and prepare
> it for (near) future extensions and amendments.
>
> The series is mostly of refactoring nature, however it may contain
> simple fixes (for example, fixes for obvious bugs, or additions of
> simple subregister handling). The more complex fixes and improvements
> (for example, additions of VPE-related functionalities) are, for now,
> outside the scope of this series.
>
> Aleksandar Markovic (30):
> target/mips: Clean up handling of CP0 register 0
> target/mips: Clean up handling of CP0 register 1
> target/mips: Clean up handling of CP0 register 2
> target/mips: Clean up handling of CP0 register 3
> target/mips: Clean up handling of CP0 register 4
> target/mips: Clean up handling of CP0 register 5
> target/mips: Clean up handling of CP0 register 6
> target/mips: Clean up handling of CP0 register 7
> target/mips: Clean up handling of CP0 register 8
> target/mips: Clean up handling of CP0 register 9
> target/mips: Clean up handling of CP0 register 10
> target/mips: Clean up handling of CP0 register 11
> target/mips: Clean up handling of CP0 register 12
> target/mips: Clean up handling of CP0 register 13
> target/mips: Clean up handling of CP0 register 14
> target/mips: Clean up handling of CP0 register 15
> target/mips: Clean up handling of CP0 register 16
> target/mips: Clean up handling of CP0 register 17
> target/mips: Clean up handling of CP0 register 18
> target/mips: Clean up handling of CP0 register 19
> target/mips: Clean up handling of CP0 register 20
> target/mips: Clean up handling of CP0 register 23
> target/mips: Clean up handling of CP0 register 24
> target/mips: Clean up handling of CP0 register 25
> target/mips: Clean up handling of CP0 register 26
> target/mips: Clean up handling of CP0 register 27
> target/mips: Clean up handling of CP0 register 28
> target/mips: Clean up handling of CP0 register 29
> target/mips: Clean up handling of CP0 register 30
> target/mips: Clean up handling of CP0 register 31
>
> target/mips/cpu.h | 113 ++++-
> target/mips/translate.c | 1150 ++++++++++++++++++++++++-----------------------
> 2 files changed, 681 insertions(+), 582 deletions(-)
>
> --
> 2.7.4
The series looks good to me. It would be nice to include MTTP and MFTR handling in future cleanups.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2019-08-28 17:08 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
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2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
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2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 02/30] target/mips: Clean up handling of CP0 register 1 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 03/30] target/mips: Clean up handling of CP0 register 2 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 04/30] target/mips: Clean up handling of CP0 register 3 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 05/30] target/mips: Clean up handling of CP0 register 4 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 06/30] target/mips: Clean up handling of CP0 register 5 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 07/30] target/mips: Clean up handling of CP0 register 6 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 08/30] target/mips: Clean up handling of CP0 register 7 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 09/30] target/mips: Clean up handling of CP0 register 8 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 10/30] target/mips: Clean up handling of CP0 register 9 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 11/30] target/mips: Clean up handling of CP0 register 10 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 12/30] target/mips: Clean up handling of CP0 register 11 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 13/30] target/mips: Clean up handling of CP0 register 12 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 14/30] target/mips: Clean up handling of CP0 register 13 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 15/30] target/mips: Clean up handling of CP0 register 14 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 16/30] target/mips: Clean up handling of CP0 register 15 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 17/30] target/mips: Clean up handling of CP0 register 16 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 18/30] target/mips: Clean up handling of CP0 register 17 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 19/30] target/mips: Clean up handling of CP0 register 18 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 20/30] target/mips: Clean up handling of CP0 register 19 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 21/30] target/mips: Clean up handling of CP0 register 20 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 22/30] target/mips: Clean up handling of CP0 register 23 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 23/30] target/mips: Clean up handling of CP0 register 24 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 24/30] target/mips: Clean up handling of CP0 register 25 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 25/30] target/mips: Clean up handling of CP0 register 26 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 26/30] target/mips: Clean up handling of CP0 register 27 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 27/30] target/mips: Clean up handling of CP0 register 28 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 28/30] target/mips: Clean up handling of CP0 register 29 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 29/30] target/mips: Clean up handling of CP0 register 30 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 30/30] target/mips: Clean up handling of CP0 register 31 Aleksandar Markovic
2019-08-28 16:46 ` [Qemu-devel] [EXTERNAL][PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Rikalo
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