* [PATCH v7 0/9] Support dsi for mt8183
@ 2019-09-19 6:57 Jitao Shi
2019-09-19 6:57 ` [PATCH v7 1/9] drm/mediatek: move mipi_dsi_host_register to probe Jitao Shi
` (9 more replies)
0 siblings, 10 replies; 21+ messages in thread
From: Jitao Shi @ 2019-09-19 6:57 UTC (permalink / raw)
To: CK Hu, David Airlie, Daniel Vetter, dri-devel
Cc: Jitao Shi, srv_heupstream, stonea168, cawa.cheng, sj.huang,
linux-mediatek, Matthias Brugger, yingjoe.chen, eddie.huang
Changes since v6:
- add dphy reset to avoid dphy fifo error after lines number setting
- separate dsi cmd reg setting from "fixes CMDQ reg address of mt8173
is different with mt2701"
Changes since v5:
- fine tune dphy timing.
Changes since v4:
- move mipi_dsi_host_unregiter() to .remove()
- fine tune add frame size control coding style
- change the data type of data_rate as u32, and add DIV_ROUND_UP_ULL
- use div_u64 when 8000000000ULL / dsi->data_rate.
Changes since v3
- add one more 'tab' for bitwise define.
- add Tested-by: Ryan Case <ryandcase@chromium.org>
and Reviewed-by: CK Hu <ck.hu@mediatek.com>.
- remove compare da_hs_zero to da_hs_prepare.
Changes since v2:
- change the video timing calc method
- fine the dsi and mipitx init sequence
- fine tune commit msg
Changes since v1:
- separate frame size and reg commit control independent patches.
- fix some return values in probe
- remove DSI_CMDW0 in "CMDQ reg address of mt8173 is different with mt2701"
Jitao Shi (9):
drm/mediatek: move mipi_dsi_host_register to probe
drm/mediatek: fixes CMDQ reg address of mt8173 is different with
mt2701
drm/mediatek: replace writeb() with mtk_dsi_mask()
drm/mediatek: add dsi reg commit disable control
drm/mediatek: add frame size control
drm/mediatek: add mt8183 dsi driver support
drm/mediatek: change the dsi phytiming calculate method
drm: mediatek: adjust dsi and mipi_tx probe sequence
drm/mediatek: add dphy reset after setting lanes number
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +-
drivers/gpu/drm/mediatek/mtk_dsi.c | 233 ++++++++++++++++++-------
2 files changed, 170 insertions(+), 65 deletions(-)
--
2.21.0
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^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v7 1/9] drm/mediatek: move mipi_dsi_host_register to probe
2019-09-19 6:57 [PATCH v7 0/9] Support dsi for mt8183 Jitao Shi
@ 2019-09-19 6:57 ` Jitao Shi
2019-09-19 6:57 ` [PATCH v7 2/9] drm/mediatek: fixes CMDQ reg address of mt8173 is different with mt2701 Jitao Shi
` (8 subsequent siblings)
9 siblings, 0 replies; 21+ messages in thread
From: Jitao Shi @ 2019-09-19 6:57 UTC (permalink / raw)
To: CK Hu, David Airlie, Daniel Vetter, dri-devel
Cc: Jitao Shi, srv_heupstream, stonea168, cawa.cheng, sj.huang,
linux-mediatek, Matthias Brugger, yingjoe.chen, eddie.huang
DSI panel driver need attach function which is inculde in
mipi_dsi_host_ops.
If mipi_dsi_host_register is not in probe, dsi panel will
probe more delay.
So move the mipi_dsi_host_register to probe from bind.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 53 +++++++++++++++++-------------
1 file changed, 31 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index b91c4616644a..52b49daeed9f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -520,7 +520,7 @@ static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t)
static int mtk_dsi_poweron(struct mtk_dsi *dsi)
{
- struct device *dev = dsi->dev;
+ struct device *dev = dsi->host.dev;
int ret;
u64 pixel_clock, total_bits;
u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
@@ -1047,12 +1047,6 @@ static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
return ret;
}
- ret = mipi_dsi_host_register(&dsi->host);
- if (ret < 0) {
- dev_err(dev, "failed to register DSI host: %d\n", ret);
- goto err_ddp_comp_unregister;
- }
-
ret = mtk_dsi_create_conn_enc(drm, dsi);
if (ret) {
DRM_ERROR("Encoder create failed with %d\n", ret);
@@ -1062,8 +1056,6 @@ static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
return 0;
err_unregister:
- mipi_dsi_host_unregister(&dsi->host);
-err_ddp_comp_unregister:
mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
return ret;
}
@@ -1075,7 +1067,6 @@ static void mtk_dsi_unbind(struct device *dev, struct device *master,
struct mtk_dsi *dsi = dev_get_drvdata(dev);
mtk_dsi_destroy_conn_enc(dsi);
- mipi_dsi_host_unregister(&dsi->host);
mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
}
@@ -1099,31 +1090,36 @@ static int mtk_dsi_probe(struct platform_device *pdev)
dsi->host.ops = &mtk_dsi_ops;
dsi->host.dev = dev;
+ ret = mipi_dsi_host_register(&dsi->host);
+ if (ret < 0) {
+ dev_err(dev, "failed to register DSI host: %d\n", ret);
+ return ret;
+ }
ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
&dsi->panel, &dsi->bridge);
if (ret)
- return ret;
+ goto err_unregister_host;
dsi->engine_clk = devm_clk_get(dev, "engine");
if (IS_ERR(dsi->engine_clk)) {
ret = PTR_ERR(dsi->engine_clk);
dev_err(dev, "Failed to get engine clock: %d\n", ret);
- return ret;
+ goto err_unregister_host;
}
dsi->digital_clk = devm_clk_get(dev, "digital");
if (IS_ERR(dsi->digital_clk)) {
ret = PTR_ERR(dsi->digital_clk);
dev_err(dev, "Failed to get digital clock: %d\n", ret);
- return ret;
+ goto err_unregister_host;
}
dsi->hs_clk = devm_clk_get(dev, "hs");
if (IS_ERR(dsi->hs_clk)) {
ret = PTR_ERR(dsi->hs_clk);
dev_err(dev, "Failed to get hs clock: %d\n", ret);
- return ret;
+ goto err_unregister_host;
}
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1131,33 +1127,35 @@ static int mtk_dsi_probe(struct platform_device *pdev)
if (IS_ERR(dsi->regs)) {
ret = PTR_ERR(dsi->regs);
dev_err(dev, "Failed to ioremap memory: %d\n", ret);
- return ret;
+ goto err_unregister_host;
}
dsi->phy = devm_phy_get(dev, "dphy");
if (IS_ERR(dsi->phy)) {
ret = PTR_ERR(dsi->phy);
dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
- return ret;
+ goto err_unregister_host;
}
comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
if (comp_id < 0) {
dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
- return comp_id;
+ ret = comp_id;
+ goto err_unregister_host;
}
ret = mtk_ddp_comp_init(dev, dev->of_node, &dsi->ddp_comp, comp_id,
&mtk_dsi_funcs);
if (ret) {
dev_err(dev, "Failed to initialize component: %d\n", ret);
- return ret;
+ goto err_unregister_host;
}
irq_num = platform_get_irq(pdev, 0);
if (irq_num < 0) {
- dev_err(&pdev->dev, "failed to request dsi irq resource\n");
- return -EPROBE_DEFER;
+ dev_err(&pdev->dev, "failed to get dsi irq_num: %d\n", irq_num);
+ ret = irq_num;
+ goto err_unregister_host;
}
irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW);
@@ -1165,14 +1163,24 @@ static int mtk_dsi_probe(struct platform_device *pdev)
IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi);
if (ret) {
dev_err(&pdev->dev, "failed to request mediatek dsi irq\n");
- return -EPROBE_DEFER;
+ goto err_unregister_host;
}
init_waitqueue_head(&dsi->irq_wait_queue);
platform_set_drvdata(pdev, dsi);
- return component_add(&pdev->dev, &mtk_dsi_component_ops);
+ ret = component_add(&pdev->dev, &mtk_dsi_component_ops);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to add component: %d\n", ret);
+ goto err_unregister_host;
+ }
+
+ return 0;
+
+err_unregister_host:
+ mipi_dsi_host_unregister(&dsi->host);
+ return ret;
}
static int mtk_dsi_remove(struct platform_device *pdev)
@@ -1181,6 +1189,7 @@ static int mtk_dsi_remove(struct platform_device *pdev)
mtk_output_dsi_disable(dsi);
component_del(&pdev->dev, &mtk_dsi_component_ops);
+ mipi_dsi_host_unregister(&dsi->host);
return 0;
}
--
2.21.0
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v7 2/9] drm/mediatek: fixes CMDQ reg address of mt8173 is different with mt2701
2019-09-19 6:57 [PATCH v7 0/9] Support dsi for mt8183 Jitao Shi
2019-09-19 6:57 ` [PATCH v7 1/9] drm/mediatek: move mipi_dsi_host_register to probe Jitao Shi
@ 2019-09-19 6:57 ` Jitao Shi
2019-09-26 8:50 ` CK Hu
2019-09-19 6:58 ` [PATCH v7 3/9] drm/mediatek: replace writeb() with mtk_dsi_mask() Jitao Shi
` (7 subsequent siblings)
9 siblings, 1 reply; 21+ messages in thread
From: Jitao Shi @ 2019-09-19 6:57 UTC (permalink / raw)
To: CK Hu, David Airlie, Daniel Vetter, dri-devel
Cc: Jitao Shi, srv_heupstream, stonea168, cawa.cheng, sj.huang,
linux-mediatek, Matthias Brugger, yingjoe.chen, eddie.huang
Config the different CMDQ reg address in driver data.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 27 ++++++++++++++++++++++-----
1 file changed, 22 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 52b49daeed9f..7e24d03cdccc 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -123,7 +123,6 @@
#define VM_CMD_EN BIT(0)
#define TS_VFP_EN BIT(5)
-#define DSI_CMDQ0 0x180
#define CONFIG (0xff << 0)
#define SHORT_PACKET 0
#define LONG_PACKET 2
@@ -148,6 +147,10 @@
struct phy;
+struct mtk_dsi_driver_data {
+ const u32 reg_cmdq_off;
+};
+
struct mtk_dsi {
struct mtk_ddp_comp ddp_comp;
struct device *dev;
@@ -174,6 +177,7 @@ struct mtk_dsi {
bool enabled;
u32 irq_data;
wait_queue_head_t irq_wait_queue;
+ const struct mtk_dsi_driver_data *driver_data;
};
static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
@@ -936,6 +940,7 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
const char *tx_buf = msg->tx_buf;
u8 config, cmdq_size, cmdq_off, type = msg->type;
u32 reg_val, cmdq_mask, i;
+ u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off;
if (MTK_DSI_HOST_IS_READ(type))
config = BTA;
@@ -955,9 +960,9 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
}
for (i = 0; i < msg->tx_len; i++)
- writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i);
+ writeb(tx_buf[i], dsi->regs + reg_cmdq_off + cmdq_off + i);
- mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val);
+ mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
}
@@ -1101,6 +1106,8 @@ static int mtk_dsi_probe(struct platform_device *pdev)
if (ret)
goto err_unregister_host;
+ dsi->driver_data = of_device_get_match_data(dev);
+
dsi->engine_clk = devm_clk_get(dev, "engine");
if (IS_ERR(dsi->engine_clk)) {
ret = PTR_ERR(dsi->engine_clk);
@@ -1194,9 +1201,19 @@ static int mtk_dsi_remove(struct platform_device *pdev)
return 0;
}
+static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = {
+ .reg_cmdq_off = 0x200,
+};
+
+static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = {
+ .reg_cmdq_off = 0x180,
+};
+
static const struct of_device_id mtk_dsi_of_match[] = {
- { .compatible = "mediatek,mt2701-dsi" },
- { .compatible = "mediatek,mt8173-dsi" },
+ { .compatible = "mediatek,mt2701-dsi",
+ .data = &mt2701_dsi_driver_data },
+ { .compatible = "mediatek,mt8173-dsi",
+ .data = &mt8173_dsi_driver_data },
{ },
};
--
2.21.0
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v7 3/9] drm/mediatek: replace writeb() with mtk_dsi_mask()
2019-09-19 6:57 [PATCH v7 0/9] Support dsi for mt8183 Jitao Shi
2019-09-19 6:57 ` [PATCH v7 1/9] drm/mediatek: move mipi_dsi_host_register to probe Jitao Shi
2019-09-19 6:57 ` [PATCH v7 2/9] drm/mediatek: fixes CMDQ reg address of mt8173 is different with mt2701 Jitao Shi
@ 2019-09-19 6:58 ` Jitao Shi
2019-09-26 8:50 ` CK Hu
2019-09-19 6:58 ` [PATCH v7 4/9] drm/mediatek: add dsi reg commit disable control Jitao Shi
` (6 subsequent siblings)
9 siblings, 1 reply; 21+ messages in thread
From: Jitao Shi @ 2019-09-19 6:58 UTC (permalink / raw)
To: CK Hu, David Airlie, Daniel Vetter, dri-devel
Cc: Jitao Shi, srv_heupstream, stonea168, cawa.cheng, sj.huang,
linux-mediatek, Matthias Brugger, yingjoe.chen, eddie.huang
The writeb() is unavailable in mt8173. Because the mt8173 dsi module
doesn't support 8bit mode access.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 7e24d03cdccc..ac8e80e379f7 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -960,7 +960,9 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
}
for (i = 0; i < msg->tx_len; i++)
- writeb(tx_buf[i], dsi->regs + reg_cmdq_off + cmdq_off + i);
+ mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U),
+ (0xffUL << (((i + cmdq_off) & 3U) * 8U)),
+ tx_buf[i] << (((i + cmdq_off) & 3U) * 8U));
mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
--
2.21.0
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v7 4/9] drm/mediatek: add dsi reg commit disable control
2019-09-19 6:57 [PATCH v7 0/9] Support dsi for mt8183 Jitao Shi
` (2 preceding siblings ...)
2019-09-19 6:58 ` [PATCH v7 3/9] drm/mediatek: replace writeb() with mtk_dsi_mask() Jitao Shi
@ 2019-09-19 6:58 ` Jitao Shi
2019-09-19 6:58 ` [PATCH v7 5/9] drm/mediatek: add frame size control Jitao Shi
` (5 subsequent siblings)
9 siblings, 0 replies; 21+ messages in thread
From: Jitao Shi @ 2019-09-19 6:58 UTC (permalink / raw)
To: CK Hu, David Airlie, Daniel Vetter, dri-devel
Cc: Jitao Shi, srv_heupstream, stonea168, cawa.cheng, sj.huang,
linux-mediatek, Matthias Brugger, yingjoe.chen, eddie.huang
New DSI IP has shadow register and working reg. The register
values are writen to shadow register. And then trigger with
commit reg, the register values will be moved working register.
This fucntion is defualt on. But this driver doesn't use this
function. So add the disable control.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index ac8e80e379f7..314bfb1c827b 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -123,6 +123,10 @@
#define VM_CMD_EN BIT(0)
#define TS_VFP_EN BIT(5)
+#define DSI_SHADOW_DEBUG 0x190U
+#define FORCE_COMMIT BIT(0)
+#define BYPASS_SHADOW BIT(1)
+
#define CONFIG (0xff << 0)
#define SHORT_PACKET 0
#define LONG_PACKET 2
@@ -149,6 +153,7 @@ struct phy;
struct mtk_dsi_driver_data {
const u32 reg_cmdq_off;
+ bool has_shadow_ctl;
};
struct mtk_dsi {
@@ -586,6 +591,11 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
}
mtk_dsi_enable(dsi);
+
+ if (dsi->driver_data->has_shadow_ctl)
+ writel(FORCE_COMMIT | BYPASS_SHADOW,
+ dsi->regs + DSI_SHADOW_DEBUG);
+
mtk_dsi_reset_engine(dsi);
mtk_dsi_phy_timconfig(dsi);
--
2.21.0
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v7 5/9] drm/mediatek: add frame size control
2019-09-19 6:57 [PATCH v7 0/9] Support dsi for mt8183 Jitao Shi
` (3 preceding siblings ...)
2019-09-19 6:58 ` [PATCH v7 4/9] drm/mediatek: add dsi reg commit disable control Jitao Shi
@ 2019-09-19 6:58 ` Jitao Shi
2019-09-19 6:58 ` [PATCH v7 6/9] drm/mediatek: add mt8183 dsi driver support Jitao Shi
` (4 subsequent siblings)
9 siblings, 0 replies; 21+ messages in thread
From: Jitao Shi @ 2019-09-19 6:58 UTC (permalink / raw)
To: CK Hu, David Airlie, Daniel Vetter, dri-devel
Cc: Jitao Shi, srv_heupstream, stonea168, cawa.cheng, sj.huang,
linux-mediatek, Matthias Brugger, yingjoe.chen, eddie.huang
Our new DSI chip has frame size control.
So add the driver data to control for different chips.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 314bfb1c827b..68794edecf96 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -70,6 +70,7 @@
#define DSI_VBP_NL 0x24
#define DSI_VFP_NL 0x28
#define DSI_VACT_NL 0x2C
+#define DSI_SIZE_CON 0x38
#define DSI_HSA_WC 0x50
#define DSI_HBP_WC 0x54
#define DSI_HFP_WC 0x58
@@ -154,6 +155,7 @@ struct phy;
struct mtk_dsi_driver_data {
const u32 reg_cmdq_off;
bool has_shadow_ctl;
+ bool has_size_ctl;
};
struct mtk_dsi {
@@ -422,6 +424,10 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
writel(vm->vactive, dsi->regs + DSI_VACT_NL);
+ if (dsi->driver_data->has_size_ctl)
+ writel(vm->vactive << 16 | vm->hactive,
+ dsi->regs + DSI_SIZE_CON);
+
horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
--
2.21.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v7 6/9] drm/mediatek: add mt8183 dsi driver support
2019-09-19 6:57 [PATCH v7 0/9] Support dsi for mt8183 Jitao Shi
` (4 preceding siblings ...)
2019-09-19 6:58 ` [PATCH v7 5/9] drm/mediatek: add frame size control Jitao Shi
@ 2019-09-19 6:58 ` Jitao Shi
2019-09-19 6:58 ` [PATCH v7 7/9] drm/mediatek: change the dsi phytiming calculate method Jitao Shi
` (3 subsequent siblings)
9 siblings, 0 replies; 21+ messages in thread
From: Jitao Shi @ 2019-09-19 6:58 UTC (permalink / raw)
To: CK Hu, David Airlie, Daniel Vetter, dri-devel
Cc: Jitao Shi, srv_heupstream, stonea168, cawa.cheng, sj.huang,
linux-mediatek, Matthias Brugger, yingjoe.chen, eddie.huang
Add mt8183 dsi driver data. Enable size control and
reg commit control.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 68794edecf96..b3676426aeb5 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -1227,11 +1227,19 @@ static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = {
.reg_cmdq_off = 0x180,
};
+static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = {
+ .reg_cmdq_off = 0x200,
+ .has_shadow_ctl = true,
+ .has_size_ctl = true,
+};
+
static const struct of_device_id mtk_dsi_of_match[] = {
{ .compatible = "mediatek,mt2701-dsi",
.data = &mt2701_dsi_driver_data },
{ .compatible = "mediatek,mt8173-dsi",
.data = &mt8173_dsi_driver_data },
+ { .compatible = "mediatek,mt8183-dsi",
+ .data = &mt8183_dsi_driver_data },
{ },
};
--
2.21.0
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v7 7/9] drm/mediatek: change the dsi phytiming calculate method
2019-09-19 6:57 [PATCH v7 0/9] Support dsi for mt8183 Jitao Shi
` (5 preceding siblings ...)
2019-09-19 6:58 ` [PATCH v7 6/9] drm/mediatek: add mt8183 dsi driver support Jitao Shi
@ 2019-09-19 6:58 ` Jitao Shi
2019-09-26 8:51 ` CK Hu
2019-09-19 6:58 ` [PATCH v7 8/9] drm: mediatek: adjust dsi and mipi_tx probe sequence Jitao Shi
` (2 subsequent siblings)
9 siblings, 1 reply; 21+ messages in thread
From: Jitao Shi @ 2019-09-19 6:58 UTC (permalink / raw)
To: CK Hu, David Airlie, Daniel Vetter, dri-devel
Cc: Jitao Shi, srv_heupstream, stonea168, cawa.cheng, Ryan Case,
sj.huang, linux-mediatek, Matthias Brugger, yingjoe.chen,
eddie.huang
Change the method of frame rate calc which can get more accurate
frame rate.
data rate = pixel_clock * bit_per_pixel / lanes
Adjust hfp_wc to adapt the additional phy_data
if MIPI_DSI_MODE_VIDEO_BURST
hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12 - 6;
else
hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12;
Note:
//(2: 1 for sync, 1 for phy idle)
data_phy_cycles = T_hs_exit + T_lpx + T_hs_prepare + T_hs_zero + 2;
bpp: bit per pixel
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Tested-by: Ryan Case <ryandcase@chromium.org>
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 118 ++++++++++++++++++++---------
1 file changed, 81 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index b3676426aeb5..b02373b04848 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -136,12 +136,6 @@
#define DATA_0 (0xff << 16)
#define DATA_1 (0xff << 24)
-#define T_LPX 5
-#define T_HS_PREP 6
-#define T_HS_TRAIL 8
-#define T_HS_EXIT 7
-#define T_HS_ZERO 10
-
#define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
#define MTK_DSI_HOST_IS_READ(type) \
@@ -150,6 +144,25 @@
(type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
(type == MIPI_DSI_DCS_READ))
+struct mtk_phy_timing {
+ u32 lpx;
+ u32 da_hs_prepare;
+ u32 da_hs_zero;
+ u32 da_hs_trail;
+
+ u32 ta_go;
+ u32 ta_sure;
+ u32 ta_get;
+ u32 da_hs_exit;
+
+ u32 clk_hs_zero;
+ u32 clk_hs_trail;
+
+ u32 clk_hs_prepare;
+ u32 clk_hs_post;
+ u32 clk_hs_exit;
+};
+
struct phy;
struct mtk_dsi_driver_data {
@@ -180,6 +193,7 @@ struct mtk_dsi {
enum mipi_dsi_pixel_format format;
unsigned int lanes;
struct videomode vm;
+ struct mtk_phy_timing phy_timing;
int refcount;
bool enabled;
u32 irq_data;
@@ -213,17 +227,36 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
{
u32 timcon0, timcon1, timcon2, timcon3;
u32 ui, cycle_time;
+ struct mtk_phy_timing *timing = &dsi->phy_timing;
+
+ ui = DIV_ROUND_UP(1000000000, dsi->data_rate);
+ cycle_time = div_u64(8000000000ULL, dsi->data_rate);
+
+ timing->lpx = NS_TO_CYCLE(60, cycle_time);
+ timing->da_hs_prepare = NS_TO_CYCLE(50 + 5 * ui, cycle_time);
+ timing->da_hs_zero = NS_TO_CYCLE(110 + 6 * ui, cycle_time);
+ timing->da_hs_trail = NS_TO_CYCLE(77 + 4 * ui, cycle_time);
- ui = 1000 / dsi->data_rate + 0x01;
- cycle_time = 8000 / dsi->data_rate + 0x01;
+ timing->ta_go = 4 * timing->lpx;
+ timing->ta_sure = 3 * timing->lpx / 2;
+ timing->ta_get = 5 * timing->lpx;
+ timing->da_hs_exit = 2 * timing->lpx;
- timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
- timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 |
- T_HS_EXIT << 24;
- timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
- (NS_TO_CYCLE(0x150, cycle_time) << 16);
- timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 |
- NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
+ timing->clk_hs_zero = NS_TO_CYCLE(336, cycle_time);
+ timing->clk_hs_trail = NS_TO_CYCLE(100, cycle_time) + 10;
+
+ timing->clk_hs_prepare = NS_TO_CYCLE(64, cycle_time);
+ timing->clk_hs_post = NS_TO_CYCLE(80 + 52 * ui, cycle_time);
+ timing->clk_hs_exit = 2 * timing->lpx;
+
+ timcon0 = timing->lpx | timing->da_hs_prepare << 8 |
+ timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
+ timcon1 = timing->ta_go | timing->ta_sure << 8 |
+ timing->ta_get << 16 | timing->da_hs_exit << 24;
+ timcon2 = 1 << 8 | timing->clk_hs_zero << 16 |
+ timing->clk_hs_trail << 24;
+ timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 |
+ timing->clk_hs_exit << 16;
writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
@@ -410,7 +443,8 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
u32 horizontal_sync_active_byte;
u32 horizontal_backporch_byte;
u32 horizontal_frontporch_byte;
- u32 dsi_tmp_buf_bpp;
+ u32 dsi_tmp_buf_bpp, data_phy_cycles;
+ struct mtk_phy_timing *timing = &dsi->phy_timing;
struct videomode *vm = &dsi->vm;
@@ -437,7 +471,34 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
dsi_tmp_buf_bpp - 10);
- horizontal_frontporch_byte = (vm->hfront_porch * dsi_tmp_buf_bpp - 12);
+ data_phy_cycles = timing->lpx + timing->da_hs_prepare +
+ timing->da_hs_zero + timing->da_hs_exit + 2;
+
+ if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
+ if (vm->hfront_porch * dsi_tmp_buf_bpp >
+ data_phy_cycles * dsi->lanes + 18) {
+ horizontal_frontporch_byte = vm->hfront_porch *
+ dsi_tmp_buf_bpp -
+ data_phy_cycles *
+ dsi->lanes - 18;
+ } else {
+ DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
+ horizontal_frontporch_byte = vm->hfront_porch *
+ dsi_tmp_buf_bpp;
+ }
+ } else {
+ if (vm->hfront_porch * dsi_tmp_buf_bpp >
+ data_phy_cycles * dsi->lanes + 12) {
+ horizontal_frontporch_byte = vm->hfront_porch *
+ dsi_tmp_buf_bpp -
+ data_phy_cycles *
+ dsi->lanes - 12;
+ } else {
+ DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
+ horizontal_frontporch_byte = vm->hfront_porch *
+ dsi_tmp_buf_bpp;
+ }
+ }
writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
@@ -537,8 +598,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
{
struct device *dev = dsi->host.dev;
int ret;
- u64 pixel_clock, total_bits;
- u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
+ u32 bit_per_pixel;
if (++dsi->refcount != 1)
return 0;
@@ -557,24 +617,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
break;
}
- /**
- * htotal_time = htotal * byte_per_pixel / num_lanes
- * overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit
- * mipi_ratio = (htotal_time + overhead_time) / htotal_time
- * data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes;
- */
- pixel_clock = dsi->vm.pixelclock;
- htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch +
- dsi->vm.hsync_len;
- htotal_bits = htotal * bit_per_pixel;
-
- overhead_cycles = T_LPX + T_HS_PREP + T_HS_ZERO + T_HS_TRAIL +
- T_HS_EXIT;
- overhead_bits = overhead_cycles * dsi->lanes * 8;
- total_bits = htotal_bits + overhead_bits;
-
- dsi->data_rate = DIV_ROUND_UP_ULL(pixel_clock * total_bits,
- htotal * dsi->lanes);
+ dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
+ dsi->lanes);
ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
if (ret < 0) {
--
2.21.0
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v7 8/9] drm: mediatek: adjust dsi and mipi_tx probe sequence
2019-09-19 6:57 [PATCH v7 0/9] Support dsi for mt8183 Jitao Shi
` (6 preceding siblings ...)
2019-09-19 6:58 ` [PATCH v7 7/9] drm/mediatek: change the dsi phytiming calculate method Jitao Shi
@ 2019-09-19 6:58 ` Jitao Shi
2019-09-19 6:58 ` [PATCH v7 9/9] drm/mediatek: add dphy reset after setting lanes number Jitao Shi
2019-09-27 1:35 ` [PATCH v7 0/9] Support dsi for mt8183 CK Hu
9 siblings, 0 replies; 21+ messages in thread
From: Jitao Shi @ 2019-09-19 6:58 UTC (permalink / raw)
To: CK Hu, David Airlie, Daniel Vetter, dri-devel
Cc: Jitao Shi, srv_heupstream, stonea168, cawa.cheng, sj.huang,
linux-mediatek, Matthias Brugger, yingjoe.chen, eddie.huang
mtk_mipi_tx is the phy of mtk_dsi.
mtk_dsi get the phy(mtk_mipi_tx) in probe().
So, mtk_mipi_tx init should be ahead of mtk_dsi. Or mtk_dsi will
defer to wait mtk_mipi_tx probe done.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 945bc20f1d33..7f072cc98530 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -677,8 +677,8 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_disp_rdma_driver,
&mtk_dpi_driver,
&mtk_drm_platform_driver,
- &mtk_dsi_driver,
&mtk_mipi_tx_driver,
+ &mtk_dsi_driver,
};
static int __init mtk_drm_init(void)
--
2.21.0
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v7 9/9] drm/mediatek: add dphy reset after setting lanes number
2019-09-19 6:57 [PATCH v7 0/9] Support dsi for mt8183 Jitao Shi
` (7 preceding siblings ...)
2019-09-19 6:58 ` [PATCH v7 8/9] drm: mediatek: adjust dsi and mipi_tx probe sequence Jitao Shi
@ 2019-09-19 6:58 ` Jitao Shi
2019-09-26 8:52 ` CK Hu
2019-09-27 1:35 ` [PATCH v7 0/9] Support dsi for mt8183 CK Hu
9 siblings, 1 reply; 21+ messages in thread
From: Jitao Shi @ 2019-09-19 6:58 UTC (permalink / raw)
To: CK Hu, David Airlie, Daniel Vetter, dri-devel
Cc: Jitao Shi, srv_heupstream, stonea168, cawa.cheng, sj.huang,
linux-mediatek, Matthias Brugger, yingjoe.chen, eddie.huang
Add dphy reset after setting lanes number to avoid dphy fifo effor.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index b02373b04848..8c2620ea18d0 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -37,6 +37,7 @@
#define DSI_CON_CTRL 0x10
#define DSI_RESET BIT(0)
#define DSI_EN BIT(1)
+#define DPHY_RESET BIT(2)
#define DSI_MODE_CTRL 0x14
#define MODE (3)
@@ -280,6 +281,12 @@ static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
}
+static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi)
+{
+ mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET);
+ mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, 0);
+}
+
static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
{
mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
@@ -650,6 +657,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
mtk_dsi_phy_timconfig(dsi);
mtk_dsi_rxtx_control(dsi);
+ usleep_range(30, 100);
+ mtk_dsi_reset_dphy(dsi);
mtk_dsi_ps_control_vact(dsi);
mtk_dsi_set_vm_cmd(dsi);
mtk_dsi_config_vdo_timing(dsi);
--
2.21.0
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v7 2/9] drm/mediatek: fixes CMDQ reg address of mt8173 is different with mt2701
2019-09-19 6:57 ` [PATCH v7 2/9] drm/mediatek: fixes CMDQ reg address of mt8173 is different with mt2701 Jitao Shi
@ 2019-09-26 8:50 ` CK Hu
0 siblings, 0 replies; 21+ messages in thread
From: CK Hu @ 2019-09-26 8:50 UTC (permalink / raw)
To: Jitao Shi
Cc: srv_heupstream, David Airlie, stonea168, cawa.cheng, dri-devel,
sj.huang, linux-mediatek, Matthias Brugger, yingjoe.chen,
eddie.huang
Hi, Jitao:
On Thu, 2019-09-19 at 14:57 +0800, Jitao Shi wrote:
> Config the different CMDQ reg address in driver data.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 27 ++++++++++++++++++++++-----
> 1 file changed, 22 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 52b49daeed9f..7e24d03cdccc 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -123,7 +123,6 @@
> #define VM_CMD_EN BIT(0)
> #define TS_VFP_EN BIT(5)
>
> -#define DSI_CMDQ0 0x180
> #define CONFIG (0xff << 0)
> #define SHORT_PACKET 0
> #define LONG_PACKET 2
> @@ -148,6 +147,10 @@
>
> struct phy;
>
> +struct mtk_dsi_driver_data {
> + const u32 reg_cmdq_off;
> +};
> +
> struct mtk_dsi {
> struct mtk_ddp_comp ddp_comp;
> struct device *dev;
> @@ -174,6 +177,7 @@ struct mtk_dsi {
> bool enabled;
> u32 irq_data;
> wait_queue_head_t irq_wait_queue;
> + const struct mtk_dsi_driver_data *driver_data;
> };
>
> static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
> @@ -936,6 +940,7 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
> const char *tx_buf = msg->tx_buf;
> u8 config, cmdq_size, cmdq_off, type = msg->type;
> u32 reg_val, cmdq_mask, i;
> + u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off;
>
> if (MTK_DSI_HOST_IS_READ(type))
> config = BTA;
> @@ -955,9 +960,9 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
> }
>
> for (i = 0; i < msg->tx_len; i++)
> - writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i);
> + writeb(tx_buf[i], dsi->regs + reg_cmdq_off + cmdq_off + i);
>
> - mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val);
> + mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
> mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
> }
>
> @@ -1101,6 +1106,8 @@ static int mtk_dsi_probe(struct platform_device *pdev)
> if (ret)
> goto err_unregister_host;
>
> + dsi->driver_data = of_device_get_match_data(dev);
> +
> dsi->engine_clk = devm_clk_get(dev, "engine");
> if (IS_ERR(dsi->engine_clk)) {
> ret = PTR_ERR(dsi->engine_clk);
> @@ -1194,9 +1201,19 @@ static int mtk_dsi_remove(struct platform_device *pdev)
> return 0;
> }
>
> +static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = {
> + .reg_cmdq_off = 0x200,
> +};
> +
> +static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = {
> + .reg_cmdq_off = 0x180,
> +};
> +
> static const struct of_device_id mtk_dsi_of_match[] = {
> - { .compatible = "mediatek,mt2701-dsi" },
> - { .compatible = "mediatek,mt8173-dsi" },
> + { .compatible = "mediatek,mt2701-dsi",
> + .data = &mt2701_dsi_driver_data },
> + { .compatible = "mediatek,mt8173-dsi",
> + .data = &mt8173_dsi_driver_data },
> { },
> };
>
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v7 3/9] drm/mediatek: replace writeb() with mtk_dsi_mask()
2019-09-19 6:58 ` [PATCH v7 3/9] drm/mediatek: replace writeb() with mtk_dsi_mask() Jitao Shi
@ 2019-09-26 8:50 ` CK Hu
0 siblings, 0 replies; 21+ messages in thread
From: CK Hu @ 2019-09-26 8:50 UTC (permalink / raw)
To: Jitao Shi
Cc: srv_heupstream, David Airlie, stonea168, cawa.cheng, dri-devel,
sj.huang, linux-mediatek, Matthias Brugger, yingjoe.chen,
eddie.huang
Hi, Jitao:
On Thu, 2019-09-19 at 14:58 +0800, Jitao Shi wrote:
> The writeb() is unavailable in mt8173. Because the mt8173 dsi module
> doesn't support 8bit mode access.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 7e24d03cdccc..ac8e80e379f7 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -960,7 +960,9 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
> }
>
> for (i = 0; i < msg->tx_len; i++)
> - writeb(tx_buf[i], dsi->regs + reg_cmdq_off + cmdq_off + i);
> + mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U),
> + (0xffUL << (((i + cmdq_off) & 3U) * 8U)),
> + tx_buf[i] << (((i + cmdq_off) & 3U) * 8U));
>
> mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
> mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v7 7/9] drm/mediatek: change the dsi phytiming calculate method
2019-09-19 6:58 ` [PATCH v7 7/9] drm/mediatek: change the dsi phytiming calculate method Jitao Shi
@ 2019-09-26 8:51 ` CK Hu
2019-12-12 13:53 ` Enric Balletbo Serra
0 siblings, 1 reply; 21+ messages in thread
From: CK Hu @ 2019-09-26 8:51 UTC (permalink / raw)
To: Jitao Shi
Cc: srv_heupstream, David Airlie, stonea168, cawa.cheng, dri-devel,
Ryan Case, sj.huang, linux-mediatek, Matthias Brugger,
yingjoe.chen, eddie.huang
Hi, Jitao:
On Thu, 2019-09-19 at 14:58 +0800, Jitao Shi wrote:
> Change the method of frame rate calc which can get more accurate
> frame rate.
>
> data rate = pixel_clock * bit_per_pixel / lanes
> Adjust hfp_wc to adapt the additional phy_data
>
> if MIPI_DSI_MODE_VIDEO_BURST
> hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12 - 6;
> else
> hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12;
>
> Note:
> //(2: 1 for sync, 1 for phy idle)
> data_phy_cycles = T_hs_exit + T_lpx + T_hs_prepare + T_hs_zero + 2;
>
> bpp: bit per pixel
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> Tested-by: Ryan Case <ryandcase@chromium.org>
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 118 ++++++++++++++++++++---------
> 1 file changed, 81 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index b3676426aeb5..b02373b04848 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -136,12 +136,6 @@
> #define DATA_0 (0xff << 16)
> #define DATA_1 (0xff << 24)
>
> -#define T_LPX 5
> -#define T_HS_PREP 6
> -#define T_HS_TRAIL 8
> -#define T_HS_EXIT 7
> -#define T_HS_ZERO 10
> -
> #define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
>
> #define MTK_DSI_HOST_IS_READ(type) \
> @@ -150,6 +144,25 @@
> (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
> (type == MIPI_DSI_DCS_READ))
>
> +struct mtk_phy_timing {
> + u32 lpx;
> + u32 da_hs_prepare;
> + u32 da_hs_zero;
> + u32 da_hs_trail;
> +
> + u32 ta_go;
> + u32 ta_sure;
> + u32 ta_get;
> + u32 da_hs_exit;
> +
> + u32 clk_hs_zero;
> + u32 clk_hs_trail;
> +
> + u32 clk_hs_prepare;
> + u32 clk_hs_post;
> + u32 clk_hs_exit;
> +};
> +
> struct phy;
>
> struct mtk_dsi_driver_data {
> @@ -180,6 +193,7 @@ struct mtk_dsi {
> enum mipi_dsi_pixel_format format;
> unsigned int lanes;
> struct videomode vm;
> + struct mtk_phy_timing phy_timing;
> int refcount;
> bool enabled;
> u32 irq_data;
> @@ -213,17 +227,36 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
> {
> u32 timcon0, timcon1, timcon2, timcon3;
> u32 ui, cycle_time;
> + struct mtk_phy_timing *timing = &dsi->phy_timing;
> +
> + ui = DIV_ROUND_UP(1000000000, dsi->data_rate);
> + cycle_time = div_u64(8000000000ULL, dsi->data_rate);
> +
> + timing->lpx = NS_TO_CYCLE(60, cycle_time);
> + timing->da_hs_prepare = NS_TO_CYCLE(50 + 5 * ui, cycle_time);
> + timing->da_hs_zero = NS_TO_CYCLE(110 + 6 * ui, cycle_time);
> + timing->da_hs_trail = NS_TO_CYCLE(77 + 4 * ui, cycle_time);
>
> - ui = 1000 / dsi->data_rate + 0x01;
> - cycle_time = 8000 / dsi->data_rate + 0x01;
> + timing->ta_go = 4 * timing->lpx;
> + timing->ta_sure = 3 * timing->lpx / 2;
> + timing->ta_get = 5 * timing->lpx;
> + timing->da_hs_exit = 2 * timing->lpx;
>
> - timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
> - timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 |
> - T_HS_EXIT << 24;
> - timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
> - (NS_TO_CYCLE(0x150, cycle_time) << 16);
> - timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 |
> - NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
> + timing->clk_hs_zero = NS_TO_CYCLE(336, cycle_time);
> + timing->clk_hs_trail = NS_TO_CYCLE(100, cycle_time) + 10;
> +
> + timing->clk_hs_prepare = NS_TO_CYCLE(64, cycle_time);
> + timing->clk_hs_post = NS_TO_CYCLE(80 + 52 * ui, cycle_time);
> + timing->clk_hs_exit = 2 * timing->lpx;
> +
> + timcon0 = timing->lpx | timing->da_hs_prepare << 8 |
> + timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
> + timcon1 = timing->ta_go | timing->ta_sure << 8 |
> + timing->ta_get << 16 | timing->da_hs_exit << 24;
> + timcon2 = 1 << 8 | timing->clk_hs_zero << 16 |
> + timing->clk_hs_trail << 24;
> + timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 |
> + timing->clk_hs_exit << 16;
>
> writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
> writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
> @@ -410,7 +443,8 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
> u32 horizontal_sync_active_byte;
> u32 horizontal_backporch_byte;
> u32 horizontal_frontporch_byte;
> - u32 dsi_tmp_buf_bpp;
> + u32 dsi_tmp_buf_bpp, data_phy_cycles;
> + struct mtk_phy_timing *timing = &dsi->phy_timing;
>
> struct videomode *vm = &dsi->vm;
>
> @@ -437,7 +471,34 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
> horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
> dsi_tmp_buf_bpp - 10);
>
> - horizontal_frontporch_byte = (vm->hfront_porch * dsi_tmp_buf_bpp - 12);
> + data_phy_cycles = timing->lpx + timing->da_hs_prepare +
> + timing->da_hs_zero + timing->da_hs_exit + 2;
> +
> + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
> + if (vm->hfront_porch * dsi_tmp_buf_bpp >
> + data_phy_cycles * dsi->lanes + 18) {
> + horizontal_frontporch_byte = vm->hfront_porch *
> + dsi_tmp_buf_bpp -
> + data_phy_cycles *
> + dsi->lanes - 18;
> + } else {
> + DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
> + horizontal_frontporch_byte = vm->hfront_porch *
> + dsi_tmp_buf_bpp;
> + }
> + } else {
> + if (vm->hfront_porch * dsi_tmp_buf_bpp >
> + data_phy_cycles * dsi->lanes + 12) {
> + horizontal_frontporch_byte = vm->hfront_porch *
> + dsi_tmp_buf_bpp -
> + data_phy_cycles *
> + dsi->lanes - 12;
> + } else {
> + DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
> + horizontal_frontporch_byte = vm->hfront_porch *
> + dsi_tmp_buf_bpp;
> + }
> + }
>
> writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
> writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
> @@ -537,8 +598,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> {
> struct device *dev = dsi->host.dev;
> int ret;
> - u64 pixel_clock, total_bits;
> - u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
> + u32 bit_per_pixel;
>
> if (++dsi->refcount != 1)
> return 0;
> @@ -557,24 +617,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> break;
> }
>
> - /**
> - * htotal_time = htotal * byte_per_pixel / num_lanes
> - * overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit
> - * mipi_ratio = (htotal_time + overhead_time) / htotal_time
> - * data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes;
> - */
> - pixel_clock = dsi->vm.pixelclock;
> - htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch +
> - dsi->vm.hsync_len;
> - htotal_bits = htotal * bit_per_pixel;
> -
> - overhead_cycles = T_LPX + T_HS_PREP + T_HS_ZERO + T_HS_TRAIL +
> - T_HS_EXIT;
> - overhead_bits = overhead_cycles * dsi->lanes * 8;
> - total_bits = htotal_bits + overhead_bits;
> -
> - dsi->data_rate = DIV_ROUND_UP_ULL(pixel_clock * total_bits,
> - htotal * dsi->lanes);
> + dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
> + dsi->lanes);
>
> ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
> if (ret < 0) {
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v7 9/9] drm/mediatek: add dphy reset after setting lanes number
2019-09-19 6:58 ` [PATCH v7 9/9] drm/mediatek: add dphy reset after setting lanes number Jitao Shi
@ 2019-09-26 8:52 ` CK Hu
0 siblings, 0 replies; 21+ messages in thread
From: CK Hu @ 2019-09-26 8:52 UTC (permalink / raw)
To: Jitao Shi
Cc: srv_heupstream, David Airlie, stonea168, cawa.cheng, dri-devel,
sj.huang, linux-mediatek, Matthias Brugger, yingjoe.chen,
eddie.huang
Hi, Jitao:
On Thu, 2019-09-19 at 14:58 +0800, Jitao Shi wrote:
> Add dphy reset after setting lanes number to avoid dphy fifo effor.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index b02373b04848..8c2620ea18d0 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -37,6 +37,7 @@
> #define DSI_CON_CTRL 0x10
> #define DSI_RESET BIT(0)
> #define DSI_EN BIT(1)
> +#define DPHY_RESET BIT(2)
>
> #define DSI_MODE_CTRL 0x14
> #define MODE (3)
> @@ -280,6 +281,12 @@ static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
> mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
> }
>
> +static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi)
> +{
> + mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET);
> + mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, 0);
> +}
> +
> static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
> {
> mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
> @@ -650,6 +657,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> mtk_dsi_phy_timconfig(dsi);
>
> mtk_dsi_rxtx_control(dsi);
> + usleep_range(30, 100);
> + mtk_dsi_reset_dphy(dsi);
> mtk_dsi_ps_control_vact(dsi);
> mtk_dsi_set_vm_cmd(dsi);
> mtk_dsi_config_vdo_timing(dsi);
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v7 0/9] Support dsi for mt8183
2019-09-19 6:57 [PATCH v7 0/9] Support dsi for mt8183 Jitao Shi
` (8 preceding siblings ...)
2019-09-19 6:58 ` [PATCH v7 9/9] drm/mediatek: add dphy reset after setting lanes number Jitao Shi
@ 2019-09-27 1:35 ` CK Hu
9 siblings, 0 replies; 21+ messages in thread
From: CK Hu @ 2019-09-27 1:35 UTC (permalink / raw)
To: Jitao Shi
Cc: srv_heupstream, David Airlie, stonea168, cawa.cheng, dri-devel,
sj.huang, linux-mediatek, Matthias Brugger, yingjoe.chen,
eddie.huang
Hi, Jitao:
For this series, applied to mediatek-drm-next-5.5 [1], thanks.
[1]
https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.5
Regards,
CK
On Thu, 2019-09-19 at 14:57 +0800, Jitao Shi wrote:
> Changes since v6:
> - add dphy reset to avoid dphy fifo error after lines number setting
> - separate dsi cmd reg setting from "fixes CMDQ reg address of mt8173
> is different with mt2701"
>
> Changes since v5:
> - fine tune dphy timing.
>
> Changes since v4:
> - move mipi_dsi_host_unregiter() to .remove()
> - fine tune add frame size control coding style
> - change the data type of data_rate as u32, and add DIV_ROUND_UP_ULL
> - use div_u64 when 8000000000ULL / dsi->data_rate.
>
> Changes since v3
> - add one more 'tab' for bitwise define.
> - add Tested-by: Ryan Case <ryandcase@chromium.org>
> and Reviewed-by: CK Hu <ck.hu@mediatek.com>.
> - remove compare da_hs_zero to da_hs_prepare.
>
> Changes since v2:
> - change the video timing calc method
> - fine the dsi and mipitx init sequence
> - fine tune commit msg
>
> Changes since v1:
> - separate frame size and reg commit control independent patches.
> - fix some return values in probe
> - remove DSI_CMDW0 in "CMDQ reg address of mt8173 is different with mt2701"
>
> Jitao Shi (9):
> drm/mediatek: move mipi_dsi_host_register to probe
> drm/mediatek: fixes CMDQ reg address of mt8173 is different with
> mt2701
> drm/mediatek: replace writeb() with mtk_dsi_mask()
> drm/mediatek: add dsi reg commit disable control
> drm/mediatek: add frame size control
> drm/mediatek: add mt8183 dsi driver support
> drm/mediatek: change the dsi phytiming calculate method
> drm: mediatek: adjust dsi and mipi_tx probe sequence
> drm/mediatek: add dphy reset after setting lanes number
>
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +-
> drivers/gpu/drm/mediatek/mtk_dsi.c | 233 ++++++++++++++++++-------
> 2 files changed, 170 insertions(+), 65 deletions(-)
>
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v7 7/9] drm/mediatek: change the dsi phytiming calculate method
2019-09-26 8:51 ` CK Hu
@ 2019-12-12 13:53 ` Enric Balletbo Serra
0 siblings, 0 replies; 21+ messages in thread
From: Enric Balletbo Serra @ 2019-12-12 13:53 UTC (permalink / raw)
To: CK Hu
Cc: Nicolas Boichat, Jitao Shi, srv_heupstream, David Airlie,
stonea168, cawa cheng, dri-devel, sj.huang, Hsinyu Chao,
Ryan Case, Yingjoe Chen, Matthias Brugger,
moderated list:ARM/Mediatek SoC support,
Eddie Huang (黃智傑)
Hi,
Missatge de CK Hu <ck.hu@mediatek.com> del dia dj., 26 de set. 2019 a les 10:51:
>
> Hi, Jitao:
>
> On Thu, 2019-09-19 at 14:58 +0800, Jitao Shi wrote:
> > Change the method of frame rate calc which can get more accurate
> > frame rate.
> >
> > data rate = pixel_clock * bit_per_pixel / lanes
> > Adjust hfp_wc to adapt the additional phy_data
> >
> > if MIPI_DSI_MODE_VIDEO_BURST
> > hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12 - 6;
> > else
> > hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12;
> >
> > Note:
> > //(2: 1 for sync, 1 for phy idle)
> > data_phy_cycles = T_hs_exit + T_lpx + T_hs_prepare + T_hs_zero + 2;
> >
> > bpp: bit per pixel
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> >
> > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> > Tested-by: Ryan Case <ryandcase@chromium.org>
> > ---
> > drivers/gpu/drm/mediatek/mtk_dsi.c | 118 ++++++++++++++++++++---------
I didn't look in detail yet because looks like there is a lot of maths
involved, but this patch introduces a regression for MT8173 or my
board (Acer Chromebook R 13 - ELM). I need to revert this patch in
order to make the display working, basically, I don't see any error
but I only get a black screen. Reverting this patch fixes the issue
for me. If anyone knows what could be the problem I'd appreciate.
Thanks,
Enric
> > 1 file changed, 81 insertions(+), 37 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index b3676426aeb5..b02373b04848 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -136,12 +136,6 @@
> > #define DATA_0 (0xff << 16)
> > #define DATA_1 (0xff << 24)
> >
> > -#define T_LPX 5
> > -#define T_HS_PREP 6
> > -#define T_HS_TRAIL 8
> > -#define T_HS_EXIT 7
> > -#define T_HS_ZERO 10
> > -
> > #define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
> >
> > #define MTK_DSI_HOST_IS_READ(type) \
> > @@ -150,6 +144,25 @@
> > (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
> > (type == MIPI_DSI_DCS_READ))
> >
> > +struct mtk_phy_timing {
> > + u32 lpx;
> > + u32 da_hs_prepare;
> > + u32 da_hs_zero;
> > + u32 da_hs_trail;
> > +
> > + u32 ta_go;
> > + u32 ta_sure;
> > + u32 ta_get;
> > + u32 da_hs_exit;
> > +
> > + u32 clk_hs_zero;
> > + u32 clk_hs_trail;
> > +
> > + u32 clk_hs_prepare;
> > + u32 clk_hs_post;
> > + u32 clk_hs_exit;
> > +};
> > +
> > struct phy;
> >
> > struct mtk_dsi_driver_data {
> > @@ -180,6 +193,7 @@ struct mtk_dsi {
> > enum mipi_dsi_pixel_format format;
> > unsigned int lanes;
> > struct videomode vm;
> > + struct mtk_phy_timing phy_timing;
> > int refcount;
> > bool enabled;
> > u32 irq_data;
> > @@ -213,17 +227,36 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
> > {
> > u32 timcon0, timcon1, timcon2, timcon3;
> > u32 ui, cycle_time;
> > + struct mtk_phy_timing *timing = &dsi->phy_timing;
> > +
> > + ui = DIV_ROUND_UP(1000000000, dsi->data_rate);
> > + cycle_time = div_u64(8000000000ULL, dsi->data_rate);
> > +
> > + timing->lpx = NS_TO_CYCLE(60, cycle_time);
> > + timing->da_hs_prepare = NS_TO_CYCLE(50 + 5 * ui, cycle_time);
> > + timing->da_hs_zero = NS_TO_CYCLE(110 + 6 * ui, cycle_time);
> > + timing->da_hs_trail = NS_TO_CYCLE(77 + 4 * ui, cycle_time);
> >
> > - ui = 1000 / dsi->data_rate + 0x01;
> > - cycle_time = 8000 / dsi->data_rate + 0x01;
> > + timing->ta_go = 4 * timing->lpx;
> > + timing->ta_sure = 3 * timing->lpx / 2;
> > + timing->ta_get = 5 * timing->lpx;
> > + timing->da_hs_exit = 2 * timing->lpx;
> >
> > - timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
> > - timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 |
> > - T_HS_EXIT << 24;
> > - timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
> > - (NS_TO_CYCLE(0x150, cycle_time) << 16);
> > - timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 |
> > - NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
> > + timing->clk_hs_zero = NS_TO_CYCLE(336, cycle_time);
> > + timing->clk_hs_trail = NS_TO_CYCLE(100, cycle_time) + 10;
> > +
> > + timing->clk_hs_prepare = NS_TO_CYCLE(64, cycle_time);
> > + timing->clk_hs_post = NS_TO_CYCLE(80 + 52 * ui, cycle_time);
> > + timing->clk_hs_exit = 2 * timing->lpx;
> > +
> > + timcon0 = timing->lpx | timing->da_hs_prepare << 8 |
> > + timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
> > + timcon1 = timing->ta_go | timing->ta_sure << 8 |
> > + timing->ta_get << 16 | timing->da_hs_exit << 24;
> > + timcon2 = 1 << 8 | timing->clk_hs_zero << 16 |
> > + timing->clk_hs_trail << 24;
> > + timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 |
> > + timing->clk_hs_exit << 16;
> >
> > writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
> > writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
> > @@ -410,7 +443,8 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
> > u32 horizontal_sync_active_byte;
> > u32 horizontal_backporch_byte;
> > u32 horizontal_frontporch_byte;
> > - u32 dsi_tmp_buf_bpp;
> > + u32 dsi_tmp_buf_bpp, data_phy_cycles;
> > + struct mtk_phy_timing *timing = &dsi->phy_timing;
> >
> > struct videomode *vm = &dsi->vm;
> >
> > @@ -437,7 +471,34 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
> > horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
> > dsi_tmp_buf_bpp - 10);
> >
> > - horizontal_frontporch_byte = (vm->hfront_porch * dsi_tmp_buf_bpp - 12);
> > + data_phy_cycles = timing->lpx + timing->da_hs_prepare +
> > + timing->da_hs_zero + timing->da_hs_exit + 2;
> > +
> > + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
> > + if (vm->hfront_porch * dsi_tmp_buf_bpp >
> > + data_phy_cycles * dsi->lanes + 18) {
> > + horizontal_frontporch_byte = vm->hfront_porch *
> > + dsi_tmp_buf_bpp -
> > + data_phy_cycles *
> > + dsi->lanes - 18;
> > + } else {
> > + DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
> > + horizontal_frontporch_byte = vm->hfront_porch *
> > + dsi_tmp_buf_bpp;
> > + }
> > + } else {
> > + if (vm->hfront_porch * dsi_tmp_buf_bpp >
> > + data_phy_cycles * dsi->lanes + 12) {
> > + horizontal_frontporch_byte = vm->hfront_porch *
> > + dsi_tmp_buf_bpp -
> > + data_phy_cycles *
> > + dsi->lanes - 12;
> > + } else {
> > + DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
> > + horizontal_frontporch_byte = vm->hfront_porch *
> > + dsi_tmp_buf_bpp;
> > + }
> > + }
> >
> > writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
> > writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
> > @@ -537,8 +598,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> > {
> > struct device *dev = dsi->host.dev;
> > int ret;
> > - u64 pixel_clock, total_bits;
> > - u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
> > + u32 bit_per_pixel;
> >
> > if (++dsi->refcount != 1)
> > return 0;
> > @@ -557,24 +617,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> > break;
> > }
> >
> > - /**
> > - * htotal_time = htotal * byte_per_pixel / num_lanes
> > - * overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit
> > - * mipi_ratio = (htotal_time + overhead_time) / htotal_time
> > - * data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes;
> > - */
> > - pixel_clock = dsi->vm.pixelclock;
> > - htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch +
> > - dsi->vm.hsync_len;
> > - htotal_bits = htotal * bit_per_pixel;
> > -
> > - overhead_cycles = T_LPX + T_HS_PREP + T_HS_ZERO + T_HS_TRAIL +
> > - T_HS_EXIT;
> > - overhead_bits = overhead_cycles * dsi->lanes * 8;
> > - total_bits = htotal_bits + overhead_bits;
> > -
> > - dsi->data_rate = DIV_ROUND_UP_ULL(pixel_clock * total_bits,
> > - htotal * dsi->lanes);
> > + dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
> > + dsi->lanes);
> >
> > ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
> > if (ret < 0) {
>
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v7 7/9] drm/mediatek: change the dsi phytiming calculate method
@ 2019-12-12 13:53 ` Enric Balletbo Serra
0 siblings, 0 replies; 21+ messages in thread
From: Enric Balletbo Serra @ 2019-12-12 13:53 UTC (permalink / raw)
To: CK Hu
Cc: Nicolas Boichat, Jitao Shi, srv_heupstream, David Airlie,
stonea168, cawa cheng, dri-devel, sj.huang, Hsinyu Chao,
Ryan Case, Yingjoe Chen, Matthias Brugger,
moderated list:ARM/Mediatek SoC support,
Eddie Huang (黃智傑)
Hi,
Missatge de CK Hu <ck.hu@mediatek.com> del dia dj., 26 de set. 2019 a les 10:51:
>
> Hi, Jitao:
>
> On Thu, 2019-09-19 at 14:58 +0800, Jitao Shi wrote:
> > Change the method of frame rate calc which can get more accurate
> > frame rate.
> >
> > data rate = pixel_clock * bit_per_pixel / lanes
> > Adjust hfp_wc to adapt the additional phy_data
> >
> > if MIPI_DSI_MODE_VIDEO_BURST
> > hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12 - 6;
> > else
> > hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12;
> >
> > Note:
> > //(2: 1 for sync, 1 for phy idle)
> > data_phy_cycles = T_hs_exit + T_lpx + T_hs_prepare + T_hs_zero + 2;
> >
> > bpp: bit per pixel
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> >
> > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> > Tested-by: Ryan Case <ryandcase@chromium.org>
> > ---
> > drivers/gpu/drm/mediatek/mtk_dsi.c | 118 ++++++++++++++++++++---------
I didn't look in detail yet because looks like there is a lot of maths
involved, but this patch introduces a regression for MT8173 or my
board (Acer Chromebook R 13 - ELM). I need to revert this patch in
order to make the display working, basically, I don't see any error
but I only get a black screen. Reverting this patch fixes the issue
for me. If anyone knows what could be the problem I'd appreciate.
Thanks,
Enric
> > 1 file changed, 81 insertions(+), 37 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index b3676426aeb5..b02373b04848 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -136,12 +136,6 @@
> > #define DATA_0 (0xff << 16)
> > #define DATA_1 (0xff << 24)
> >
> > -#define T_LPX 5
> > -#define T_HS_PREP 6
> > -#define T_HS_TRAIL 8
> > -#define T_HS_EXIT 7
> > -#define T_HS_ZERO 10
> > -
> > #define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
> >
> > #define MTK_DSI_HOST_IS_READ(type) \
> > @@ -150,6 +144,25 @@
> > (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
> > (type == MIPI_DSI_DCS_READ))
> >
> > +struct mtk_phy_timing {
> > + u32 lpx;
> > + u32 da_hs_prepare;
> > + u32 da_hs_zero;
> > + u32 da_hs_trail;
> > +
> > + u32 ta_go;
> > + u32 ta_sure;
> > + u32 ta_get;
> > + u32 da_hs_exit;
> > +
> > + u32 clk_hs_zero;
> > + u32 clk_hs_trail;
> > +
> > + u32 clk_hs_prepare;
> > + u32 clk_hs_post;
> > + u32 clk_hs_exit;
> > +};
> > +
> > struct phy;
> >
> > struct mtk_dsi_driver_data {
> > @@ -180,6 +193,7 @@ struct mtk_dsi {
> > enum mipi_dsi_pixel_format format;
> > unsigned int lanes;
> > struct videomode vm;
> > + struct mtk_phy_timing phy_timing;
> > int refcount;
> > bool enabled;
> > u32 irq_data;
> > @@ -213,17 +227,36 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
> > {
> > u32 timcon0, timcon1, timcon2, timcon3;
> > u32 ui, cycle_time;
> > + struct mtk_phy_timing *timing = &dsi->phy_timing;
> > +
> > + ui = DIV_ROUND_UP(1000000000, dsi->data_rate);
> > + cycle_time = div_u64(8000000000ULL, dsi->data_rate);
> > +
> > + timing->lpx = NS_TO_CYCLE(60, cycle_time);
> > + timing->da_hs_prepare = NS_TO_CYCLE(50 + 5 * ui, cycle_time);
> > + timing->da_hs_zero = NS_TO_CYCLE(110 + 6 * ui, cycle_time);
> > + timing->da_hs_trail = NS_TO_CYCLE(77 + 4 * ui, cycle_time);
> >
> > - ui = 1000 / dsi->data_rate + 0x01;
> > - cycle_time = 8000 / dsi->data_rate + 0x01;
> > + timing->ta_go = 4 * timing->lpx;
> > + timing->ta_sure = 3 * timing->lpx / 2;
> > + timing->ta_get = 5 * timing->lpx;
> > + timing->da_hs_exit = 2 * timing->lpx;
> >
> > - timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
> > - timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 |
> > - T_HS_EXIT << 24;
> > - timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
> > - (NS_TO_CYCLE(0x150, cycle_time) << 16);
> > - timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 |
> > - NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
> > + timing->clk_hs_zero = NS_TO_CYCLE(336, cycle_time);
> > + timing->clk_hs_trail = NS_TO_CYCLE(100, cycle_time) + 10;
> > +
> > + timing->clk_hs_prepare = NS_TO_CYCLE(64, cycle_time);
> > + timing->clk_hs_post = NS_TO_CYCLE(80 + 52 * ui, cycle_time);
> > + timing->clk_hs_exit = 2 * timing->lpx;
> > +
> > + timcon0 = timing->lpx | timing->da_hs_prepare << 8 |
> > + timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
> > + timcon1 = timing->ta_go | timing->ta_sure << 8 |
> > + timing->ta_get << 16 | timing->da_hs_exit << 24;
> > + timcon2 = 1 << 8 | timing->clk_hs_zero << 16 |
> > + timing->clk_hs_trail << 24;
> > + timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 |
> > + timing->clk_hs_exit << 16;
> >
> > writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
> > writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
> > @@ -410,7 +443,8 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
> > u32 horizontal_sync_active_byte;
> > u32 horizontal_backporch_byte;
> > u32 horizontal_frontporch_byte;
> > - u32 dsi_tmp_buf_bpp;
> > + u32 dsi_tmp_buf_bpp, data_phy_cycles;
> > + struct mtk_phy_timing *timing = &dsi->phy_timing;
> >
> > struct videomode *vm = &dsi->vm;
> >
> > @@ -437,7 +471,34 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
> > horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
> > dsi_tmp_buf_bpp - 10);
> >
> > - horizontal_frontporch_byte = (vm->hfront_porch * dsi_tmp_buf_bpp - 12);
> > + data_phy_cycles = timing->lpx + timing->da_hs_prepare +
> > + timing->da_hs_zero + timing->da_hs_exit + 2;
> > +
> > + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
> > + if (vm->hfront_porch * dsi_tmp_buf_bpp >
> > + data_phy_cycles * dsi->lanes + 18) {
> > + horizontal_frontporch_byte = vm->hfront_porch *
> > + dsi_tmp_buf_bpp -
> > + data_phy_cycles *
> > + dsi->lanes - 18;
> > + } else {
> > + DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
> > + horizontal_frontporch_byte = vm->hfront_porch *
> > + dsi_tmp_buf_bpp;
> > + }
> > + } else {
> > + if (vm->hfront_porch * dsi_tmp_buf_bpp >
> > + data_phy_cycles * dsi->lanes + 12) {
> > + horizontal_frontporch_byte = vm->hfront_porch *
> > + dsi_tmp_buf_bpp -
> > + data_phy_cycles *
> > + dsi->lanes - 12;
> > + } else {
> > + DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
> > + horizontal_frontporch_byte = vm->hfront_porch *
> > + dsi_tmp_buf_bpp;
> > + }
> > + }
> >
> > writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
> > writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
> > @@ -537,8 +598,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> > {
> > struct device *dev = dsi->host.dev;
> > int ret;
> > - u64 pixel_clock, total_bits;
> > - u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
> > + u32 bit_per_pixel;
> >
> > if (++dsi->refcount != 1)
> > return 0;
> > @@ -557,24 +617,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> > break;
> > }
> >
> > - /**
> > - * htotal_time = htotal * byte_per_pixel / num_lanes
> > - * overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit
> > - * mipi_ratio = (htotal_time + overhead_time) / htotal_time
> > - * data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes;
> > - */
> > - pixel_clock = dsi->vm.pixelclock;
> > - htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch +
> > - dsi->vm.hsync_len;
> > - htotal_bits = htotal * bit_per_pixel;
> > -
> > - overhead_cycles = T_LPX + T_HS_PREP + T_HS_ZERO + T_HS_TRAIL +
> > - T_HS_EXIT;
> > - overhead_bits = overhead_cycles * dsi->lanes * 8;
> > - total_bits = htotal_bits + overhead_bits;
> > -
> > - dsi->data_rate = DIV_ROUND_UP_ULL(pixel_clock * total_bits,
> > - htotal * dsi->lanes);
> > + dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
> > + dsi->lanes);
> >
> > ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
> > if (ret < 0) {
>
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v7 7/9] drm/mediatek: change the dsi phytiming calculate method
2019-12-12 13:53 ` Enric Balletbo Serra
@ 2019-12-12 22:47 ` Ryan Case
-1 siblings, 0 replies; 21+ messages in thread
From: Ryan Case @ 2019-12-12 22:47 UTC (permalink / raw)
To: Enric Balletbo Serra
Cc: Nicolas Boichat, Jitao Shi, srv_heupstream, David Airlie,
stonea168, cawa cheng, dri-devel, Matthias Brugger, sj.huang,
Hsinyu Chao, moderated list:ARM/Mediatek SoC support, CK Hu,
Yingjoe Chen, Eddie Huang (黃智傑)
Hi Enric,
On Thu, Dec 12, 2019 at 5:53 AM Enric Balletbo Serra
<eballetbo@gmail.com> wrote:
>
> Hi,
>
> Missatge de CK Hu <ck.hu@mediatek.com> del dia dj., 26 de set. 2019 a les 10:51:
> >
> > Hi, Jitao:
> >
> > On Thu, 2019-09-19 at 14:58 +0800, Jitao Shi wrote:
> > > Change the method of frame rate calc which can get more accurate
> > > frame rate.
> > >
> > > data rate = pixel_clock * bit_per_pixel / lanes
> > > Adjust hfp_wc to adapt the additional phy_data
> > >
> > > if MIPI_DSI_MODE_VIDEO_BURST
> > > hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12 - 6;
> > > else
> > > hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12;
> > >
> > > Note:
> > > //(2: 1 for sync, 1 for phy idle)
> > > data_phy_cycles = T_hs_exit + T_lpx + T_hs_prepare + T_hs_zero + 2;
> > >
> > > bpp: bit per pixel
> >
> > Reviewed-by: CK Hu <ck.hu@mediatek.com>
> >
> > >
> > > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> > > Tested-by: Ryan Case <ryandcase@chromium.org>
> > > ---
> > > drivers/gpu/drm/mediatek/mtk_dsi.c | 118 ++++++++++++++++++++---------
>
> I didn't look in detail yet because looks like there is a lot of maths
> involved, but this patch introduces a regression for MT8173 or my
> board (Acer Chromebook R 13 - ELM). I need to revert this patch in
> order to make the display working, basically, I don't see any error
> but I only get a black screen. Reverting this patch fixes the issue
> for me. If anyone knows what could be the problem I'd appreciate.
I won't pretend to be aware of current status but an in progress patch
with updated timings that have been tested on elm can be found here:
https://crrev.com/c/1915442
- ryan
>
> Thanks,
> Enric
>
> > > 1 file changed, 81 insertions(+), 37 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > index b3676426aeb5..b02373b04848 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > @@ -136,12 +136,6 @@
> > > #define DATA_0 (0xff << 16)
> > > #define DATA_1 (0xff << 24)
> > >
> > > -#define T_LPX 5
> > > -#define T_HS_PREP 6
> > > -#define T_HS_TRAIL 8
> > > -#define T_HS_EXIT 7
> > > -#define T_HS_ZERO 10
> > > -
> > > #define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
> > >
> > > #define MTK_DSI_HOST_IS_READ(type) \
> > > @@ -150,6 +144,25 @@
> > > (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
> > > (type == MIPI_DSI_DCS_READ))
> > >
> > > +struct mtk_phy_timing {
> > > + u32 lpx;
> > > + u32 da_hs_prepare;
> > > + u32 da_hs_zero;
> > > + u32 da_hs_trail;
> > > +
> > > + u32 ta_go;
> > > + u32 ta_sure;
> > > + u32 ta_get;
> > > + u32 da_hs_exit;
> > > +
> > > + u32 clk_hs_zero;
> > > + u32 clk_hs_trail;
> > > +
> > > + u32 clk_hs_prepare;
> > > + u32 clk_hs_post;
> > > + u32 clk_hs_exit;
> > > +};
> > > +
> > > struct phy;
> > >
> > > struct mtk_dsi_driver_data {
> > > @@ -180,6 +193,7 @@ struct mtk_dsi {
> > > enum mipi_dsi_pixel_format format;
> > > unsigned int lanes;
> > > struct videomode vm;
> > > + struct mtk_phy_timing phy_timing;
> > > int refcount;
> > > bool enabled;
> > > u32 irq_data;
> > > @@ -213,17 +227,36 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
> > > {
> > > u32 timcon0, timcon1, timcon2, timcon3;
> > > u32 ui, cycle_time;
> > > + struct mtk_phy_timing *timing = &dsi->phy_timing;
> > > +
> > > + ui = DIV_ROUND_UP(1000000000, dsi->data_rate);
> > > + cycle_time = div_u64(8000000000ULL, dsi->data_rate);
> > > +
> > > + timing->lpx = NS_TO_CYCLE(60, cycle_time);
> > > + timing->da_hs_prepare = NS_TO_CYCLE(50 + 5 * ui, cycle_time);
> > > + timing->da_hs_zero = NS_TO_CYCLE(110 + 6 * ui, cycle_time);
> > > + timing->da_hs_trail = NS_TO_CYCLE(77 + 4 * ui, cycle_time);
> > >
> > > - ui = 1000 / dsi->data_rate + 0x01;
> > > - cycle_time = 8000 / dsi->data_rate + 0x01;
> > > + timing->ta_go = 4 * timing->lpx;
> > > + timing->ta_sure = 3 * timing->lpx / 2;
> > > + timing->ta_get = 5 * timing->lpx;
> > > + timing->da_hs_exit = 2 * timing->lpx;
> > >
> > > - timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
> > > - timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 |
> > > - T_HS_EXIT << 24;
> > > - timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
> > > - (NS_TO_CYCLE(0x150, cycle_time) << 16);
> > > - timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 |
> > > - NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
> > > + timing->clk_hs_zero = NS_TO_CYCLE(336, cycle_time);
> > > + timing->clk_hs_trail = NS_TO_CYCLE(100, cycle_time) + 10;
> > > +
> > > + timing->clk_hs_prepare = NS_TO_CYCLE(64, cycle_time);
> > > + timing->clk_hs_post = NS_TO_CYCLE(80 + 52 * ui, cycle_time);
> > > + timing->clk_hs_exit = 2 * timing->lpx;
> > > +
> > > + timcon0 = timing->lpx | timing->da_hs_prepare << 8 |
> > > + timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
> > > + timcon1 = timing->ta_go | timing->ta_sure << 8 |
> > > + timing->ta_get << 16 | timing->da_hs_exit << 24;
> > > + timcon2 = 1 << 8 | timing->clk_hs_zero << 16 |
> > > + timing->clk_hs_trail << 24;
> > > + timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 |
> > > + timing->clk_hs_exit << 16;
> > >
> > > writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
> > > writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
> > > @@ -410,7 +443,8 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
> > > u32 horizontal_sync_active_byte;
> > > u32 horizontal_backporch_byte;
> > > u32 horizontal_frontporch_byte;
> > > - u32 dsi_tmp_buf_bpp;
> > > + u32 dsi_tmp_buf_bpp, data_phy_cycles;
> > > + struct mtk_phy_timing *timing = &dsi->phy_timing;
> > >
> > > struct videomode *vm = &dsi->vm;
> > >
> > > @@ -437,7 +471,34 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
> > > horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
> > > dsi_tmp_buf_bpp - 10);
> > >
> > > - horizontal_frontporch_byte = (vm->hfront_porch * dsi_tmp_buf_bpp - 12);
> > > + data_phy_cycles = timing->lpx + timing->da_hs_prepare +
> > > + timing->da_hs_zero + timing->da_hs_exit + 2;
> > > +
> > > + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
> > > + if (vm->hfront_porch * dsi_tmp_buf_bpp >
> > > + data_phy_cycles * dsi->lanes + 18) {
> > > + horizontal_frontporch_byte = vm->hfront_porch *
> > > + dsi_tmp_buf_bpp -
> > > + data_phy_cycles *
> > > + dsi->lanes - 18;
> > > + } else {
> > > + DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
> > > + horizontal_frontporch_byte = vm->hfront_porch *
> > > + dsi_tmp_buf_bpp;
> > > + }
> > > + } else {
> > > + if (vm->hfront_porch * dsi_tmp_buf_bpp >
> > > + data_phy_cycles * dsi->lanes + 12) {
> > > + horizontal_frontporch_byte = vm->hfront_porch *
> > > + dsi_tmp_buf_bpp -
> > > + data_phy_cycles *
> > > + dsi->lanes - 12;
> > > + } else {
> > > + DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
> > > + horizontal_frontporch_byte = vm->hfront_porch *
> > > + dsi_tmp_buf_bpp;
> > > + }
> > > + }
> > >
> > > writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
> > > writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
> > > @@ -537,8 +598,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> > > {
> > > struct device *dev = dsi->host.dev;
> > > int ret;
> > > - u64 pixel_clock, total_bits;
> > > - u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
> > > + u32 bit_per_pixel;
> > >
> > > if (++dsi->refcount != 1)
> > > return 0;
> > > @@ -557,24 +617,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> > > break;
> > > }
> > >
> > > - /**
> > > - * htotal_time = htotal * byte_per_pixel / num_lanes
> > > - * overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit
> > > - * mipi_ratio = (htotal_time + overhead_time) / htotal_time
> > > - * data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes;
> > > - */
> > > - pixel_clock = dsi->vm.pixelclock;
> > > - htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch +
> > > - dsi->vm.hsync_len;
> > > - htotal_bits = htotal * bit_per_pixel;
> > > -
> > > - overhead_cycles = T_LPX + T_HS_PREP + T_HS_ZERO + T_HS_TRAIL +
> > > - T_HS_EXIT;
> > > - overhead_bits = overhead_cycles * dsi->lanes * 8;
> > > - total_bits = htotal_bits + overhead_bits;
> > > -
> > > - dsi->data_rate = DIV_ROUND_UP_ULL(pixel_clock * total_bits,
> > > - htotal * dsi->lanes);
> > > + dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
> > > + dsi->lanes);
> > >
> > > ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
> > > if (ret < 0) {
> >
> >
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v7 7/9] drm/mediatek: change the dsi phytiming calculate method
@ 2019-12-12 22:47 ` Ryan Case
0 siblings, 0 replies; 21+ messages in thread
From: Ryan Case @ 2019-12-12 22:47 UTC (permalink / raw)
To: Enric Balletbo Serra
Cc: Nicolas Boichat, Jitao Shi, srv_heupstream, David Airlie,
stonea168, cawa cheng, dri-devel, Matthias Brugger, sj.huang,
Hsinyu Chao, moderated list:ARM/Mediatek SoC support,
Yingjoe Chen, Eddie Huang (黃智傑)
Hi Enric,
On Thu, Dec 12, 2019 at 5:53 AM Enric Balletbo Serra
<eballetbo@gmail.com> wrote:
>
> Hi,
>
> Missatge de CK Hu <ck.hu@mediatek.com> del dia dj., 26 de set. 2019 a les 10:51:
> >
> > Hi, Jitao:
> >
> > On Thu, 2019-09-19 at 14:58 +0800, Jitao Shi wrote:
> > > Change the method of frame rate calc which can get more accurate
> > > frame rate.
> > >
> > > data rate = pixel_clock * bit_per_pixel / lanes
> > > Adjust hfp_wc to adapt the additional phy_data
> > >
> > > if MIPI_DSI_MODE_VIDEO_BURST
> > > hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12 - 6;
> > > else
> > > hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12;
> > >
> > > Note:
> > > //(2: 1 for sync, 1 for phy idle)
> > > data_phy_cycles = T_hs_exit + T_lpx + T_hs_prepare + T_hs_zero + 2;
> > >
> > > bpp: bit per pixel
> >
> > Reviewed-by: CK Hu <ck.hu@mediatek.com>
> >
> > >
> > > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> > > Tested-by: Ryan Case <ryandcase@chromium.org>
> > > ---
> > > drivers/gpu/drm/mediatek/mtk_dsi.c | 118 ++++++++++++++++++++---------
>
> I didn't look in detail yet because looks like there is a lot of maths
> involved, but this patch introduces a regression for MT8173 or my
> board (Acer Chromebook R 13 - ELM). I need to revert this patch in
> order to make the display working, basically, I don't see any error
> but I only get a black screen. Reverting this patch fixes the issue
> for me. If anyone knows what could be the problem I'd appreciate.
I won't pretend to be aware of current status but an in progress patch
with updated timings that have been tested on elm can be found here:
https://crrev.com/c/1915442
- ryan
>
> Thanks,
> Enric
>
> > > 1 file changed, 81 insertions(+), 37 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > index b3676426aeb5..b02373b04848 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > @@ -136,12 +136,6 @@
> > > #define DATA_0 (0xff << 16)
> > > #define DATA_1 (0xff << 24)
> > >
> > > -#define T_LPX 5
> > > -#define T_HS_PREP 6
> > > -#define T_HS_TRAIL 8
> > > -#define T_HS_EXIT 7
> > > -#define T_HS_ZERO 10
> > > -
> > > #define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
> > >
> > > #define MTK_DSI_HOST_IS_READ(type) \
> > > @@ -150,6 +144,25 @@
> > > (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
> > > (type == MIPI_DSI_DCS_READ))
> > >
> > > +struct mtk_phy_timing {
> > > + u32 lpx;
> > > + u32 da_hs_prepare;
> > > + u32 da_hs_zero;
> > > + u32 da_hs_trail;
> > > +
> > > + u32 ta_go;
> > > + u32 ta_sure;
> > > + u32 ta_get;
> > > + u32 da_hs_exit;
> > > +
> > > + u32 clk_hs_zero;
> > > + u32 clk_hs_trail;
> > > +
> > > + u32 clk_hs_prepare;
> > > + u32 clk_hs_post;
> > > + u32 clk_hs_exit;
> > > +};
> > > +
> > > struct phy;
> > >
> > > struct mtk_dsi_driver_data {
> > > @@ -180,6 +193,7 @@ struct mtk_dsi {
> > > enum mipi_dsi_pixel_format format;
> > > unsigned int lanes;
> > > struct videomode vm;
> > > + struct mtk_phy_timing phy_timing;
> > > int refcount;
> > > bool enabled;
> > > u32 irq_data;
> > > @@ -213,17 +227,36 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
> > > {
> > > u32 timcon0, timcon1, timcon2, timcon3;
> > > u32 ui, cycle_time;
> > > + struct mtk_phy_timing *timing = &dsi->phy_timing;
> > > +
> > > + ui = DIV_ROUND_UP(1000000000, dsi->data_rate);
> > > + cycle_time = div_u64(8000000000ULL, dsi->data_rate);
> > > +
> > > + timing->lpx = NS_TO_CYCLE(60, cycle_time);
> > > + timing->da_hs_prepare = NS_TO_CYCLE(50 + 5 * ui, cycle_time);
> > > + timing->da_hs_zero = NS_TO_CYCLE(110 + 6 * ui, cycle_time);
> > > + timing->da_hs_trail = NS_TO_CYCLE(77 + 4 * ui, cycle_time);
> > >
> > > - ui = 1000 / dsi->data_rate + 0x01;
> > > - cycle_time = 8000 / dsi->data_rate + 0x01;
> > > + timing->ta_go = 4 * timing->lpx;
> > > + timing->ta_sure = 3 * timing->lpx / 2;
> > > + timing->ta_get = 5 * timing->lpx;
> > > + timing->da_hs_exit = 2 * timing->lpx;
> > >
> > > - timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
> > > - timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 |
> > > - T_HS_EXIT << 24;
> > > - timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
> > > - (NS_TO_CYCLE(0x150, cycle_time) << 16);
> > > - timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 |
> > > - NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
> > > + timing->clk_hs_zero = NS_TO_CYCLE(336, cycle_time);
> > > + timing->clk_hs_trail = NS_TO_CYCLE(100, cycle_time) + 10;
> > > +
> > > + timing->clk_hs_prepare = NS_TO_CYCLE(64, cycle_time);
> > > + timing->clk_hs_post = NS_TO_CYCLE(80 + 52 * ui, cycle_time);
> > > + timing->clk_hs_exit = 2 * timing->lpx;
> > > +
> > > + timcon0 = timing->lpx | timing->da_hs_prepare << 8 |
> > > + timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
> > > + timcon1 = timing->ta_go | timing->ta_sure << 8 |
> > > + timing->ta_get << 16 | timing->da_hs_exit << 24;
> > > + timcon2 = 1 << 8 | timing->clk_hs_zero << 16 |
> > > + timing->clk_hs_trail << 24;
> > > + timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 |
> > > + timing->clk_hs_exit << 16;
> > >
> > > writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
> > > writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
> > > @@ -410,7 +443,8 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
> > > u32 horizontal_sync_active_byte;
> > > u32 horizontal_backporch_byte;
> > > u32 horizontal_frontporch_byte;
> > > - u32 dsi_tmp_buf_bpp;
> > > + u32 dsi_tmp_buf_bpp, data_phy_cycles;
> > > + struct mtk_phy_timing *timing = &dsi->phy_timing;
> > >
> > > struct videomode *vm = &dsi->vm;
> > >
> > > @@ -437,7 +471,34 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
> > > horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
> > > dsi_tmp_buf_bpp - 10);
> > >
> > > - horizontal_frontporch_byte = (vm->hfront_porch * dsi_tmp_buf_bpp - 12);
> > > + data_phy_cycles = timing->lpx + timing->da_hs_prepare +
> > > + timing->da_hs_zero + timing->da_hs_exit + 2;
> > > +
> > > + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
> > > + if (vm->hfront_porch * dsi_tmp_buf_bpp >
> > > + data_phy_cycles * dsi->lanes + 18) {
> > > + horizontal_frontporch_byte = vm->hfront_porch *
> > > + dsi_tmp_buf_bpp -
> > > + data_phy_cycles *
> > > + dsi->lanes - 18;
> > > + } else {
> > > + DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
> > > + horizontal_frontporch_byte = vm->hfront_porch *
> > > + dsi_tmp_buf_bpp;
> > > + }
> > > + } else {
> > > + if (vm->hfront_porch * dsi_tmp_buf_bpp >
> > > + data_phy_cycles * dsi->lanes + 12) {
> > > + horizontal_frontporch_byte = vm->hfront_porch *
> > > + dsi_tmp_buf_bpp -
> > > + data_phy_cycles *
> > > + dsi->lanes - 12;
> > > + } else {
> > > + DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
> > > + horizontal_frontporch_byte = vm->hfront_porch *
> > > + dsi_tmp_buf_bpp;
> > > + }
> > > + }
> > >
> > > writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
> > > writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
> > > @@ -537,8 +598,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> > > {
> > > struct device *dev = dsi->host.dev;
> > > int ret;
> > > - u64 pixel_clock, total_bits;
> > > - u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
> > > + u32 bit_per_pixel;
> > >
> > > if (++dsi->refcount != 1)
> > > return 0;
> > > @@ -557,24 +617,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> > > break;
> > > }
> > >
> > > - /**
> > > - * htotal_time = htotal * byte_per_pixel / num_lanes
> > > - * overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit
> > > - * mipi_ratio = (htotal_time + overhead_time) / htotal_time
> > > - * data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes;
> > > - */
> > > - pixel_clock = dsi->vm.pixelclock;
> > > - htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch +
> > > - dsi->vm.hsync_len;
> > > - htotal_bits = htotal * bit_per_pixel;
> > > -
> > > - overhead_cycles = T_LPX + T_HS_PREP + T_HS_ZERO + T_HS_TRAIL +
> > > - T_HS_EXIT;
> > > - overhead_bits = overhead_cycles * dsi->lanes * 8;
> > > - total_bits = htotal_bits + overhead_bits;
> > > -
> > > - dsi->data_rate = DIV_ROUND_UP_ULL(pixel_clock * total_bits,
> > > - htotal * dsi->lanes);
> > > + dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
> > > + dsi->lanes);
> > >
> > > ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
> > > if (ret < 0) {
> >
> >
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v7 7/9] drm/mediatek: change the dsi phytiming calculate method
2019-12-12 22:47 ` Ryan Case
@ 2019-12-13 2:45 ` CK Hu
-1 siblings, 0 replies; 21+ messages in thread
From: CK Hu @ 2019-12-13 2:45 UTC (permalink / raw)
To: Ryan Case
Cc: Nicolas Boichat, Jitao Shi, srv_heupstream, Enric Balletbo Serra,
stonea168, cawa cheng, dri-devel, David Airlie, sj.huang,
Hsinyu Chao, moderated list:ARM/Mediatek SoC support,
Matthias Brugger, Yingjoe Chen,
Eddie Huang (黃智傑)
Hi, Ryan:
On Thu, 2019-12-12 at 14:47 -0800, Ryan Case wrote:
> Hi Enric,
>
> On Thu, Dec 12, 2019 at 5:53 AM Enric Balletbo Serra
> <eballetbo@gmail.com> wrote:
> >
> > Hi,
> >
> > Missatge de CK Hu <ck.hu@mediatek.com> del dia dj., 26 de set. 2019 a les 10:51:
> > >
> > > Hi, Jitao:
> > >
> > > On Thu, 2019-09-19 at 14:58 +0800, Jitao Shi wrote:
> > > > Change the method of frame rate calc which can get more accurate
> > > > frame rate.
> > > >
> > > > data rate = pixel_clock * bit_per_pixel / lanes
> > > > Adjust hfp_wc to adapt the additional phy_data
> > > >
> > > > if MIPI_DSI_MODE_VIDEO_BURST
> > > > hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12 - 6;
> > > > else
> > > > hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12;
> > > >
> > > > Note:
> > > > //(2: 1 for sync, 1 for phy idle)
> > > > data_phy_cycles = T_hs_exit + T_lpx + T_hs_prepare + T_hs_zero + 2;
> > > >
> > > > bpp: bit per pixel
> > >
> > > Reviewed-by: CK Hu <ck.hu@mediatek.com>
> > >
> > > >
> > > > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> > > > Tested-by: Ryan Case <ryandcase@chromium.org>
> > > > ---
> > > > drivers/gpu/drm/mediatek/mtk_dsi.c | 118 ++++++++++++++++++++---------
> >
> > I didn't look in detail yet because looks like there is a lot of maths
> > involved, but this patch introduces a regression for MT8173 or my
> > board (Acer Chromebook R 13 - ELM). I need to revert this patch in
> > order to make the display working, basically, I don't see any error
> > but I only get a black screen. Reverting this patch fixes the issue
> > for me. If anyone knows what could be the problem I'd appreciate.
>
> I won't pretend to be aware of current status but an in progress patch
> with updated timings that have been tested on elm can be found here:
> https://crrev.com/c/1915442
>
It seems that patch works fine in elm, so I would wait for the fixup
patch in rc stage. Otherwise, I would revert this patch.
Regards,
CK
> - ryan
>
> >
> > Thanks,
> > Enric
> >
> > > > 1 file changed, 81 insertions(+), 37 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > > index b3676426aeb5..b02373b04848 100644
> > > > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > > @@ -136,12 +136,6 @@
> > > > #define DATA_0 (0xff << 16)
> > > > #define DATA_1 (0xff << 24)
> > > >
> > > > -#define T_LPX 5
> > > > -#define T_HS_PREP 6
> > > > -#define T_HS_TRAIL 8
> > > > -#define T_HS_EXIT 7
> > > > -#define T_HS_ZERO 10
> > > > -
> > > > #define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
> > > >
> > > > #define MTK_DSI_HOST_IS_READ(type) \
> > > > @@ -150,6 +144,25 @@
> > > > (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
> > > > (type == MIPI_DSI_DCS_READ))
> > > >
> > > > +struct mtk_phy_timing {
> > > > + u32 lpx;
> > > > + u32 da_hs_prepare;
> > > > + u32 da_hs_zero;
> > > > + u32 da_hs_trail;
> > > > +
> > > > + u32 ta_go;
> > > > + u32 ta_sure;
> > > > + u32 ta_get;
> > > > + u32 da_hs_exit;
> > > > +
> > > > + u32 clk_hs_zero;
> > > > + u32 clk_hs_trail;
> > > > +
> > > > + u32 clk_hs_prepare;
> > > > + u32 clk_hs_post;
> > > > + u32 clk_hs_exit;
> > > > +};
> > > > +
> > > > struct phy;
> > > >
> > > > struct mtk_dsi_driver_data {
> > > > @@ -180,6 +193,7 @@ struct mtk_dsi {
> > > > enum mipi_dsi_pixel_format format;
> > > > unsigned int lanes;
> > > > struct videomode vm;
> > > > + struct mtk_phy_timing phy_timing;
> > > > int refcount;
> > > > bool enabled;
> > > > u32 irq_data;
> > > > @@ -213,17 +227,36 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
> > > > {
> > > > u32 timcon0, timcon1, timcon2, timcon3;
> > > > u32 ui, cycle_time;
> > > > + struct mtk_phy_timing *timing = &dsi->phy_timing;
> > > > +
> > > > + ui = DIV_ROUND_UP(1000000000, dsi->data_rate);
> > > > + cycle_time = div_u64(8000000000ULL, dsi->data_rate);
> > > > +
> > > > + timing->lpx = NS_TO_CYCLE(60, cycle_time);
> > > > + timing->da_hs_prepare = NS_TO_CYCLE(50 + 5 * ui, cycle_time);
> > > > + timing->da_hs_zero = NS_TO_CYCLE(110 + 6 * ui, cycle_time);
> > > > + timing->da_hs_trail = NS_TO_CYCLE(77 + 4 * ui, cycle_time);
> > > >
> > > > - ui = 1000 / dsi->data_rate + 0x01;
> > > > - cycle_time = 8000 / dsi->data_rate + 0x01;
> > > > + timing->ta_go = 4 * timing->lpx;
> > > > + timing->ta_sure = 3 * timing->lpx / 2;
> > > > + timing->ta_get = 5 * timing->lpx;
> > > > + timing->da_hs_exit = 2 * timing->lpx;
> > > >
> > > > - timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
> > > > - timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 |
> > > > - T_HS_EXIT << 24;
> > > > - timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
> > > > - (NS_TO_CYCLE(0x150, cycle_time) << 16);
> > > > - timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 |
> > > > - NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
> > > > + timing->clk_hs_zero = NS_TO_CYCLE(336, cycle_time);
> > > > + timing->clk_hs_trail = NS_TO_CYCLE(100, cycle_time) + 10;
> > > > +
> > > > + timing->clk_hs_prepare = NS_TO_CYCLE(64, cycle_time);
> > > > + timing->clk_hs_post = NS_TO_CYCLE(80 + 52 * ui, cycle_time);
> > > > + timing->clk_hs_exit = 2 * timing->lpx;
> > > > +
> > > > + timcon0 = timing->lpx | timing->da_hs_prepare << 8 |
> > > > + timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
> > > > + timcon1 = timing->ta_go | timing->ta_sure << 8 |
> > > > + timing->ta_get << 16 | timing->da_hs_exit << 24;
> > > > + timcon2 = 1 << 8 | timing->clk_hs_zero << 16 |
> > > > + timing->clk_hs_trail << 24;
> > > > + timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 |
> > > > + timing->clk_hs_exit << 16;
> > > >
> > > > writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
> > > > writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
> > > > @@ -410,7 +443,8 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
> > > > u32 horizontal_sync_active_byte;
> > > > u32 horizontal_backporch_byte;
> > > > u32 horizontal_frontporch_byte;
> > > > - u32 dsi_tmp_buf_bpp;
> > > > + u32 dsi_tmp_buf_bpp, data_phy_cycles;
> > > > + struct mtk_phy_timing *timing = &dsi->phy_timing;
> > > >
> > > > struct videomode *vm = &dsi->vm;
> > > >
> > > > @@ -437,7 +471,34 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
> > > > horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
> > > > dsi_tmp_buf_bpp - 10);
> > > >
> > > > - horizontal_frontporch_byte = (vm->hfront_porch * dsi_tmp_buf_bpp - 12);
> > > > + data_phy_cycles = timing->lpx + timing->da_hs_prepare +
> > > > + timing->da_hs_zero + timing->da_hs_exit + 2;
> > > > +
> > > > + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
> > > > + if (vm->hfront_porch * dsi_tmp_buf_bpp >
> > > > + data_phy_cycles * dsi->lanes + 18) {
> > > > + horizontal_frontporch_byte = vm->hfront_porch *
> > > > + dsi_tmp_buf_bpp -
> > > > + data_phy_cycles *
> > > > + dsi->lanes - 18;
> > > > + } else {
> > > > + DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
> > > > + horizontal_frontporch_byte = vm->hfront_porch *
> > > > + dsi_tmp_buf_bpp;
> > > > + }
> > > > + } else {
> > > > + if (vm->hfront_porch * dsi_tmp_buf_bpp >
> > > > + data_phy_cycles * dsi->lanes + 12) {
> > > > + horizontal_frontporch_byte = vm->hfront_porch *
> > > > + dsi_tmp_buf_bpp -
> > > > + data_phy_cycles *
> > > > + dsi->lanes - 12;
> > > > + } else {
> > > > + DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
> > > > + horizontal_frontporch_byte = vm->hfront_porch *
> > > > + dsi_tmp_buf_bpp;
> > > > + }
> > > > + }
> > > >
> > > > writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
> > > > writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
> > > > @@ -537,8 +598,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> > > > {
> > > > struct device *dev = dsi->host.dev;
> > > > int ret;
> > > > - u64 pixel_clock, total_bits;
> > > > - u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
> > > > + u32 bit_per_pixel;
> > > >
> > > > if (++dsi->refcount != 1)
> > > > return 0;
> > > > @@ -557,24 +617,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> > > > break;
> > > > }
> > > >
> > > > - /**
> > > > - * htotal_time = htotal * byte_per_pixel / num_lanes
> > > > - * overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit
> > > > - * mipi_ratio = (htotal_time + overhead_time) / htotal_time
> > > > - * data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes;
> > > > - */
> > > > - pixel_clock = dsi->vm.pixelclock;
> > > > - htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch +
> > > > - dsi->vm.hsync_len;
> > > > - htotal_bits = htotal * bit_per_pixel;
> > > > -
> > > > - overhead_cycles = T_LPX + T_HS_PREP + T_HS_ZERO + T_HS_TRAIL +
> > > > - T_HS_EXIT;
> > > > - overhead_bits = overhead_cycles * dsi->lanes * 8;
> > > > - total_bits = htotal_bits + overhead_bits;
> > > > -
> > > > - dsi->data_rate = DIV_ROUND_UP_ULL(pixel_clock * total_bits,
> > > > - htotal * dsi->lanes);
> > > > + dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
> > > > + dsi->lanes);
> > > >
> > > > ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
> > > > if (ret < 0) {
> > >
> > >
> > > _______________________________________________
> > > dri-devel mailing list
> > > dri-devel@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v7 7/9] drm/mediatek: change the dsi phytiming calculate method
@ 2019-12-13 2:45 ` CK Hu
0 siblings, 0 replies; 21+ messages in thread
From: CK Hu @ 2019-12-13 2:45 UTC (permalink / raw)
To: Ryan Case
Cc: Nicolas Boichat, Jitao Shi, srv_heupstream, stonea168,
cawa cheng, dri-devel, David Airlie, sj.huang, Hsinyu Chao,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
Yingjoe Chen, Eddie Huang (黃智傑)
Hi, Ryan:
On Thu, 2019-12-12 at 14:47 -0800, Ryan Case wrote:
> Hi Enric,
>
> On Thu, Dec 12, 2019 at 5:53 AM Enric Balletbo Serra
> <eballetbo@gmail.com> wrote:
> >
> > Hi,
> >
> > Missatge de CK Hu <ck.hu@mediatek.com> del dia dj., 26 de set. 2019 a les 10:51:
> > >
> > > Hi, Jitao:
> > >
> > > On Thu, 2019-09-19 at 14:58 +0800, Jitao Shi wrote:
> > > > Change the method of frame rate calc which can get more accurate
> > > > frame rate.
> > > >
> > > > data rate = pixel_clock * bit_per_pixel / lanes
> > > > Adjust hfp_wc to adapt the additional phy_data
> > > >
> > > > if MIPI_DSI_MODE_VIDEO_BURST
> > > > hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12 - 6;
> > > > else
> > > > hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12;
> > > >
> > > > Note:
> > > > //(2: 1 for sync, 1 for phy idle)
> > > > data_phy_cycles = T_hs_exit + T_lpx + T_hs_prepare + T_hs_zero + 2;
> > > >
> > > > bpp: bit per pixel
> > >
> > > Reviewed-by: CK Hu <ck.hu@mediatek.com>
> > >
> > > >
> > > > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> > > > Tested-by: Ryan Case <ryandcase@chromium.org>
> > > > ---
> > > > drivers/gpu/drm/mediatek/mtk_dsi.c | 118 ++++++++++++++++++++---------
> >
> > I didn't look in detail yet because looks like there is a lot of maths
> > involved, but this patch introduces a regression for MT8173 or my
> > board (Acer Chromebook R 13 - ELM). I need to revert this patch in
> > order to make the display working, basically, I don't see any error
> > but I only get a black screen. Reverting this patch fixes the issue
> > for me. If anyone knows what could be the problem I'd appreciate.
>
> I won't pretend to be aware of current status but an in progress patch
> with updated timings that have been tested on elm can be found here:
> https://crrev.com/c/1915442
>
It seems that patch works fine in elm, so I would wait for the fixup
patch in rc stage. Otherwise, I would revert this patch.
Regards,
CK
> - ryan
>
> >
> > Thanks,
> > Enric
> >
> > > > 1 file changed, 81 insertions(+), 37 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > > index b3676426aeb5..b02373b04848 100644
> > > > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > > @@ -136,12 +136,6 @@
> > > > #define DATA_0 (0xff << 16)
> > > > #define DATA_1 (0xff << 24)
> > > >
> > > > -#define T_LPX 5
> > > > -#define T_HS_PREP 6
> > > > -#define T_HS_TRAIL 8
> > > > -#define T_HS_EXIT 7
> > > > -#define T_HS_ZERO 10
> > > > -
> > > > #define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
> > > >
> > > > #define MTK_DSI_HOST_IS_READ(type) \
> > > > @@ -150,6 +144,25 @@
> > > > (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
> > > > (type == MIPI_DSI_DCS_READ))
> > > >
> > > > +struct mtk_phy_timing {
> > > > + u32 lpx;
> > > > + u32 da_hs_prepare;
> > > > + u32 da_hs_zero;
> > > > + u32 da_hs_trail;
> > > > +
> > > > + u32 ta_go;
> > > > + u32 ta_sure;
> > > > + u32 ta_get;
> > > > + u32 da_hs_exit;
> > > > +
> > > > + u32 clk_hs_zero;
> > > > + u32 clk_hs_trail;
> > > > +
> > > > + u32 clk_hs_prepare;
> > > > + u32 clk_hs_post;
> > > > + u32 clk_hs_exit;
> > > > +};
> > > > +
> > > > struct phy;
> > > >
> > > > struct mtk_dsi_driver_data {
> > > > @@ -180,6 +193,7 @@ struct mtk_dsi {
> > > > enum mipi_dsi_pixel_format format;
> > > > unsigned int lanes;
> > > > struct videomode vm;
> > > > + struct mtk_phy_timing phy_timing;
> > > > int refcount;
> > > > bool enabled;
> > > > u32 irq_data;
> > > > @@ -213,17 +227,36 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
> > > > {
> > > > u32 timcon0, timcon1, timcon2, timcon3;
> > > > u32 ui, cycle_time;
> > > > + struct mtk_phy_timing *timing = &dsi->phy_timing;
> > > > +
> > > > + ui = DIV_ROUND_UP(1000000000, dsi->data_rate);
> > > > + cycle_time = div_u64(8000000000ULL, dsi->data_rate);
> > > > +
> > > > + timing->lpx = NS_TO_CYCLE(60, cycle_time);
> > > > + timing->da_hs_prepare = NS_TO_CYCLE(50 + 5 * ui, cycle_time);
> > > > + timing->da_hs_zero = NS_TO_CYCLE(110 + 6 * ui, cycle_time);
> > > > + timing->da_hs_trail = NS_TO_CYCLE(77 + 4 * ui, cycle_time);
> > > >
> > > > - ui = 1000 / dsi->data_rate + 0x01;
> > > > - cycle_time = 8000 / dsi->data_rate + 0x01;
> > > > + timing->ta_go = 4 * timing->lpx;
> > > > + timing->ta_sure = 3 * timing->lpx / 2;
> > > > + timing->ta_get = 5 * timing->lpx;
> > > > + timing->da_hs_exit = 2 * timing->lpx;
> > > >
> > > > - timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
> > > > - timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 |
> > > > - T_HS_EXIT << 24;
> > > > - timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
> > > > - (NS_TO_CYCLE(0x150, cycle_time) << 16);
> > > > - timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 |
> > > > - NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
> > > > + timing->clk_hs_zero = NS_TO_CYCLE(336, cycle_time);
> > > > + timing->clk_hs_trail = NS_TO_CYCLE(100, cycle_time) + 10;
> > > > +
> > > > + timing->clk_hs_prepare = NS_TO_CYCLE(64, cycle_time);
> > > > + timing->clk_hs_post = NS_TO_CYCLE(80 + 52 * ui, cycle_time);
> > > > + timing->clk_hs_exit = 2 * timing->lpx;
> > > > +
> > > > + timcon0 = timing->lpx | timing->da_hs_prepare << 8 |
> > > > + timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
> > > > + timcon1 = timing->ta_go | timing->ta_sure << 8 |
> > > > + timing->ta_get << 16 | timing->da_hs_exit << 24;
> > > > + timcon2 = 1 << 8 | timing->clk_hs_zero << 16 |
> > > > + timing->clk_hs_trail << 24;
> > > > + timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 |
> > > > + timing->clk_hs_exit << 16;
> > > >
> > > > writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
> > > > writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
> > > > @@ -410,7 +443,8 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
> > > > u32 horizontal_sync_active_byte;
> > > > u32 horizontal_backporch_byte;
> > > > u32 horizontal_frontporch_byte;
> > > > - u32 dsi_tmp_buf_bpp;
> > > > + u32 dsi_tmp_buf_bpp, data_phy_cycles;
> > > > + struct mtk_phy_timing *timing = &dsi->phy_timing;
> > > >
> > > > struct videomode *vm = &dsi->vm;
> > > >
> > > > @@ -437,7 +471,34 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
> > > > horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
> > > > dsi_tmp_buf_bpp - 10);
> > > >
> > > > - horizontal_frontporch_byte = (vm->hfront_porch * dsi_tmp_buf_bpp - 12);
> > > > + data_phy_cycles = timing->lpx + timing->da_hs_prepare +
> > > > + timing->da_hs_zero + timing->da_hs_exit + 2;
> > > > +
> > > > + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
> > > > + if (vm->hfront_porch * dsi_tmp_buf_bpp >
> > > > + data_phy_cycles * dsi->lanes + 18) {
> > > > + horizontal_frontporch_byte = vm->hfront_porch *
> > > > + dsi_tmp_buf_bpp -
> > > > + data_phy_cycles *
> > > > + dsi->lanes - 18;
> > > > + } else {
> > > > + DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
> > > > + horizontal_frontporch_byte = vm->hfront_porch *
> > > > + dsi_tmp_buf_bpp;
> > > > + }
> > > > + } else {
> > > > + if (vm->hfront_porch * dsi_tmp_buf_bpp >
> > > > + data_phy_cycles * dsi->lanes + 12) {
> > > > + horizontal_frontporch_byte = vm->hfront_porch *
> > > > + dsi_tmp_buf_bpp -
> > > > + data_phy_cycles *
> > > > + dsi->lanes - 12;
> > > > + } else {
> > > > + DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
> > > > + horizontal_frontporch_byte = vm->hfront_porch *
> > > > + dsi_tmp_buf_bpp;
> > > > + }
> > > > + }
> > > >
> > > > writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
> > > > writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
> > > > @@ -537,8 +598,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> > > > {
> > > > struct device *dev = dsi->host.dev;
> > > > int ret;
> > > > - u64 pixel_clock, total_bits;
> > > > - u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
> > > > + u32 bit_per_pixel;
> > > >
> > > > if (++dsi->refcount != 1)
> > > > return 0;
> > > > @@ -557,24 +617,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> > > > break;
> > > > }
> > > >
> > > > - /**
> > > > - * htotal_time = htotal * byte_per_pixel / num_lanes
> > > > - * overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit
> > > > - * mipi_ratio = (htotal_time + overhead_time) / htotal_time
> > > > - * data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes;
> > > > - */
> > > > - pixel_clock = dsi->vm.pixelclock;
> > > > - htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch +
> > > > - dsi->vm.hsync_len;
> > > > - htotal_bits = htotal * bit_per_pixel;
> > > > -
> > > > - overhead_cycles = T_LPX + T_HS_PREP + T_HS_ZERO + T_HS_TRAIL +
> > > > - T_HS_EXIT;
> > > > - overhead_bits = overhead_cycles * dsi->lanes * 8;
> > > > - total_bits = htotal_bits + overhead_bits;
> > > > -
> > > > - dsi->data_rate = DIV_ROUND_UP_ULL(pixel_clock * total_bits,
> > > > - htotal * dsi->lanes);
> > > > + dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
> > > > + dsi->lanes);
> > > >
> > > > ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
> > > > if (ret < 0) {
> > >
> > >
> > > _______________________________________________
> > > dri-devel mailing list
> > > dri-devel@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2019-12-13 8:22 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-09-19 6:57 [PATCH v7 0/9] Support dsi for mt8183 Jitao Shi
2019-09-19 6:57 ` [PATCH v7 1/9] drm/mediatek: move mipi_dsi_host_register to probe Jitao Shi
2019-09-19 6:57 ` [PATCH v7 2/9] drm/mediatek: fixes CMDQ reg address of mt8173 is different with mt2701 Jitao Shi
2019-09-26 8:50 ` CK Hu
2019-09-19 6:58 ` [PATCH v7 3/9] drm/mediatek: replace writeb() with mtk_dsi_mask() Jitao Shi
2019-09-26 8:50 ` CK Hu
2019-09-19 6:58 ` [PATCH v7 4/9] drm/mediatek: add dsi reg commit disable control Jitao Shi
2019-09-19 6:58 ` [PATCH v7 5/9] drm/mediatek: add frame size control Jitao Shi
2019-09-19 6:58 ` [PATCH v7 6/9] drm/mediatek: add mt8183 dsi driver support Jitao Shi
2019-09-19 6:58 ` [PATCH v7 7/9] drm/mediatek: change the dsi phytiming calculate method Jitao Shi
2019-09-26 8:51 ` CK Hu
2019-12-12 13:53 ` Enric Balletbo Serra
2019-12-12 13:53 ` Enric Balletbo Serra
2019-12-12 22:47 ` Ryan Case
2019-12-12 22:47 ` Ryan Case
2019-12-13 2:45 ` CK Hu
2019-12-13 2:45 ` CK Hu
2019-09-19 6:58 ` [PATCH v7 8/9] drm: mediatek: adjust dsi and mipi_tx probe sequence Jitao Shi
2019-09-19 6:58 ` [PATCH v7 9/9] drm/mediatek: add dphy reset after setting lanes number Jitao Shi
2019-09-26 8:52 ` CK Hu
2019-09-27 1:35 ` [PATCH v7 0/9] Support dsi for mt8183 CK Hu
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