* [PATCH 1/2] drm/amdgpu/gfx: Clear more EDC cnt
@ 2019-11-26 19:33 ` James Zhu
0 siblings, 0 replies; 10+ messages in thread
From: James Zhu @ 2019-11-26 19:33 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: jamesz-5C7GfCeVMHo
Clear SDMA and HDP EDC counter in GPR workarounds.
Signed-off-by: James Zhu <James.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index c8ace51..dc38df8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -48,6 +48,8 @@
#include "amdgpu_ras.h"
+#include "sdma0/sdma0_4_0_offset.h"
+#include "sdma1/sdma1_4_0_offset.h"
#define GFX9_NUM_GFX_RINGS 1
#define GFX9_MEC_HPD_SIZE 4096
#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
@@ -4029,6 +4031,9 @@ static const struct soc15_reg_entry sec_ded_counter_registers[] = {
{ SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16},
{ SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2},
{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},
+ { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 0, 1, 1},
+ { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_EDC_COUNTER), 0, 1, 1},
+ { SOC15_REG_ENTRY(HDP, 0, mmHDP_EDC_CNT), 0, 1, 1},
};
static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)
--
2.7.4
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 1/2] drm/amdgpu/gfx: Clear more EDC cnt
@ 2019-11-26 19:33 ` James Zhu
0 siblings, 0 replies; 10+ messages in thread
From: James Zhu @ 2019-11-26 19:33 UTC (permalink / raw)
To: amd-gfx; +Cc: jamesz
Clear SDMA and HDP EDC counter in GPR workarounds.
Signed-off-by: James Zhu <James.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index c8ace51..dc38df8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -48,6 +48,8 @@
#include "amdgpu_ras.h"
+#include "sdma0/sdma0_4_0_offset.h"
+#include "sdma1/sdma1_4_0_offset.h"
#define GFX9_NUM_GFX_RINGS 1
#define GFX9_MEC_HPD_SIZE 4096
#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
@@ -4029,6 +4031,9 @@ static const struct soc15_reg_entry sec_ded_counter_registers[] = {
{ SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16},
{ SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2},
{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},
+ { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 0, 1, 1},
+ { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_EDC_COUNTER), 0, 1, 1},
+ { SOC15_REG_ENTRY(HDP, 0, mmHDP_EDC_CNT), 0, 1, 1},
};
static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)
--
2.7.4
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^ permalink raw reply related [flat|nested] 10+ messages in thread[parent not found: <1574796818-11648-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>]
* [PATCH 2/2] drm/amdgpu/gfx: Increase dispatch packet number
@ 2019-11-26 19:33 ` James Zhu
0 siblings, 0 replies; 10+ messages in thread
From: James Zhu @ 2019-11-26 19:33 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: jamesz-5C7GfCeVMHo
For Arcturus, increase dispatch packet number to stress scheduler.
Signed-off-by: James Zhu <James.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index dc38df8..e905ac5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4146,7 +4146,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
/* write dispatch packet */
ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
- ib.ptr[ib.length_dw++] = 128; /* x */
+ ib.ptr[ib.length_dw++] = 256; /* x */
ib.ptr[ib.length_dw++] = 1; /* y */
ib.ptr[ib.length_dw++] = 1; /* z */
ib.ptr[ib.length_dw++] =
@@ -4174,7 +4174,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
/* write dispatch packet */
ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
- ib.ptr[ib.length_dw++] = 128; /* x */
+ ib.ptr[ib.length_dw++] = 256; /* x */
ib.ptr[ib.length_dw++] = 1; /* y */
ib.ptr[ib.length_dw++] = 1; /* z */
ib.ptr[ib.length_dw++] =
--
2.7.4
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/2] drm/amdgpu/gfx: Increase dispatch packet number
@ 2019-11-26 19:33 ` James Zhu
0 siblings, 0 replies; 10+ messages in thread
From: James Zhu @ 2019-11-26 19:33 UTC (permalink / raw)
To: amd-gfx; +Cc: jamesz
For Arcturus, increase dispatch packet number to stress scheduler.
Signed-off-by: James Zhu <James.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index dc38df8..e905ac5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4146,7 +4146,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
/* write dispatch packet */
ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
- ib.ptr[ib.length_dw++] = 128; /* x */
+ ib.ptr[ib.length_dw++] = 256; /* x */
ib.ptr[ib.length_dw++] = 1; /* y */
ib.ptr[ib.length_dw++] = 1; /* z */
ib.ptr[ib.length_dw++] =
@@ -4174,7 +4174,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
/* write dispatch packet */
ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
- ib.ptr[ib.length_dw++] = 128; /* x */
+ ib.ptr[ib.length_dw++] = 256; /* x */
ib.ptr[ib.length_dw++] = 1; /* y */
ib.ptr[ib.length_dw++] = 1; /* z */
ib.ptr[ib.length_dw++] =
--
2.7.4
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^ permalink raw reply related [flat|nested] 10+ messages in thread
[parent not found: <1574796818-11648-2-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>]
* RE: [PATCH 2/2] drm/amdgpu/gfx: Increase dispatch packet number
@ 2019-11-27 3:26 ` Zhang, Hawking
0 siblings, 0 replies; 10+ messages in thread
From: Zhang, Hawking @ 2019-11-27 3:26 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zhu, James
[AMD Official Use Only - Internal Distribution Only]
The Patch is
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Regards,
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of James Zhu
Sent: 2019年11月27日 3:34
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, James <James.Zhu@amd.com>
Subject: [PATCH 2/2] drm/amdgpu/gfx: Increase dispatch packet number
For Arcturus, increase dispatch packet number to stress scheduler.
Signed-off-by: James Zhu <James.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index dc38df8..e905ac5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4146,7 +4146,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
/* write dispatch packet */
ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
- ib.ptr[ib.length_dw++] = 128; /* x */
+ ib.ptr[ib.length_dw++] = 256; /* x */
ib.ptr[ib.length_dw++] = 1; /* y */
ib.ptr[ib.length_dw++] = 1; /* z */
ib.ptr[ib.length_dw++] =
@@ -4174,7 +4174,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
/* write dispatch packet */
ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
- ib.ptr[ib.length_dw++] = 128; /* x */
+ ib.ptr[ib.length_dw++] = 256; /* x */
ib.ptr[ib.length_dw++] = 1; /* y */
ib.ptr[ib.length_dw++] = 1; /* z */
ib.ptr[ib.length_dw++] =
--
2.7.4
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* RE: [PATCH 2/2] drm/amdgpu/gfx: Increase dispatch packet number
@ 2019-11-27 3:26 ` Zhang, Hawking
0 siblings, 0 replies; 10+ messages in thread
From: Zhang, Hawking @ 2019-11-27 3:26 UTC (permalink / raw)
To: Zhu, James, amd-gfx; +Cc: Zhu, James
[AMD Official Use Only - Internal Distribution Only]
The Patch is
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Regards,
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of James Zhu
Sent: 2019年11月27日 3:34
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, James <James.Zhu@amd.com>
Subject: [PATCH 2/2] drm/amdgpu/gfx: Increase dispatch packet number
For Arcturus, increase dispatch packet number to stress scheduler.
Signed-off-by: James Zhu <James.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index dc38df8..e905ac5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4146,7 +4146,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
/* write dispatch packet */
ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
- ib.ptr[ib.length_dw++] = 128; /* x */
+ ib.ptr[ib.length_dw++] = 256; /* x */
ib.ptr[ib.length_dw++] = 1; /* y */
ib.ptr[ib.length_dw++] = 1; /* z */
ib.ptr[ib.length_dw++] =
@@ -4174,7 +4174,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
/* write dispatch packet */
ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
- ib.ptr[ib.length_dw++] = 128; /* x */
+ ib.ptr[ib.length_dw++] = 256; /* x */
ib.ptr[ib.length_dw++] = 1; /* y */
ib.ptr[ib.length_dw++] = 1; /* z */
ib.ptr[ib.length_dw++] =
--
2.7.4
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* RE: [PATCH 1/2] drm/amdgpu/gfx: Clear more EDC cnt
@ 2019-11-27 3:24 ` Zhang, Hawking
0 siblings, 0 replies; 10+ messages in thread
From: Zhang, Hawking @ 2019-11-27 3:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zhu, James
[AMD Official Use Only - Internal Distribution Only]
Hi James,
Arcturus and vg20 have different SDMA instances so that the common edc counter array can't cover both ASICs. The edc counter initialization has to be either keeping in IP specific ecc late init or using different regs array.
Since error injection is not supported by SDMA/HDP/SEM in VG20 and Arcturus, there is actually no way to validate EDC for all the OSS blocks. As you may notice that, driver doesn't log any edc counter for any of OSS blocks and expose this to the users.
Regards,
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of James Zhu
Sent: 2019年11月27日 3:34
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, James <James.Zhu@amd.com>
Subject: [PATCH 1/2] drm/amdgpu/gfx: Clear more EDC cnt
Clear SDMA and HDP EDC counter in GPR workarounds.
Signed-off-by: James Zhu <James.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index c8ace51..dc38df8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -48,6 +48,8 @@
#include "amdgpu_ras.h"
+#include "sdma0/sdma0_4_0_offset.h"
+#include "sdma1/sdma1_4_0_offset.h"
#define GFX9_NUM_GFX_RINGS 1
#define GFX9_MEC_HPD_SIZE 4096
#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L @@ -4029,6 +4031,9 @@ static const struct soc15_reg_entry sec_ded_counter_registers[] = {
{ SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16},
{ SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2},
{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},
+ { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 0, 1, 1},
+ { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_EDC_COUNTER), 0, 1, 1},
+ { SOC15_REG_ENTRY(HDP, 0, mmHDP_EDC_CNT), 0, 1, 1},
};
static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)
--
2.7.4
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^ permalink raw reply related [flat|nested] 10+ messages in thread* RE: [PATCH 1/2] drm/amdgpu/gfx: Clear more EDC cnt
@ 2019-11-27 3:24 ` Zhang, Hawking
0 siblings, 0 replies; 10+ messages in thread
From: Zhang, Hawking @ 2019-11-27 3:24 UTC (permalink / raw)
To: Zhu, James, amd-gfx; +Cc: Zhu, James
[AMD Official Use Only - Internal Distribution Only]
Hi James,
Arcturus and vg20 have different SDMA instances so that the common edc counter array can't cover both ASICs. The edc counter initialization has to be either keeping in IP specific ecc late init or using different regs array.
Since error injection is not supported by SDMA/HDP/SEM in VG20 and Arcturus, there is actually no way to validate EDC for all the OSS blocks. As you may notice that, driver doesn't log any edc counter for any of OSS blocks and expose this to the users.
Regards,
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of James Zhu
Sent: 2019年11月27日 3:34
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, James <James.Zhu@amd.com>
Subject: [PATCH 1/2] drm/amdgpu/gfx: Clear more EDC cnt
Clear SDMA and HDP EDC counter in GPR workarounds.
Signed-off-by: James Zhu <James.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index c8ace51..dc38df8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -48,6 +48,8 @@
#include "amdgpu_ras.h"
+#include "sdma0/sdma0_4_0_offset.h"
+#include "sdma1/sdma1_4_0_offset.h"
#define GFX9_NUM_GFX_RINGS 1
#define GFX9_MEC_HPD_SIZE 4096
#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L @@ -4029,6 +4031,9 @@ static const struct soc15_reg_entry sec_ded_counter_registers[] = {
{ SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16},
{ SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2},
{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},
+ { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 0, 1, 1},
+ { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_EDC_COUNTER), 0, 1, 1},
+ { SOC15_REG_ENTRY(HDP, 0, mmHDP_EDC_CNT), 0, 1, 1},
};
static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)
--
2.7.4
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^ permalink raw reply related [flat|nested] 10+ messages in thread[parent not found: <DM5PR12MB1418C276613502A0CD12F1B6FC440-2J9CzHegvk81aAVlcVN8UQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>]
* RE: [PATCH 1/2] drm/amdgpu/gfx: Clear more EDC cnt
@ 2019-11-27 3:26 ` Zhang, Hawking
0 siblings, 0 replies; 10+ messages in thread
From: Zhang, Hawking @ 2019-11-27 3:26 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zhu, James
[AMD Official Use Only - Internal Distribution Only]
Ah, send it too quickly. Clean up oss edc counters seems not necessary to me unless it helps current gfx ras spgr issue. (I suspect it would help on that issue).
Regards,
Hawking
-----Original Message-----
From: Zhang, Hawking
Sent: 2019年11月27日 11:24
To: James Zhu <James.Zhu@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Zhu, James <James.Zhu@amd.com>
Subject: RE: [PATCH 1/2] drm/amdgpu/gfx: Clear more EDC cnt
[AMD Official Use Only - Internal Distribution Only]
Hi James,
Arcturus and vg20 have different SDMA instances so that the common edc counter array can't cover both ASICs. The edc counter initialization has to be either keeping in IP specific ecc late init or using different regs array.
Since error injection is not supported by SDMA/HDP/SEM in VG20 and Arcturus, there is actually no way to validate EDC for all the OSS blocks. As you may notice that, driver doesn't log any edc counter for any of OSS blocks and expose this to the users.
Regards,
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of James Zhu
Sent: 2019年11月27日 3:34
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, James <James.Zhu@amd.com>
Subject: [PATCH 1/2] drm/amdgpu/gfx: Clear more EDC cnt
Clear SDMA and HDP EDC counter in GPR workarounds.
Signed-off-by: James Zhu <James.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index c8ace51..dc38df8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -48,6 +48,8 @@
#include "amdgpu_ras.h"
+#include "sdma0/sdma0_4_0_offset.h"
+#include "sdma1/sdma1_4_0_offset.h"
#define GFX9_NUM_GFX_RINGS 1
#define GFX9_MEC_HPD_SIZE 4096
#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L @@ -4029,6 +4031,9 @@ static const struct soc15_reg_entry sec_ded_counter_registers[] = {
{ SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16},
{ SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2},
{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},
+ { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 0, 1, 1},
+ { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_EDC_COUNTER), 0, 1, 1},
+ { SOC15_REG_ENTRY(HDP, 0, mmHDP_EDC_CNT), 0, 1, 1},
};
static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)
--
2.7.4
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^ permalink raw reply related [flat|nested] 10+ messages in thread* RE: [PATCH 1/2] drm/amdgpu/gfx: Clear more EDC cnt
@ 2019-11-27 3:26 ` Zhang, Hawking
0 siblings, 0 replies; 10+ messages in thread
From: Zhang, Hawking @ 2019-11-27 3:26 UTC (permalink / raw)
To: Zhu, James, amd-gfx; +Cc: Zhu, James
[AMD Official Use Only - Internal Distribution Only]
Ah, send it too quickly. Clean up oss edc counters seems not necessary to me unless it helps current gfx ras spgr issue. (I suspect it would help on that issue).
Regards,
Hawking
-----Original Message-----
From: Zhang, Hawking
Sent: 2019年11月27日 11:24
To: James Zhu <James.Zhu@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Zhu, James <James.Zhu@amd.com>
Subject: RE: [PATCH 1/2] drm/amdgpu/gfx: Clear more EDC cnt
[AMD Official Use Only - Internal Distribution Only]
Hi James,
Arcturus and vg20 have different SDMA instances so that the common edc counter array can't cover both ASICs. The edc counter initialization has to be either keeping in IP specific ecc late init or using different regs array.
Since error injection is not supported by SDMA/HDP/SEM in VG20 and Arcturus, there is actually no way to validate EDC for all the OSS blocks. As you may notice that, driver doesn't log any edc counter for any of OSS blocks and expose this to the users.
Regards,
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of James Zhu
Sent: 2019年11月27日 3:34
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, James <James.Zhu@amd.com>
Subject: [PATCH 1/2] drm/amdgpu/gfx: Clear more EDC cnt
Clear SDMA and HDP EDC counter in GPR workarounds.
Signed-off-by: James Zhu <James.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index c8ace51..dc38df8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -48,6 +48,8 @@
#include "amdgpu_ras.h"
+#include "sdma0/sdma0_4_0_offset.h"
+#include "sdma1/sdma1_4_0_offset.h"
#define GFX9_NUM_GFX_RINGS 1
#define GFX9_MEC_HPD_SIZE 4096
#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L @@ -4029,6 +4031,9 @@ static const struct soc15_reg_entry sec_ded_counter_registers[] = {
{ SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16},
{ SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2},
{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},
+ { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 0, 1, 1},
+ { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_EDC_COUNTER), 0, 1, 1},
+ { SOC15_REG_ENTRY(HDP, 0, mmHDP_EDC_CNT), 0, 1, 1},
};
static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)
--
2.7.4
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^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2019-11-27 3:26 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-26 19:33 [PATCH 1/2] drm/amdgpu/gfx: Clear more EDC cnt James Zhu
2019-11-26 19:33 ` James Zhu
[not found] ` <1574796818-11648-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
2019-11-26 19:33 ` [PATCH 2/2] drm/amdgpu/gfx: Increase dispatch packet number James Zhu
2019-11-26 19:33 ` James Zhu
[not found] ` <1574796818-11648-2-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
2019-11-27 3:26 ` Zhang, Hawking
2019-11-27 3:26 ` Zhang, Hawking
2019-11-27 3:24 ` [PATCH 1/2] drm/amdgpu/gfx: Clear more EDC cnt Zhang, Hawking
2019-11-27 3:24 ` Zhang, Hawking
[not found] ` <DM5PR12MB1418C276613502A0CD12F1B6FC440-2J9CzHegvk81aAVlcVN8UQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-11-27 3:26 ` Zhang, Hawking
2019-11-27 3:26 ` Zhang, Hawking
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