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* [PATCH] riscv/sifive_u: fix a memory leak in soc_realize()
@ 2019-12-10  7:14 ` pannengyuan
  0 siblings, 0 replies; 6+ messages in thread
From: pannengyuan @ 2019-12-10  7:14 UTC (permalink / raw)
  To: palmer, Alistair.Francis, sagark, kbastian
  Cc: Pan Nengyuan, qemu-riscv, qemu-devel, zhang.zhanghailiang

From: Pan Nengyuan <pannengyuan@huawei.com>

Fix a minor memory leak in riscv_sifive_u_soc_realize()

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com>
---
 hw/riscv/sifive_u.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 0140e95..0e12b3c 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -542,6 +542,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
         SIFIVE_U_PLIC_CONTEXT_BASE,
         SIFIVE_U_PLIC_CONTEXT_STRIDE,
         memmap[SIFIVE_U_PLIC].size);
+    g_free(plic_hart_config);
     sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
         serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
     sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
-- 
2.7.2.windows.1




^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH] riscv/sifive_u: fix a memory leak in soc_realize()
@ 2019-12-10  7:14 ` pannengyuan
  0 siblings, 0 replies; 6+ messages in thread
From: pannengyuan @ 2019-12-10  7:14 UTC (permalink / raw)
  To: palmer, Alistair.Francis, sagark, kbastian
  Cc: qemu-riscv, qemu-devel, zhang.zhanghailiang, Pan Nengyuan

From: Pan Nengyuan <pannengyuan@huawei.com>

Fix a minor memory leak in riscv_sifive_u_soc_realize()

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com>
---
 hw/riscv/sifive_u.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 0140e95..0e12b3c 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -542,6 +542,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
         SIFIVE_U_PLIC_CONTEXT_BASE,
         SIFIVE_U_PLIC_CONTEXT_STRIDE,
         memmap[SIFIVE_U_PLIC].size);
+    g_free(plic_hart_config);
     sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
         serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
     sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
-- 
2.7.2.windows.1




^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [PATCH] riscv/sifive_u: fix a memory leak in soc_realize()
  2019-12-10  7:14 ` pannengyuan
  (?)
@ 2019-12-10  7:46 ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-12-10  7:46 UTC (permalink / raw)
  To: pannengyuan, palmer, Alistair.Francis, sagark, kbastian
  Cc: qemu-riscv, qemu-devel, zhang.zhanghailiang

On 12/10/19 8:14 AM, pannengyuan@huawei.com wrote:
> From: Pan Nengyuan <pannengyuan@huawei.com>
> 
> Fix a minor memory leak in riscv_sifive_u_soc_realize()
> 
> Reported-by: Euler Robot <euler.robot@huawei.com>
> Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com>
> ---
>   hw/riscv/sifive_u.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 0140e95..0e12b3c 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -542,6 +542,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
>           SIFIVE_U_PLIC_CONTEXT_BASE,
>           SIFIVE_U_PLIC_CONTEXT_STRIDE,
>           memmap[SIFIVE_U_PLIC].size);
> +    g_free(plic_hart_config);
>       sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
>           serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
>       sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
> 

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>



^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] riscv/sifive_u: fix a memory leak in soc_realize()
  2019-12-10  7:14 ` pannengyuan
@ 2019-12-10 18:38   ` Alistair Francis
  -1 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2019-12-10 18:38 UTC (permalink / raw)
  To: pannengyuan
  Cc: open list:RISC-V, zhang.zhanghailiang, Sagar Karandikar,
	Bastian Koppelmann, qemu-devel@nongnu.org Developers,
	Alistair Francis, Palmer Dabbelt

On Mon, Dec 9, 2019 at 11:15 PM <pannengyuan@huawei.com> wrote:
>
> From: Pan Nengyuan <pannengyuan@huawei.com>
>
> Fix a minor memory leak in riscv_sifive_u_soc_realize()
>
> Reported-by: Euler Robot <euler.robot@huawei.com>
> Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/sifive_u.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 0140e95..0e12b3c 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -542,6 +542,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
>          SIFIVE_U_PLIC_CONTEXT_BASE,
>          SIFIVE_U_PLIC_CONTEXT_STRIDE,
>          memmap[SIFIVE_U_PLIC].size);
> +    g_free(plic_hart_config);
>      sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
>          serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
>      sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
> --
> 2.7.2.windows.1
>
>
>


^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] riscv/sifive_u: fix a memory leak in soc_realize()
@ 2019-12-10 18:38   ` Alistair Francis
  0 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2019-12-10 18:38 UTC (permalink / raw)
  To: pannengyuan
  Cc: Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
	Bastian Koppelmann, open list:RISC-V,
	qemu-devel@nongnu.org Developers, zhang.zhanghailiang

On Mon, Dec 9, 2019 at 11:15 PM <pannengyuan@huawei.com> wrote:
>
> From: Pan Nengyuan <pannengyuan@huawei.com>
>
> Fix a minor memory leak in riscv_sifive_u_soc_realize()
>
> Reported-by: Euler Robot <euler.robot@huawei.com>
> Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/sifive_u.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 0140e95..0e12b3c 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -542,6 +542,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
>          SIFIVE_U_PLIC_CONTEXT_BASE,
>          SIFIVE_U_PLIC_CONTEXT_STRIDE,
>          memmap[SIFIVE_U_PLIC].size);
> +    g_free(plic_hart_config);
>      sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
>          serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
>      sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
> --
> 2.7.2.windows.1
>
>
>


^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] riscv/sifive_u: fix a memory leak in soc_realize()
  2019-12-10  7:14 ` pannengyuan
                   ` (2 preceding siblings ...)
  (?)
@ 2020-01-09 23:42 ` Palmer Dabbelt
  -1 siblings, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2020-01-09 23:42 UTC (permalink / raw)
  To: alistair23
  Cc: pannengyuan, Alistair Francis, sagark, Bastian Koppelmann,
	qemu-riscv, qemu-devel, zhang.zhanghailiang

On Tue, 10 Dec 2019 10:38:29 PST (-0800), alistair23@gmail.com wrote:
> On Mon, Dec 9, 2019 at 11:15 PM <pannengyuan@huawei.com> wrote:
>>
>> From: Pan Nengyuan <pannengyuan@huawei.com>
>>
>> Fix a minor memory leak in riscv_sifive_u_soc_realize()
>>
>> Reported-by: Euler Robot <euler.robot@huawei.com>
>> Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com>
>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Thanks.  This is in the queue, I'm hoping to submit a PR after the H patch set
is ready to go.

>
> Alistair
>
>> ---
>>  hw/riscv/sifive_u.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
>> index 0140e95..0e12b3c 100644
>> --- a/hw/riscv/sifive_u.c
>> +++ b/hw/riscv/sifive_u.c
>> @@ -542,6 +542,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
>>          SIFIVE_U_PLIC_CONTEXT_BASE,
>>          SIFIVE_U_PLIC_CONTEXT_STRIDE,
>>          memmap[SIFIVE_U_PLIC].size);
>> +    g_free(plic_hart_config);
>>      sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
>>          serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
>>      sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
>> --
>> 2.7.2.windows.1
>>
>>
>>


^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-01-09 23:43 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-12-10  7:14 [PATCH] riscv/sifive_u: fix a memory leak in soc_realize() pannengyuan
2019-12-10  7:14 ` pannengyuan
2019-12-10  7:46 ` Philippe Mathieu-Daudé
2019-12-10 18:38 ` Alistair Francis
2019-12-10 18:38   ` Alistair Francis
2020-01-09 23:42 ` Palmer Dabbelt

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