* [PATCH v2, 0/2] drm/mediatek: Add ctm property support
@ 2019-12-13 7:28 ` Yongqiang Niu
0 siblings, 0 replies; 44+ messages in thread
From: Yongqiang Niu @ 2019-12-13 7:28 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Yongqiang Niu
Changes since v1:
-separate gamma patch
-remove cmdq support for ctm setting
Yongqiang Niu (2):
drm/mediatek: Fix gamma correction issue
drm/mediatek: Add ctm property support
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +++++++--
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
3 files changed, 85 insertions(+), 4 deletions(-)
--
1.8.1.1.dirty
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v2, 0/2] drm/mediatek: Add ctm property support
@ 2019-12-13 7:28 ` Yongqiang Niu
0 siblings, 0 replies; 44+ messages in thread
From: Yongqiang Niu @ 2019-12-13 7:28 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, Daniel Vetter,
linux-arm-kernel
Changes since v1:
-separate gamma patch
-remove cmdq support for ctm setting
Yongqiang Niu (2):
drm/mediatek: Fix gamma correction issue
drm/mediatek: Add ctm property support
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +++++++--
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
3 files changed, 85 insertions(+), 4 deletions(-)
--
1.8.1.1.dirty
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v2, 0/2] drm/mediatek: Add ctm property support
@ 2019-12-13 7:28 ` Yongqiang Niu
0 siblings, 0 replies; 44+ messages in thread
From: Yongqiang Niu @ 2019-12-13 7:28 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, Daniel Vetter,
linux-arm-kernel
Changes since v1:
-separate gamma patch
-remove cmdq support for ctm setting
Yongqiang Niu (2):
drm/mediatek: Fix gamma correction issue
drm/mediatek: Add ctm property support
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +++++++--
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
3 files changed, 85 insertions(+), 4 deletions(-)
--
1.8.1.1.dirty
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v2, 0/2] drm/mediatek: Add ctm property support
@ 2019-12-13 7:28 ` Yongqiang Niu
0 siblings, 0 replies; 44+ messages in thread
From: Yongqiang Niu @ 2019-12-13 7:28 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel
Changes since v1:
-separate gamma patch
-remove cmdq support for ctm setting
Yongqiang Niu (2):
drm/mediatek: Fix gamma correction issue
drm/mediatek: Add ctm property support
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +++++++--
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
3 files changed, 85 insertions(+), 4 deletions(-)
--
1.8.1.1.dirty
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v2, 1/2] drm/mediatek: Fix gamma correction issue
2019-12-13 7:28 ` Yongqiang Niu
(?)
(?)
@ 2019-12-13 7:28 ` Yongqiang Niu
-1 siblings, 0 replies; 44+ messages in thread
From: Yongqiang Niu @ 2019-12-13 7:28 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Yongqiang Niu
if there is no gamma function in the crtc
display path, don't add gamma property
for crtc
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index ca4fc47..9a8e1d4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -734,6 +734,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
int pipe = priv->num_pipes;
int ret;
int i;
+ uint gamma_lut_size = 0;
if (!path)
return 0;
@@ -785,6 +786,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
}
mtk_crtc->ddp_comp[i] = comp;
+
+ if (comp->funcs->gamma_set)
+ gamma_lut_size = MTK_LUT_SIZE;
}
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
@@ -805,8 +809,10 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
NULL, pipe);
if (ret < 0)
return ret;
- drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
- drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);
+
+ if (gamma_lut_size)
+ drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
+ drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
priv->num_pipes++;
mutex_init(&mtk_crtc->hw_lock);
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2, 1/2] drm/mediatek: Fix gamma correction issue
@ 2019-12-13 7:28 ` Yongqiang Niu
0 siblings, 0 replies; 44+ messages in thread
From: Yongqiang Niu @ 2019-12-13 7:28 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, Daniel Vetter,
linux-arm-kernel
if there is no gamma function in the crtc
display path, don't add gamma property
for crtc
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index ca4fc47..9a8e1d4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -734,6 +734,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
int pipe = priv->num_pipes;
int ret;
int i;
+ uint gamma_lut_size = 0;
if (!path)
return 0;
@@ -785,6 +786,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
}
mtk_crtc->ddp_comp[i] = comp;
+
+ if (comp->funcs->gamma_set)
+ gamma_lut_size = MTK_LUT_SIZE;
}
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
@@ -805,8 +809,10 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
NULL, pipe);
if (ret < 0)
return ret;
- drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
- drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);
+
+ if (gamma_lut_size)
+ drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
+ drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
priv->num_pipes++;
mutex_init(&mtk_crtc->hw_lock);
--
1.8.1.1.dirty
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2, 1/2] drm/mediatek: Fix gamma correction issue
@ 2019-12-13 7:28 ` Yongqiang Niu
0 siblings, 0 replies; 44+ messages in thread
From: Yongqiang Niu @ 2019-12-13 7:28 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, Daniel Vetter,
linux-arm-kernel
if there is no gamma function in the crtc
display path, don't add gamma property
for crtc
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index ca4fc47..9a8e1d4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -734,6 +734,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
int pipe = priv->num_pipes;
int ret;
int i;
+ uint gamma_lut_size = 0;
if (!path)
return 0;
@@ -785,6 +786,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
}
mtk_crtc->ddp_comp[i] = comp;
+
+ if (comp->funcs->gamma_set)
+ gamma_lut_size = MTK_LUT_SIZE;
}
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
@@ -805,8 +809,10 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
NULL, pipe);
if (ret < 0)
return ret;
- drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
- drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);
+
+ if (gamma_lut_size)
+ drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
+ drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
priv->num_pipes++;
mutex_init(&mtk_crtc->hw_lock);
--
1.8.1.1.dirty
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2, 1/2] drm/mediatek: Fix gamma correction issue
@ 2019-12-13 7:28 ` Yongqiang Niu
0 siblings, 0 replies; 44+ messages in thread
From: Yongqiang Niu @ 2019-12-13 7:28 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel
if there is no gamma function in the crtc
display path, don't add gamma property
for crtc
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index ca4fc47..9a8e1d4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -734,6 +734,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
int pipe = priv->num_pipes;
int ret;
int i;
+ uint gamma_lut_size = 0;
if (!path)
return 0;
@@ -785,6 +786,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
}
mtk_crtc->ddp_comp[i] = comp;
+
+ if (comp->funcs->gamma_set)
+ gamma_lut_size = MTK_LUT_SIZE;
}
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
@@ -805,8 +809,10 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
NULL, pipe);
if (ret < 0)
return ret;
- drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
- drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);
+
+ if (gamma_lut_size)
+ drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
+ drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
priv->num_pipes++;
mutex_init(&mtk_crtc->hw_lock);
--
1.8.1.1.dirty
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2, 2/2] drm/mediatek: Add ctm property support
2019-12-13 7:28 ` Yongqiang Niu
(?)
(?)
@ 2019-12-13 7:28 ` Yongqiang Niu
-1 siblings, 0 replies; 44+ messages in thread
From: Yongqiang Niu @ 2019-12-13 7:28 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Yongqiang Niu
Add ctm property support
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
3 files changed, 78 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 9a8e1d4..db3031e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -614,8 +614,10 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
if (mtk_crtc->event)
mtk_crtc->pending_needs_vblank = true;
if (crtc->state->color_mgmt_changed)
- for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
+ for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
+ mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
+ }
mtk_drm_crtc_hw_config(mtk_crtc);
}
@@ -734,6 +736,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
int pipe = priv->num_pipes;
int ret;
int i;
+ bool has_ctm = false;
uint gamma_lut_size = 0;
if (!path)
@@ -787,6 +790,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
mtk_crtc->ddp_comp[i] = comp;
+ if (comp->funcs->ctm_set)
+ has_ctm = true;
+
if (comp->funcs->gamma_set)
gamma_lut_size = MTK_LUT_SIZE;
}
@@ -812,7 +818,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
if (gamma_lut_size)
drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
- drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
+ drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
priv->num_pipes++;
mutex_init(&mtk_crtc->hw_lock);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index cb3296f..182990a 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -37,7 +37,15 @@
#define CCORR_EN BIT(0)
#define DISP_CCORR_CFG 0x0020
#define CCORR_RELAY_MODE BIT(0)
+#define CCORR_ENGINE_EN BIT(1)
+#define CCORR_GAMMA_OFF BIT(2)
+#define CCORR_WGAMUT_SRC_CLIP BIT(3)
#define DISP_CCORR_SIZE 0x0030
+#define DISP_CCORR_COEF_0 0x0080
+#define DISP_CCORR_COEF_1 0x0084
+#define DISP_CCORR_COEF_2 0x0088
+#define DISP_CCORR_COEF_3 0x008C
+#define DISP_CCORR_COEF_4 0x0090
#define DISP_DITHER_EN 0x0000
#define DITHER_EN BIT(0)
@@ -188,7 +196,7 @@ static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
{
mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
- mtk_ddp_write(cmdq_pkt, CCORR_RELAY_MODE, comp, DISP_CCORR_CFG);
+ mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
}
static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
@@ -201,6 +209,57 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
}
+/* Converts a DRM S31.32 value to the HW S1.10 format. */
+static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
+{
+ u16 r;
+
+ /* Sign bit. */
+ r = in & BIT_ULL(63) ? BIT(11) : 0;
+
+ if ((in & GENMASK_ULL(62, 33)) > 0) {
+ /* identity value 0x100000000 -> 0x400, */
+ /* if bigger this, set it to max 0x7ff. */
+ r |= GENMASK(10, 0);
+ } else {
+ /* take the 11 most important bits. */
+ r |= (in >> 22) & GENMASK(10, 0);
+ }
+
+ return r;
+}
+
+static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
+ struct drm_crtc_state *state)
+{
+ struct drm_property_blob *blob = state->ctm;
+ struct drm_color_ctm *ctm;
+ const u64 *input;
+ uint16_t coeffs[9] = { 0 };
+ int i;
+ struct cmdq_pkt *cmdq_pkt = NULL;
+
+ if (!blob)
+ return;
+
+ ctm = (struct drm_color_ctm *)blob->data;
+ input = ctm->matrix;
+
+ for (i = 0; i < ARRAY_SIZE(coeffs); i++)
+ coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
+
+ mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
+ comp, DISP_CCORR_COEF_0);
+ mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
+ comp, DISP_CCORR_COEF_1);
+ mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
+ comp, DISP_CCORR_COEF_2);
+ mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
+ comp, DISP_CCORR_COEF_3);
+ mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
+ comp, DISP_CCORR_COEF_4);
+}
+
static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -271,6 +330,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
.config = mtk_ccorr_config,
.start = mtk_ccorr_start,
.stop = mtk_ccorr_stop,
+ .ctm_set = mtk_ccorr_ctm_set,
};
static const struct mtk_ddp_comp_funcs ddp_dither = {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 384abae..20fe55d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -92,6 +92,8 @@ struct mtk_ddp_comp_funcs {
struct drm_crtc_state *state);
void (*bgclr_in_on)(struct mtk_ddp_comp *comp);
void (*bgclr_in_off)(struct mtk_ddp_comp *comp);
+ void (*ctm_set)(struct mtk_ddp_comp *comp,
+ struct drm_crtc_state *state);
};
struct mtk_ddp_comp {
@@ -205,6 +207,13 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp)
comp->funcs->bgclr_in_off(comp);
}
+static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
+ struct drm_crtc_state *state)
+{
+ if (comp->funcs && comp->funcs->ctm_set)
+ comp->funcs->ctm_set(comp, state);
+}
+
int mtk_ddp_comp_get_id(struct device_node *node,
enum mtk_ddp_comp_type comp_type);
int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2, 2/2] drm/mediatek: Add ctm property support
@ 2019-12-13 7:28 ` Yongqiang Niu
0 siblings, 0 replies; 44+ messages in thread
From: Yongqiang Niu @ 2019-12-13 7:28 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, Daniel Vetter,
linux-arm-kernel
Add ctm property support
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
3 files changed, 78 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 9a8e1d4..db3031e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -614,8 +614,10 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
if (mtk_crtc->event)
mtk_crtc->pending_needs_vblank = true;
if (crtc->state->color_mgmt_changed)
- for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
+ for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
+ mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
+ }
mtk_drm_crtc_hw_config(mtk_crtc);
}
@@ -734,6 +736,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
int pipe = priv->num_pipes;
int ret;
int i;
+ bool has_ctm = false;
uint gamma_lut_size = 0;
if (!path)
@@ -787,6 +790,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
mtk_crtc->ddp_comp[i] = comp;
+ if (comp->funcs->ctm_set)
+ has_ctm = true;
+
if (comp->funcs->gamma_set)
gamma_lut_size = MTK_LUT_SIZE;
}
@@ -812,7 +818,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
if (gamma_lut_size)
drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
- drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
+ drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
priv->num_pipes++;
mutex_init(&mtk_crtc->hw_lock);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index cb3296f..182990a 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -37,7 +37,15 @@
#define CCORR_EN BIT(0)
#define DISP_CCORR_CFG 0x0020
#define CCORR_RELAY_MODE BIT(0)
+#define CCORR_ENGINE_EN BIT(1)
+#define CCORR_GAMMA_OFF BIT(2)
+#define CCORR_WGAMUT_SRC_CLIP BIT(3)
#define DISP_CCORR_SIZE 0x0030
+#define DISP_CCORR_COEF_0 0x0080
+#define DISP_CCORR_COEF_1 0x0084
+#define DISP_CCORR_COEF_2 0x0088
+#define DISP_CCORR_COEF_3 0x008C
+#define DISP_CCORR_COEF_4 0x0090
#define DISP_DITHER_EN 0x0000
#define DITHER_EN BIT(0)
@@ -188,7 +196,7 @@ static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
{
mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
- mtk_ddp_write(cmdq_pkt, CCORR_RELAY_MODE, comp, DISP_CCORR_CFG);
+ mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
}
static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
@@ -201,6 +209,57 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
}
+/* Converts a DRM S31.32 value to the HW S1.10 format. */
+static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
+{
+ u16 r;
+
+ /* Sign bit. */
+ r = in & BIT_ULL(63) ? BIT(11) : 0;
+
+ if ((in & GENMASK_ULL(62, 33)) > 0) {
+ /* identity value 0x100000000 -> 0x400, */
+ /* if bigger this, set it to max 0x7ff. */
+ r |= GENMASK(10, 0);
+ } else {
+ /* take the 11 most important bits. */
+ r |= (in >> 22) & GENMASK(10, 0);
+ }
+
+ return r;
+}
+
+static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
+ struct drm_crtc_state *state)
+{
+ struct drm_property_blob *blob = state->ctm;
+ struct drm_color_ctm *ctm;
+ const u64 *input;
+ uint16_t coeffs[9] = { 0 };
+ int i;
+ struct cmdq_pkt *cmdq_pkt = NULL;
+
+ if (!blob)
+ return;
+
+ ctm = (struct drm_color_ctm *)blob->data;
+ input = ctm->matrix;
+
+ for (i = 0; i < ARRAY_SIZE(coeffs); i++)
+ coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
+
+ mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
+ comp, DISP_CCORR_COEF_0);
+ mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
+ comp, DISP_CCORR_COEF_1);
+ mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
+ comp, DISP_CCORR_COEF_2);
+ mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
+ comp, DISP_CCORR_COEF_3);
+ mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
+ comp, DISP_CCORR_COEF_4);
+}
+
static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -271,6 +330,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
.config = mtk_ccorr_config,
.start = mtk_ccorr_start,
.stop = mtk_ccorr_stop,
+ .ctm_set = mtk_ccorr_ctm_set,
};
static const struct mtk_ddp_comp_funcs ddp_dither = {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 384abae..20fe55d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -92,6 +92,8 @@ struct mtk_ddp_comp_funcs {
struct drm_crtc_state *state);
void (*bgclr_in_on)(struct mtk_ddp_comp *comp);
void (*bgclr_in_off)(struct mtk_ddp_comp *comp);
+ void (*ctm_set)(struct mtk_ddp_comp *comp,
+ struct drm_crtc_state *state);
};
struct mtk_ddp_comp {
@@ -205,6 +207,13 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp)
comp->funcs->bgclr_in_off(comp);
}
+static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
+ struct drm_crtc_state *state)
+{
+ if (comp->funcs && comp->funcs->ctm_set)
+ comp->funcs->ctm_set(comp, state);
+}
+
int mtk_ddp_comp_get_id(struct device_node *node,
enum mtk_ddp_comp_type comp_type);
int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
--
1.8.1.1.dirty
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2, 2/2] drm/mediatek: Add ctm property support
@ 2019-12-13 7:28 ` Yongqiang Niu
0 siblings, 0 replies; 44+ messages in thread
From: Yongqiang Niu @ 2019-12-13 7:28 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, Daniel Vetter,
linux-arm-kernel
Add ctm property support
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
3 files changed, 78 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 9a8e1d4..db3031e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -614,8 +614,10 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
if (mtk_crtc->event)
mtk_crtc->pending_needs_vblank = true;
if (crtc->state->color_mgmt_changed)
- for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
+ for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
+ mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
+ }
mtk_drm_crtc_hw_config(mtk_crtc);
}
@@ -734,6 +736,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
int pipe = priv->num_pipes;
int ret;
int i;
+ bool has_ctm = false;
uint gamma_lut_size = 0;
if (!path)
@@ -787,6 +790,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
mtk_crtc->ddp_comp[i] = comp;
+ if (comp->funcs->ctm_set)
+ has_ctm = true;
+
if (comp->funcs->gamma_set)
gamma_lut_size = MTK_LUT_SIZE;
}
@@ -812,7 +818,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
if (gamma_lut_size)
drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
- drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
+ drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
priv->num_pipes++;
mutex_init(&mtk_crtc->hw_lock);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index cb3296f..182990a 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -37,7 +37,15 @@
#define CCORR_EN BIT(0)
#define DISP_CCORR_CFG 0x0020
#define CCORR_RELAY_MODE BIT(0)
+#define CCORR_ENGINE_EN BIT(1)
+#define CCORR_GAMMA_OFF BIT(2)
+#define CCORR_WGAMUT_SRC_CLIP BIT(3)
#define DISP_CCORR_SIZE 0x0030
+#define DISP_CCORR_COEF_0 0x0080
+#define DISP_CCORR_COEF_1 0x0084
+#define DISP_CCORR_COEF_2 0x0088
+#define DISP_CCORR_COEF_3 0x008C
+#define DISP_CCORR_COEF_4 0x0090
#define DISP_DITHER_EN 0x0000
#define DITHER_EN BIT(0)
@@ -188,7 +196,7 @@ static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
{
mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
- mtk_ddp_write(cmdq_pkt, CCORR_RELAY_MODE, comp, DISP_CCORR_CFG);
+ mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
}
static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
@@ -201,6 +209,57 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
}
+/* Converts a DRM S31.32 value to the HW S1.10 format. */
+static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
+{
+ u16 r;
+
+ /* Sign bit. */
+ r = in & BIT_ULL(63) ? BIT(11) : 0;
+
+ if ((in & GENMASK_ULL(62, 33)) > 0) {
+ /* identity value 0x100000000 -> 0x400, */
+ /* if bigger this, set it to max 0x7ff. */
+ r |= GENMASK(10, 0);
+ } else {
+ /* take the 11 most important bits. */
+ r |= (in >> 22) & GENMASK(10, 0);
+ }
+
+ return r;
+}
+
+static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
+ struct drm_crtc_state *state)
+{
+ struct drm_property_blob *blob = state->ctm;
+ struct drm_color_ctm *ctm;
+ const u64 *input;
+ uint16_t coeffs[9] = { 0 };
+ int i;
+ struct cmdq_pkt *cmdq_pkt = NULL;
+
+ if (!blob)
+ return;
+
+ ctm = (struct drm_color_ctm *)blob->data;
+ input = ctm->matrix;
+
+ for (i = 0; i < ARRAY_SIZE(coeffs); i++)
+ coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
+
+ mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
+ comp, DISP_CCORR_COEF_0);
+ mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
+ comp, DISP_CCORR_COEF_1);
+ mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
+ comp, DISP_CCORR_COEF_2);
+ mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
+ comp, DISP_CCORR_COEF_3);
+ mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
+ comp, DISP_CCORR_COEF_4);
+}
+
static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -271,6 +330,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
.config = mtk_ccorr_config,
.start = mtk_ccorr_start,
.stop = mtk_ccorr_stop,
+ .ctm_set = mtk_ccorr_ctm_set,
};
static const struct mtk_ddp_comp_funcs ddp_dither = {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 384abae..20fe55d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -92,6 +92,8 @@ struct mtk_ddp_comp_funcs {
struct drm_crtc_state *state);
void (*bgclr_in_on)(struct mtk_ddp_comp *comp);
void (*bgclr_in_off)(struct mtk_ddp_comp *comp);
+ void (*ctm_set)(struct mtk_ddp_comp *comp,
+ struct drm_crtc_state *state);
};
struct mtk_ddp_comp {
@@ -205,6 +207,13 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp)
comp->funcs->bgclr_in_off(comp);
}
+static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
+ struct drm_crtc_state *state)
+{
+ if (comp->funcs && comp->funcs->ctm_set)
+ comp->funcs->ctm_set(comp, state);
+}
+
int mtk_ddp_comp_get_id(struct device_node *node,
enum mtk_ddp_comp_type comp_type);
int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
--
1.8.1.1.dirty
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2, 2/2] drm/mediatek: Add ctm property support
@ 2019-12-13 7:28 ` Yongqiang Niu
0 siblings, 0 replies; 44+ messages in thread
From: Yongqiang Niu @ 2019-12-13 7:28 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel
Add ctm property support
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
3 files changed, 78 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 9a8e1d4..db3031e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -614,8 +614,10 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
if (mtk_crtc->event)
mtk_crtc->pending_needs_vblank = true;
if (crtc->state->color_mgmt_changed)
- for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
+ for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
+ mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
+ }
mtk_drm_crtc_hw_config(mtk_crtc);
}
@@ -734,6 +736,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
int pipe = priv->num_pipes;
int ret;
int i;
+ bool has_ctm = false;
uint gamma_lut_size = 0;
if (!path)
@@ -787,6 +790,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
mtk_crtc->ddp_comp[i] = comp;
+ if (comp->funcs->ctm_set)
+ has_ctm = true;
+
if (comp->funcs->gamma_set)
gamma_lut_size = MTK_LUT_SIZE;
}
@@ -812,7 +818,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
if (gamma_lut_size)
drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
- drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
+ drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
priv->num_pipes++;
mutex_init(&mtk_crtc->hw_lock);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index cb3296f..182990a 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -37,7 +37,15 @@
#define CCORR_EN BIT(0)
#define DISP_CCORR_CFG 0x0020
#define CCORR_RELAY_MODE BIT(0)
+#define CCORR_ENGINE_EN BIT(1)
+#define CCORR_GAMMA_OFF BIT(2)
+#define CCORR_WGAMUT_SRC_CLIP BIT(3)
#define DISP_CCORR_SIZE 0x0030
+#define DISP_CCORR_COEF_0 0x0080
+#define DISP_CCORR_COEF_1 0x0084
+#define DISP_CCORR_COEF_2 0x0088
+#define DISP_CCORR_COEF_3 0x008C
+#define DISP_CCORR_COEF_4 0x0090
#define DISP_DITHER_EN 0x0000
#define DITHER_EN BIT(0)
@@ -188,7 +196,7 @@ static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
{
mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
- mtk_ddp_write(cmdq_pkt, CCORR_RELAY_MODE, comp, DISP_CCORR_CFG);
+ mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
}
static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
@@ -201,6 +209,57 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
}
+/* Converts a DRM S31.32 value to the HW S1.10 format. */
+static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
+{
+ u16 r;
+
+ /* Sign bit. */
+ r = in & BIT_ULL(63) ? BIT(11) : 0;
+
+ if ((in & GENMASK_ULL(62, 33)) > 0) {
+ /* identity value 0x100000000 -> 0x400, */
+ /* if bigger this, set it to max 0x7ff. */
+ r |= GENMASK(10, 0);
+ } else {
+ /* take the 11 most important bits. */
+ r |= (in >> 22) & GENMASK(10, 0);
+ }
+
+ return r;
+}
+
+static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
+ struct drm_crtc_state *state)
+{
+ struct drm_property_blob *blob = state->ctm;
+ struct drm_color_ctm *ctm;
+ const u64 *input;
+ uint16_t coeffs[9] = { 0 };
+ int i;
+ struct cmdq_pkt *cmdq_pkt = NULL;
+
+ if (!blob)
+ return;
+
+ ctm = (struct drm_color_ctm *)blob->data;
+ input = ctm->matrix;
+
+ for (i = 0; i < ARRAY_SIZE(coeffs); i++)
+ coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
+
+ mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
+ comp, DISP_CCORR_COEF_0);
+ mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
+ comp, DISP_CCORR_COEF_1);
+ mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
+ comp, DISP_CCORR_COEF_2);
+ mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
+ comp, DISP_CCORR_COEF_3);
+ mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
+ comp, DISP_CCORR_COEF_4);
+}
+
static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -271,6 +330,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
.config = mtk_ccorr_config,
.start = mtk_ccorr_start,
.stop = mtk_ccorr_stop,
+ .ctm_set = mtk_ccorr_ctm_set,
};
static const struct mtk_ddp_comp_funcs ddp_dither = {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 384abae..20fe55d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -92,6 +92,8 @@ struct mtk_ddp_comp_funcs {
struct drm_crtc_state *state);
void (*bgclr_in_on)(struct mtk_ddp_comp *comp);
void (*bgclr_in_off)(struct mtk_ddp_comp *comp);
+ void (*ctm_set)(struct mtk_ddp_comp *comp,
+ struct drm_crtc_state *state);
};
struct mtk_ddp_comp {
@@ -205,6 +207,13 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp)
comp->funcs->bgclr_in_off(comp);
}
+static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
+ struct drm_crtc_state *state)
+{
+ if (comp->funcs && comp->funcs->ctm_set)
+ comp->funcs->ctm_set(comp, state);
+}
+
int mtk_ddp_comp_get_id(struct device_node *node,
enum mtk_ddp_comp_type comp_type);
int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
--
1.8.1.1.dirty
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 1/2] drm/mediatek: Fix gamma correction issue
2019-12-13 7:28 ` Yongqiang Niu
(?)
(?)
@ 2019-12-13 7:48 ` CK Hu
-1 siblings, 0 replies; 44+ messages in thread
From: CK Hu @ 2019-12-13 7:48 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Philipp Zabel, Rob Herring, Matthias Brugger, David Airlie,
Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
Hi, Yongqiang:
The title is too rough. Any bug of gamma would be this title. I would
like the title show explicitly what it does.
On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> if there is no gamma function in the crtc
> display path, don't add gamma property
> for crtc
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index ca4fc47..9a8e1d4 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -734,6 +734,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> int pipe = priv->num_pipes;
> int ret;
> int i;
> + uint gamma_lut_size = 0;
>
> if (!path)
> return 0;
> @@ -785,6 +786,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> }
>
> mtk_crtc->ddp_comp[i] = comp;
> +
> + if (comp->funcs->gamma_set)
> + gamma_lut_size = MTK_LUT_SIZE;
> }
>
> for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> @@ -805,8 +809,10 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> NULL, pipe);
> if (ret < 0)
> return ret;
> - drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
> - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);
> +
> + if (gamma_lut_size)
> + drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
If there is no gamma, shall we enable color management?
Regards,
CK
> priv->num_pipes++;
> mutex_init(&mtk_crtc->hw_lock);
>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 1/2] drm/mediatek: Fix gamma correction issue
@ 2019-12-13 7:48 ` CK Hu
0 siblings, 0 replies; 44+ messages in thread
From: CK Hu @ 2019-12-13 7:48 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Daniel Vetter, Matthias Brugger, linux-arm-kernel
Hi, Yongqiang:
The title is too rough. Any bug of gamma would be this title. I would
like the title show explicitly what it does.
On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> if there is no gamma function in the crtc
> display path, don't add gamma property
> for crtc
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index ca4fc47..9a8e1d4 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -734,6 +734,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> int pipe = priv->num_pipes;
> int ret;
> int i;
> + uint gamma_lut_size = 0;
>
> if (!path)
> return 0;
> @@ -785,6 +786,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> }
>
> mtk_crtc->ddp_comp[i] = comp;
> +
> + if (comp->funcs->gamma_set)
> + gamma_lut_size = MTK_LUT_SIZE;
> }
>
> for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> @@ -805,8 +809,10 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> NULL, pipe);
> if (ret < 0)
> return ret;
> - drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
> - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);
> +
> + if (gamma_lut_size)
> + drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
If there is no gamma, shall we enable color management?
Regards,
CK
> priv->num_pipes++;
> mutex_init(&mtk_crtc->hw_lock);
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 1/2] drm/mediatek: Fix gamma correction issue
@ 2019-12-13 7:48 ` CK Hu
0 siblings, 0 replies; 44+ messages in thread
From: CK Hu @ 2019-12-13 7:48 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Daniel Vetter, Matthias Brugger, linux-arm-kernel
Hi, Yongqiang:
The title is too rough. Any bug of gamma would be this title. I would
like the title show explicitly what it does.
On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> if there is no gamma function in the crtc
> display path, don't add gamma property
> for crtc
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index ca4fc47..9a8e1d4 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -734,6 +734,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> int pipe = priv->num_pipes;
> int ret;
> int i;
> + uint gamma_lut_size = 0;
>
> if (!path)
> return 0;
> @@ -785,6 +786,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> }
>
> mtk_crtc->ddp_comp[i] = comp;
> +
> + if (comp->funcs->gamma_set)
> + gamma_lut_size = MTK_LUT_SIZE;
> }
>
> for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> @@ -805,8 +809,10 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> NULL, pipe);
> if (ret < 0)
> return ret;
> - drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
> - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);
> +
> + if (gamma_lut_size)
> + drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
If there is no gamma, shall we enable color management?
Regards,
CK
> priv->num_pipes++;
> mutex_init(&mtk_crtc->hw_lock);
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 1/2] drm/mediatek: Fix gamma correction issue
@ 2019-12-13 7:48 ` CK Hu
0 siblings, 0 replies; 44+ messages in thread
From: CK Hu @ 2019-12-13 7:48 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel,
Rob Herring, linux-mediatek, Matthias Brugger, linux-arm-kernel
Hi, Yongqiang:
The title is too rough. Any bug of gamma would be this title. I would
like the title show explicitly what it does.
On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> if there is no gamma function in the crtc
> display path, don't add gamma property
> for crtc
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index ca4fc47..9a8e1d4 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -734,6 +734,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> int pipe = priv->num_pipes;
> int ret;
> int i;
> + uint gamma_lut_size = 0;
>
> if (!path)
> return 0;
> @@ -785,6 +786,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> }
>
> mtk_crtc->ddp_comp[i] = comp;
> +
> + if (comp->funcs->gamma_set)
> + gamma_lut_size = MTK_LUT_SIZE;
> }
>
> for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> @@ -805,8 +809,10 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> NULL, pipe);
> if (ret < 0)
> return ret;
> - drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
> - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);
> +
> + if (gamma_lut_size)
> + drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
If there is no gamma, shall we enable color management?
Regards,
CK
> priv->num_pipes++;
> mutex_init(&mtk_crtc->hw_lock);
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 0/2] drm/mediatek: Add ctm property support
2019-12-13 7:28 ` Yongqiang Niu
(?)
(?)
@ 2019-12-13 7:49 ` CK Hu
-1 siblings, 0 replies; 44+ messages in thread
From: CK Hu @ 2019-12-13 7:49 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Philipp Zabel, Rob Herring, Matthias Brugger, David Airlie,
Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
Hi, Yongqiang:
On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> Changes since v1:
> -separate gamma patch
> -remove cmdq support for ctm setting
If this series depend on other patch or series, please describe it.
Regards,
CK
>
>
> Yongqiang Niu (2):
> drm/mediatek: Fix gamma correction issue
> drm/mediatek: Add ctm property support
>
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +++++++--
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
> 3 files changed, 85 insertions(+), 4 deletions(-)
>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 0/2] drm/mediatek: Add ctm property support
@ 2019-12-13 7:49 ` CK Hu
0 siblings, 0 replies; 44+ messages in thread
From: CK Hu @ 2019-12-13 7:49 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Daniel Vetter, Matthias Brugger, linux-arm-kernel
Hi, Yongqiang:
On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> Changes since v1:
> -separate gamma patch
> -remove cmdq support for ctm setting
If this series depend on other patch or series, please describe it.
Regards,
CK
>
>
> Yongqiang Niu (2):
> drm/mediatek: Fix gamma correction issue
> drm/mediatek: Add ctm property support
>
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +++++++--
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
> 3 files changed, 85 insertions(+), 4 deletions(-)
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 0/2] drm/mediatek: Add ctm property support
@ 2019-12-13 7:49 ` CK Hu
0 siblings, 0 replies; 44+ messages in thread
From: CK Hu @ 2019-12-13 7:49 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Daniel Vetter, Matthias Brugger, linux-arm-kernel
Hi, Yongqiang:
On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> Changes since v1:
> -separate gamma patch
> -remove cmdq support for ctm setting
If this series depend on other patch or series, please describe it.
Regards,
CK
>
>
> Yongqiang Niu (2):
> drm/mediatek: Fix gamma correction issue
> drm/mediatek: Add ctm property support
>
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +++++++--
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
> 3 files changed, 85 insertions(+), 4 deletions(-)
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 0/2] drm/mediatek: Add ctm property support
@ 2019-12-13 7:49 ` CK Hu
0 siblings, 0 replies; 44+ messages in thread
From: CK Hu @ 2019-12-13 7:49 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel,
Rob Herring, linux-mediatek, Matthias Brugger, linux-arm-kernel
Hi, Yongqiang:
On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> Changes since v1:
> -separate gamma patch
> -remove cmdq support for ctm setting
If this series depend on other patch or series, please describe it.
Regards,
CK
>
>
> Yongqiang Niu (2):
> drm/mediatek: Fix gamma correction issue
> drm/mediatek: Add ctm property support
>
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +++++++--
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
> 3 files changed, 85 insertions(+), 4 deletions(-)
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 2/2] drm/mediatek: Add ctm property support
2019-12-13 7:28 ` Yongqiang Niu
(?)
(?)
@ 2019-12-13 7:57 ` CK Hu
-1 siblings, 0 replies; 44+ messages in thread
From: CK Hu @ 2019-12-13 7:57 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Philipp Zabel, Rob Herring, Matthias Brugger, David Airlie,
Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> Add ctm property support
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
> 3 files changed, 78 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index 9a8e1d4..db3031e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -614,8 +614,10 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
> if (mtk_crtc->event)
> mtk_crtc->pending_needs_vblank = true;
> if (crtc->state->color_mgmt_changed)
> - for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> + for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
> mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
> + mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
> + }
> mtk_drm_crtc_hw_config(mtk_crtc);
> }
>
> @@ -734,6 +736,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> int pipe = priv->num_pipes;
> int ret;
> int i;
> + bool has_ctm = false;
> uint gamma_lut_size = 0;
>
> if (!path)
> @@ -787,6 +790,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
>
> mtk_crtc->ddp_comp[i] = comp;
>
> + if (comp->funcs->ctm_set)
> + has_ctm = true;
> +
> if (comp->funcs->gamma_set)
> gamma_lut_size = MTK_LUT_SIZE;
> }
> @@ -812,7 +818,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
>
> if (gamma_lut_size)
> drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
> + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
May enable color management when has gamma or ctm.
Regards,
CK
> priv->num_pipes++;
> mutex_init(&mtk_crtc->hw_lock);
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index cb3296f..182990a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -37,7 +37,15 @@
> #define CCORR_EN BIT(0)
> #define DISP_CCORR_CFG 0x0020
> #define CCORR_RELAY_MODE BIT(0)
> +#define CCORR_ENGINE_EN BIT(1)
> +#define CCORR_GAMMA_OFF BIT(2)
> +#define CCORR_WGAMUT_SRC_CLIP BIT(3)
> #define DISP_CCORR_SIZE 0x0030
> +#define DISP_CCORR_COEF_0 0x0080
> +#define DISP_CCORR_COEF_1 0x0084
> +#define DISP_CCORR_COEF_2 0x0088
> +#define DISP_CCORR_COEF_3 0x008C
> +#define DISP_CCORR_COEF_4 0x0090
>
> #define DISP_DITHER_EN 0x0000
> #define DITHER_EN BIT(0)
> @@ -188,7 +196,7 @@ static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> {
> mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
> - mtk_ddp_write(cmdq_pkt, CCORR_RELAY_MODE, comp, DISP_CCORR_CFG);
> + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
> }
>
> static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
> @@ -201,6 +209,57 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
> writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
> }
>
> +/* Converts a DRM S31.32 value to the HW S1.10 format. */
> +static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
> +{
> + u16 r;
> +
> + /* Sign bit. */
> + r = in & BIT_ULL(63) ? BIT(11) : 0;
> +
> + if ((in & GENMASK_ULL(62, 33)) > 0) {
> + /* identity value 0x100000000 -> 0x400, */
> + /* if bigger this, set it to max 0x7ff. */
> + r |= GENMASK(10, 0);
> + } else {
> + /* take the 11 most important bits. */
> + r |= (in >> 22) & GENMASK(10, 0);
> + }
> +
> + return r;
> +}
> +
> +static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
> + struct drm_crtc_state *state)
> +{
> + struct drm_property_blob *blob = state->ctm;
> + struct drm_color_ctm *ctm;
> + const u64 *input;
> + uint16_t coeffs[9] = { 0 };
> + int i;
> + struct cmdq_pkt *cmdq_pkt = NULL;
> +
> + if (!blob)
> + return;
> +
> + ctm = (struct drm_color_ctm *)blob->data;
> + input = ctm->matrix;
> +
> + for (i = 0; i < ARRAY_SIZE(coeffs); i++)
> + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
> +
> + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
> + comp, DISP_CCORR_COEF_0);
> + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
> + comp, DISP_CCORR_COEF_1);
> + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
> + comp, DISP_CCORR_COEF_2);
> + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
> + comp, DISP_CCORR_COEF_3);
> + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
> + comp, DISP_CCORR_COEF_4);
> +}
> +
> static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> @@ -271,6 +330,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
> .config = mtk_ccorr_config,
> .start = mtk_ccorr_start,
> .stop = mtk_ccorr_stop,
> + .ctm_set = mtk_ccorr_ctm_set,
> };
>
> static const struct mtk_ddp_comp_funcs ddp_dither = {
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 384abae..20fe55d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -92,6 +92,8 @@ struct mtk_ddp_comp_funcs {
> struct drm_crtc_state *state);
> void (*bgclr_in_on)(struct mtk_ddp_comp *comp);
> void (*bgclr_in_off)(struct mtk_ddp_comp *comp);
> + void (*ctm_set)(struct mtk_ddp_comp *comp,
> + struct drm_crtc_state *state);
> };
>
> struct mtk_ddp_comp {
> @@ -205,6 +207,13 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp)
> comp->funcs->bgclr_in_off(comp);
> }
>
> +static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
> + struct drm_crtc_state *state)
> +{
> + if (comp->funcs && comp->funcs->ctm_set)
> + comp->funcs->ctm_set(comp, state);
> +}
> +
> int mtk_ddp_comp_get_id(struct device_node *node,
> enum mtk_ddp_comp_type comp_type);
> int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 2/2] drm/mediatek: Add ctm property support
@ 2019-12-13 7:57 ` CK Hu
0 siblings, 0 replies; 44+ messages in thread
From: CK Hu @ 2019-12-13 7:57 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Daniel Vetter, Matthias Brugger, linux-arm-kernel
On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> Add ctm property support
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
> 3 files changed, 78 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index 9a8e1d4..db3031e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -614,8 +614,10 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
> if (mtk_crtc->event)
> mtk_crtc->pending_needs_vblank = true;
> if (crtc->state->color_mgmt_changed)
> - for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> + for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
> mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
> + mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
> + }
> mtk_drm_crtc_hw_config(mtk_crtc);
> }
>
> @@ -734,6 +736,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> int pipe = priv->num_pipes;
> int ret;
> int i;
> + bool has_ctm = false;
> uint gamma_lut_size = 0;
>
> if (!path)
> @@ -787,6 +790,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
>
> mtk_crtc->ddp_comp[i] = comp;
>
> + if (comp->funcs->ctm_set)
> + has_ctm = true;
> +
> if (comp->funcs->gamma_set)
> gamma_lut_size = MTK_LUT_SIZE;
> }
> @@ -812,7 +818,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
>
> if (gamma_lut_size)
> drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
> + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
May enable color management when has gamma or ctm.
Regards,
CK
> priv->num_pipes++;
> mutex_init(&mtk_crtc->hw_lock);
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index cb3296f..182990a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -37,7 +37,15 @@
> #define CCORR_EN BIT(0)
> #define DISP_CCORR_CFG 0x0020
> #define CCORR_RELAY_MODE BIT(0)
> +#define CCORR_ENGINE_EN BIT(1)
> +#define CCORR_GAMMA_OFF BIT(2)
> +#define CCORR_WGAMUT_SRC_CLIP BIT(3)
> #define DISP_CCORR_SIZE 0x0030
> +#define DISP_CCORR_COEF_0 0x0080
> +#define DISP_CCORR_COEF_1 0x0084
> +#define DISP_CCORR_COEF_2 0x0088
> +#define DISP_CCORR_COEF_3 0x008C
> +#define DISP_CCORR_COEF_4 0x0090
>
> #define DISP_DITHER_EN 0x0000
> #define DITHER_EN BIT(0)
> @@ -188,7 +196,7 @@ static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> {
> mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
> - mtk_ddp_write(cmdq_pkt, CCORR_RELAY_MODE, comp, DISP_CCORR_CFG);
> + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
> }
>
> static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
> @@ -201,6 +209,57 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
> writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
> }
>
> +/* Converts a DRM S31.32 value to the HW S1.10 format. */
> +static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
> +{
> + u16 r;
> +
> + /* Sign bit. */
> + r = in & BIT_ULL(63) ? BIT(11) : 0;
> +
> + if ((in & GENMASK_ULL(62, 33)) > 0) {
> + /* identity value 0x100000000 -> 0x400, */
> + /* if bigger this, set it to max 0x7ff. */
> + r |= GENMASK(10, 0);
> + } else {
> + /* take the 11 most important bits. */
> + r |= (in >> 22) & GENMASK(10, 0);
> + }
> +
> + return r;
> +}
> +
> +static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
> + struct drm_crtc_state *state)
> +{
> + struct drm_property_blob *blob = state->ctm;
> + struct drm_color_ctm *ctm;
> + const u64 *input;
> + uint16_t coeffs[9] = { 0 };
> + int i;
> + struct cmdq_pkt *cmdq_pkt = NULL;
> +
> + if (!blob)
> + return;
> +
> + ctm = (struct drm_color_ctm *)blob->data;
> + input = ctm->matrix;
> +
> + for (i = 0; i < ARRAY_SIZE(coeffs); i++)
> + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
> +
> + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
> + comp, DISP_CCORR_COEF_0);
> + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
> + comp, DISP_CCORR_COEF_1);
> + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
> + comp, DISP_CCORR_COEF_2);
> + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
> + comp, DISP_CCORR_COEF_3);
> + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
> + comp, DISP_CCORR_COEF_4);
> +}
> +
> static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> @@ -271,6 +330,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
> .config = mtk_ccorr_config,
> .start = mtk_ccorr_start,
> .stop = mtk_ccorr_stop,
> + .ctm_set = mtk_ccorr_ctm_set,
> };
>
> static const struct mtk_ddp_comp_funcs ddp_dither = {
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 384abae..20fe55d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -92,6 +92,8 @@ struct mtk_ddp_comp_funcs {
> struct drm_crtc_state *state);
> void (*bgclr_in_on)(struct mtk_ddp_comp *comp);
> void (*bgclr_in_off)(struct mtk_ddp_comp *comp);
> + void (*ctm_set)(struct mtk_ddp_comp *comp,
> + struct drm_crtc_state *state);
> };
>
> struct mtk_ddp_comp {
> @@ -205,6 +207,13 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp)
> comp->funcs->bgclr_in_off(comp);
> }
>
> +static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
> + struct drm_crtc_state *state)
> +{
> + if (comp->funcs && comp->funcs->ctm_set)
> + comp->funcs->ctm_set(comp, state);
> +}
> +
> int mtk_ddp_comp_get_id(struct device_node *node,
> enum mtk_ddp_comp_type comp_type);
> int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 2/2] drm/mediatek: Add ctm property support
@ 2019-12-13 7:57 ` CK Hu
0 siblings, 0 replies; 44+ messages in thread
From: CK Hu @ 2019-12-13 7:57 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Daniel Vetter, Matthias Brugger, linux-arm-kernel
On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> Add ctm property support
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
> 3 files changed, 78 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index 9a8e1d4..db3031e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -614,8 +614,10 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
> if (mtk_crtc->event)
> mtk_crtc->pending_needs_vblank = true;
> if (crtc->state->color_mgmt_changed)
> - for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> + for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
> mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
> + mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
> + }
> mtk_drm_crtc_hw_config(mtk_crtc);
> }
>
> @@ -734,6 +736,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> int pipe = priv->num_pipes;
> int ret;
> int i;
> + bool has_ctm = false;
> uint gamma_lut_size = 0;
>
> if (!path)
> @@ -787,6 +790,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
>
> mtk_crtc->ddp_comp[i] = comp;
>
> + if (comp->funcs->ctm_set)
> + has_ctm = true;
> +
> if (comp->funcs->gamma_set)
> gamma_lut_size = MTK_LUT_SIZE;
> }
> @@ -812,7 +818,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
>
> if (gamma_lut_size)
> drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
> + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
May enable color management when has gamma or ctm.
Regards,
CK
> priv->num_pipes++;
> mutex_init(&mtk_crtc->hw_lock);
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index cb3296f..182990a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -37,7 +37,15 @@
> #define CCORR_EN BIT(0)
> #define DISP_CCORR_CFG 0x0020
> #define CCORR_RELAY_MODE BIT(0)
> +#define CCORR_ENGINE_EN BIT(1)
> +#define CCORR_GAMMA_OFF BIT(2)
> +#define CCORR_WGAMUT_SRC_CLIP BIT(3)
> #define DISP_CCORR_SIZE 0x0030
> +#define DISP_CCORR_COEF_0 0x0080
> +#define DISP_CCORR_COEF_1 0x0084
> +#define DISP_CCORR_COEF_2 0x0088
> +#define DISP_CCORR_COEF_3 0x008C
> +#define DISP_CCORR_COEF_4 0x0090
>
> #define DISP_DITHER_EN 0x0000
> #define DITHER_EN BIT(0)
> @@ -188,7 +196,7 @@ static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> {
> mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
> - mtk_ddp_write(cmdq_pkt, CCORR_RELAY_MODE, comp, DISP_CCORR_CFG);
> + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
> }
>
> static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
> @@ -201,6 +209,57 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
> writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
> }
>
> +/* Converts a DRM S31.32 value to the HW S1.10 format. */
> +static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
> +{
> + u16 r;
> +
> + /* Sign bit. */
> + r = in & BIT_ULL(63) ? BIT(11) : 0;
> +
> + if ((in & GENMASK_ULL(62, 33)) > 0) {
> + /* identity value 0x100000000 -> 0x400, */
> + /* if bigger this, set it to max 0x7ff. */
> + r |= GENMASK(10, 0);
> + } else {
> + /* take the 11 most important bits. */
> + r |= (in >> 22) & GENMASK(10, 0);
> + }
> +
> + return r;
> +}
> +
> +static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
> + struct drm_crtc_state *state)
> +{
> + struct drm_property_blob *blob = state->ctm;
> + struct drm_color_ctm *ctm;
> + const u64 *input;
> + uint16_t coeffs[9] = { 0 };
> + int i;
> + struct cmdq_pkt *cmdq_pkt = NULL;
> +
> + if (!blob)
> + return;
> +
> + ctm = (struct drm_color_ctm *)blob->data;
> + input = ctm->matrix;
> +
> + for (i = 0; i < ARRAY_SIZE(coeffs); i++)
> + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
> +
> + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
> + comp, DISP_CCORR_COEF_0);
> + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
> + comp, DISP_CCORR_COEF_1);
> + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
> + comp, DISP_CCORR_COEF_2);
> + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
> + comp, DISP_CCORR_COEF_3);
> + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
> + comp, DISP_CCORR_COEF_4);
> +}
> +
> static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> @@ -271,6 +330,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
> .config = mtk_ccorr_config,
> .start = mtk_ccorr_start,
> .stop = mtk_ccorr_stop,
> + .ctm_set = mtk_ccorr_ctm_set,
> };
>
> static const struct mtk_ddp_comp_funcs ddp_dither = {
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 384abae..20fe55d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -92,6 +92,8 @@ struct mtk_ddp_comp_funcs {
> struct drm_crtc_state *state);
> void (*bgclr_in_on)(struct mtk_ddp_comp *comp);
> void (*bgclr_in_off)(struct mtk_ddp_comp *comp);
> + void (*ctm_set)(struct mtk_ddp_comp *comp,
> + struct drm_crtc_state *state);
> };
>
> struct mtk_ddp_comp {
> @@ -205,6 +207,13 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp)
> comp->funcs->bgclr_in_off(comp);
> }
>
> +static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
> + struct drm_crtc_state *state)
> +{
> + if (comp->funcs && comp->funcs->ctm_set)
> + comp->funcs->ctm_set(comp, state);
> +}
> +
> int mtk_ddp_comp_get_id(struct device_node *node,
> enum mtk_ddp_comp_type comp_type);
> int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 2/2] drm/mediatek: Add ctm property support
@ 2019-12-13 7:57 ` CK Hu
0 siblings, 0 replies; 44+ messages in thread
From: CK Hu @ 2019-12-13 7:57 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel,
Rob Herring, linux-mediatek, Matthias Brugger, linux-arm-kernel
On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> Add ctm property support
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
> 3 files changed, 78 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index 9a8e1d4..db3031e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -614,8 +614,10 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
> if (mtk_crtc->event)
> mtk_crtc->pending_needs_vblank = true;
> if (crtc->state->color_mgmt_changed)
> - for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> + for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
> mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
> + mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
> + }
> mtk_drm_crtc_hw_config(mtk_crtc);
> }
>
> @@ -734,6 +736,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> int pipe = priv->num_pipes;
> int ret;
> int i;
> + bool has_ctm = false;
> uint gamma_lut_size = 0;
>
> if (!path)
> @@ -787,6 +790,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
>
> mtk_crtc->ddp_comp[i] = comp;
>
> + if (comp->funcs->ctm_set)
> + has_ctm = true;
> +
> if (comp->funcs->gamma_set)
> gamma_lut_size = MTK_LUT_SIZE;
> }
> @@ -812,7 +818,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
>
> if (gamma_lut_size)
> drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
> + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
May enable color management when has gamma or ctm.
Regards,
CK
> priv->num_pipes++;
> mutex_init(&mtk_crtc->hw_lock);
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index cb3296f..182990a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -37,7 +37,15 @@
> #define CCORR_EN BIT(0)
> #define DISP_CCORR_CFG 0x0020
> #define CCORR_RELAY_MODE BIT(0)
> +#define CCORR_ENGINE_EN BIT(1)
> +#define CCORR_GAMMA_OFF BIT(2)
> +#define CCORR_WGAMUT_SRC_CLIP BIT(3)
> #define DISP_CCORR_SIZE 0x0030
> +#define DISP_CCORR_COEF_0 0x0080
> +#define DISP_CCORR_COEF_1 0x0084
> +#define DISP_CCORR_COEF_2 0x0088
> +#define DISP_CCORR_COEF_3 0x008C
> +#define DISP_CCORR_COEF_4 0x0090
>
> #define DISP_DITHER_EN 0x0000
> #define DITHER_EN BIT(0)
> @@ -188,7 +196,7 @@ static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> {
> mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
> - mtk_ddp_write(cmdq_pkt, CCORR_RELAY_MODE, comp, DISP_CCORR_CFG);
> + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
> }
>
> static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
> @@ -201,6 +209,57 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
> writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
> }
>
> +/* Converts a DRM S31.32 value to the HW S1.10 format. */
> +static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
> +{
> + u16 r;
> +
> + /* Sign bit. */
> + r = in & BIT_ULL(63) ? BIT(11) : 0;
> +
> + if ((in & GENMASK_ULL(62, 33)) > 0) {
> + /* identity value 0x100000000 -> 0x400, */
> + /* if bigger this, set it to max 0x7ff. */
> + r |= GENMASK(10, 0);
> + } else {
> + /* take the 11 most important bits. */
> + r |= (in >> 22) & GENMASK(10, 0);
> + }
> +
> + return r;
> +}
> +
> +static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
> + struct drm_crtc_state *state)
> +{
> + struct drm_property_blob *blob = state->ctm;
> + struct drm_color_ctm *ctm;
> + const u64 *input;
> + uint16_t coeffs[9] = { 0 };
> + int i;
> + struct cmdq_pkt *cmdq_pkt = NULL;
> +
> + if (!blob)
> + return;
> +
> + ctm = (struct drm_color_ctm *)blob->data;
> + input = ctm->matrix;
> +
> + for (i = 0; i < ARRAY_SIZE(coeffs); i++)
> + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
> +
> + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
> + comp, DISP_CCORR_COEF_0);
> + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
> + comp, DISP_CCORR_COEF_1);
> + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
> + comp, DISP_CCORR_COEF_2);
> + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
> + comp, DISP_CCORR_COEF_3);
> + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
> + comp, DISP_CCORR_COEF_4);
> +}
> +
> static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> @@ -271,6 +330,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
> .config = mtk_ccorr_config,
> .start = mtk_ccorr_start,
> .stop = mtk_ccorr_stop,
> + .ctm_set = mtk_ccorr_ctm_set,
> };
>
> static const struct mtk_ddp_comp_funcs ddp_dither = {
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 384abae..20fe55d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -92,6 +92,8 @@ struct mtk_ddp_comp_funcs {
> struct drm_crtc_state *state);
> void (*bgclr_in_on)(struct mtk_ddp_comp *comp);
> void (*bgclr_in_off)(struct mtk_ddp_comp *comp);
> + void (*ctm_set)(struct mtk_ddp_comp *comp,
> + struct drm_crtc_state *state);
> };
>
> struct mtk_ddp_comp {
> @@ -205,6 +207,13 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp)
> comp->funcs->bgclr_in_off(comp);
> }
>
> +static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
> + struct drm_crtc_state *state)
> +{
> + if (comp->funcs && comp->funcs->ctm_set)
> + comp->funcs->ctm_set(comp, state);
> +}
> +
> int mtk_ddp_comp_get_id(struct device_node *node,
> enum mtk_ddp_comp_type comp_type);
> int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 1/2] drm/mediatek: Fix gamma correction issue
2019-12-13 7:48 ` CK Hu
(?)
(?)
@ 2019-12-13 8:03 ` Yongqiang Niu
-1 siblings, 0 replies; 44+ messages in thread
From: Yongqiang Niu @ 2019-12-13 8:03 UTC (permalink / raw)
To: CK Hu
Cc: Philipp Zabel, Rob Herring, Matthias Brugger, David Airlie,
Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
On Fri, 2019-12-13 at 15:48 +0800, CK Hu wrote:
> Hi, Yongqiang:
>
> The title is too rough. Any bug of gamma would be this title. I would
> like the title show explicitly what it does.
>
> On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> > if there is no gamma function in the crtc
> > display path, don't add gamma property
> > for crtc
> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++++++--
> > 1 file changed, 8 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > index ca4fc47..9a8e1d4 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > @@ -734,6 +734,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > int pipe = priv->num_pipes;
> > int ret;
> > int i;
> > + uint gamma_lut_size = 0;
> >
> > if (!path)
> > return 0;
> > @@ -785,6 +786,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > }
> >
> > mtk_crtc->ddp_comp[i] = comp;
> > +
> > + if (comp->funcs->gamma_set)
> > + gamma_lut_size = MTK_LUT_SIZE;
> > }
> >
> > for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> > @@ -805,8 +809,10 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > NULL, pipe);
> > if (ret < 0)
> > return ret;
> > - drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
> > - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);
> > +
> > + if (gamma_lut_size)
> > + drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> > + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
>
> If there is no gamma, shall we enable color management?
>
> Regards,
> CK
drm_crtc_enable_color_mgmt will check the gamma_lut_size parameter,
if no gamma, gamma_lut_size will be 0, and gamma_lut_size will not attch
gamma property for the crtc
>
> > priv->num_pipes++;
> > mutex_init(&mtk_crtc->hw_lock);
> >
>
>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 1/2] drm/mediatek: Fix gamma correction issue
@ 2019-12-13 8:03 ` Yongqiang Niu
0 siblings, 0 replies; 44+ messages in thread
From: Yongqiang Niu @ 2019-12-13 8:03 UTC (permalink / raw)
To: CK Hu
Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Daniel Vetter, Matthias Brugger, linux-arm-kernel
On Fri, 2019-12-13 at 15:48 +0800, CK Hu wrote:
> Hi, Yongqiang:
>
> The title is too rough. Any bug of gamma would be this title. I would
> like the title show explicitly what it does.
>
> On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> > if there is no gamma function in the crtc
> > display path, don't add gamma property
> > for crtc
> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++++++--
> > 1 file changed, 8 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > index ca4fc47..9a8e1d4 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > @@ -734,6 +734,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > int pipe = priv->num_pipes;
> > int ret;
> > int i;
> > + uint gamma_lut_size = 0;
> >
> > if (!path)
> > return 0;
> > @@ -785,6 +786,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > }
> >
> > mtk_crtc->ddp_comp[i] = comp;
> > +
> > + if (comp->funcs->gamma_set)
> > + gamma_lut_size = MTK_LUT_SIZE;
> > }
> >
> > for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> > @@ -805,8 +809,10 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > NULL, pipe);
> > if (ret < 0)
> > return ret;
> > - drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
> > - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);
> > +
> > + if (gamma_lut_size)
> > + drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> > + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
>
> If there is no gamma, shall we enable color management?
>
> Regards,
> CK
drm_crtc_enable_color_mgmt will check the gamma_lut_size parameter,
if no gamma, gamma_lut_size will be 0, and gamma_lut_size will not attch
gamma property for the crtc
>
> > priv->num_pipes++;
> > mutex_init(&mtk_crtc->hw_lock);
> >
>
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 1/2] drm/mediatek: Fix gamma correction issue
@ 2019-12-13 8:03 ` Yongqiang Niu
0 siblings, 0 replies; 44+ messages in thread
From: Yongqiang Niu @ 2019-12-13 8:03 UTC (permalink / raw)
To: CK Hu
Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Daniel Vetter, Matthias Brugger, linux-arm-kernel
On Fri, 2019-12-13 at 15:48 +0800, CK Hu wrote:
> Hi, Yongqiang:
>
> The title is too rough. Any bug of gamma would be this title. I would
> like the title show explicitly what it does.
>
> On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> > if there is no gamma function in the crtc
> > display path, don't add gamma property
> > for crtc
> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++++++--
> > 1 file changed, 8 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > index ca4fc47..9a8e1d4 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > @@ -734,6 +734,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > int pipe = priv->num_pipes;
> > int ret;
> > int i;
> > + uint gamma_lut_size = 0;
> >
> > if (!path)
> > return 0;
> > @@ -785,6 +786,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > }
> >
> > mtk_crtc->ddp_comp[i] = comp;
> > +
> > + if (comp->funcs->gamma_set)
> > + gamma_lut_size = MTK_LUT_SIZE;
> > }
> >
> > for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> > @@ -805,8 +809,10 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > NULL, pipe);
> > if (ret < 0)
> > return ret;
> > - drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
> > - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);
> > +
> > + if (gamma_lut_size)
> > + drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> > + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
>
> If there is no gamma, shall we enable color management?
>
> Regards,
> CK
drm_crtc_enable_color_mgmt will check the gamma_lut_size parameter,
if no gamma, gamma_lut_size will be 0, and gamma_lut_size will not attch
gamma property for the crtc
>
> > priv->num_pipes++;
> > mutex_init(&mtk_crtc->hw_lock);
> >
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 1/2] drm/mediatek: Fix gamma correction issue
@ 2019-12-13 8:03 ` Yongqiang Niu
0 siblings, 0 replies; 44+ messages in thread
From: Yongqiang Niu @ 2019-12-13 8:03 UTC (permalink / raw)
To: CK Hu
Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel,
Rob Herring, linux-mediatek, Matthias Brugger, linux-arm-kernel
On Fri, 2019-12-13 at 15:48 +0800, CK Hu wrote:
> Hi, Yongqiang:
>
> The title is too rough. Any bug of gamma would be this title. I would
> like the title show explicitly what it does.
>
> On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> > if there is no gamma function in the crtc
> > display path, don't add gamma property
> > for crtc
> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++++++--
> > 1 file changed, 8 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > index ca4fc47..9a8e1d4 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > @@ -734,6 +734,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > int pipe = priv->num_pipes;
> > int ret;
> > int i;
> > + uint gamma_lut_size = 0;
> >
> > if (!path)
> > return 0;
> > @@ -785,6 +786,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > }
> >
> > mtk_crtc->ddp_comp[i] = comp;
> > +
> > + if (comp->funcs->gamma_set)
> > + gamma_lut_size = MTK_LUT_SIZE;
> > }
> >
> > for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> > @@ -805,8 +809,10 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > NULL, pipe);
> > if (ret < 0)
> > return ret;
> > - drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
> > - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);
> > +
> > + if (gamma_lut_size)
> > + drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> > + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
>
> If there is no gamma, shall we enable color management?
>
> Regards,
> CK
drm_crtc_enable_color_mgmt will check the gamma_lut_size parameter,
if no gamma, gamma_lut_size will be 0, and gamma_lut_size will not attch
gamma property for the crtc
>
> > priv->num_pipes++;
> > mutex_init(&mtk_crtc->hw_lock);
> >
>
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 1/2] drm/mediatek: Fix gamma correction issue
2019-12-13 8:03 ` Yongqiang Niu
(?)
(?)
@ 2019-12-13 8:09 ` CK Hu
-1 siblings, 0 replies; 44+ messages in thread
From: CK Hu @ 2019-12-13 8:09 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Philipp Zabel, Rob Herring, Matthias Brugger, David Airlie,
Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
Hi, Yongqiang:
On Fri, 2019-12-13 at 16:03 +0800, Yongqiang Niu wrote:
> On Fri, 2019-12-13 at 15:48 +0800, CK Hu wrote:
> > Hi, Yongqiang:
> >
> > The title is too rough. Any bug of gamma would be this title. I would
> > like the title show explicitly what it does.
> >
> > On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> > > if there is no gamma function in the crtc
> > > display path, don't add gamma property
> > > for crtc
> > >
> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > > ---
> > > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++++++--
> > > 1 file changed, 8 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > index ca4fc47..9a8e1d4 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > @@ -734,6 +734,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > > int pipe = priv->num_pipes;
> > > int ret;
> > > int i;
> > > + uint gamma_lut_size = 0;
> > >
> > > if (!path)
> > > return 0;
> > > @@ -785,6 +786,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > > }
> > >
> > > mtk_crtc->ddp_comp[i] = comp;
> > > +
> > > + if (comp->funcs->gamma_set)
> > > + gamma_lut_size = MTK_LUT_SIZE;
> > > }
> > >
> > > for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> > > @@ -805,8 +809,10 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > > NULL, pipe);
> > > if (ret < 0)
> > > return ret;
> > > - drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
> > > - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);
> > > +
> > > + if (gamma_lut_size)
> > > + drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> > > + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
> >
> > If there is no gamma, shall we enable color management?
> >
> > Regards,
> > CK
>
> drm_crtc_enable_color_mgmt will check the gamma_lut_size parameter,
> if no gamma, gamma_lut_size will be 0, and gamma_lut_size will not attch
> gamma property for the crtc
OK, you're right. So
Reviewed-by: CK Hu <ck.hu@mediatek.com>
and what title would you like?
I could modify it when I apply this patch.
Regards,
CK
> >
> > > priv->num_pipes++;
> > > mutex_init(&mtk_crtc->hw_lock);
> > >
> >
> >
>
>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 1/2] drm/mediatek: Fix gamma correction issue
@ 2019-12-13 8:09 ` CK Hu
0 siblings, 0 replies; 44+ messages in thread
From: CK Hu @ 2019-12-13 8:09 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Daniel Vetter, Matthias Brugger, linux-arm-kernel
Hi, Yongqiang:
On Fri, 2019-12-13 at 16:03 +0800, Yongqiang Niu wrote:
> On Fri, 2019-12-13 at 15:48 +0800, CK Hu wrote:
> > Hi, Yongqiang:
> >
> > The title is too rough. Any bug of gamma would be this title. I would
> > like the title show explicitly what it does.
> >
> > On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> > > if there is no gamma function in the crtc
> > > display path, don't add gamma property
> > > for crtc
> > >
> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > > ---
> > > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++++++--
> > > 1 file changed, 8 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > index ca4fc47..9a8e1d4 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > @@ -734,6 +734,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > > int pipe = priv->num_pipes;
> > > int ret;
> > > int i;
> > > + uint gamma_lut_size = 0;
> > >
> > > if (!path)
> > > return 0;
> > > @@ -785,6 +786,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > > }
> > >
> > > mtk_crtc->ddp_comp[i] = comp;
> > > +
> > > + if (comp->funcs->gamma_set)
> > > + gamma_lut_size = MTK_LUT_SIZE;
> > > }
> > >
> > > for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> > > @@ -805,8 +809,10 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > > NULL, pipe);
> > > if (ret < 0)
> > > return ret;
> > > - drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
> > > - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);
> > > +
> > > + if (gamma_lut_size)
> > > + drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> > > + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
> >
> > If there is no gamma, shall we enable color management?
> >
> > Regards,
> > CK
>
> drm_crtc_enable_color_mgmt will check the gamma_lut_size parameter,
> if no gamma, gamma_lut_size will be 0, and gamma_lut_size will not attch
> gamma property for the crtc
OK, you're right. So
Reviewed-by: CK Hu <ck.hu@mediatek.com>
and what title would you like?
I could modify it when I apply this patch.
Regards,
CK
> >
> > > priv->num_pipes++;
> > > mutex_init(&mtk_crtc->hw_lock);
> > >
> >
> >
>
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 1/2] drm/mediatek: Fix gamma correction issue
@ 2019-12-13 8:09 ` CK Hu
0 siblings, 0 replies; 44+ messages in thread
From: CK Hu @ 2019-12-13 8:09 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Daniel Vetter, Matthias Brugger, linux-arm-kernel
Hi, Yongqiang:
On Fri, 2019-12-13 at 16:03 +0800, Yongqiang Niu wrote:
> On Fri, 2019-12-13 at 15:48 +0800, CK Hu wrote:
> > Hi, Yongqiang:
> >
> > The title is too rough. Any bug of gamma would be this title. I would
> > like the title show explicitly what it does.
> >
> > On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> > > if there is no gamma function in the crtc
> > > display path, don't add gamma property
> > > for crtc
> > >
> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > > ---
> > > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++++++--
> > > 1 file changed, 8 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > index ca4fc47..9a8e1d4 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > @@ -734,6 +734,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > > int pipe = priv->num_pipes;
> > > int ret;
> > > int i;
> > > + uint gamma_lut_size = 0;
> > >
> > > if (!path)
> > > return 0;
> > > @@ -785,6 +786,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > > }
> > >
> > > mtk_crtc->ddp_comp[i] = comp;
> > > +
> > > + if (comp->funcs->gamma_set)
> > > + gamma_lut_size = MTK_LUT_SIZE;
> > > }
> > >
> > > for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> > > @@ -805,8 +809,10 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > > NULL, pipe);
> > > if (ret < 0)
> > > return ret;
> > > - drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
> > > - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);
> > > +
> > > + if (gamma_lut_size)
> > > + drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> > > + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
> >
> > If there is no gamma, shall we enable color management?
> >
> > Regards,
> > CK
>
> drm_crtc_enable_color_mgmt will check the gamma_lut_size parameter,
> if no gamma, gamma_lut_size will be 0, and gamma_lut_size will not attch
> gamma property for the crtc
OK, you're right. So
Reviewed-by: CK Hu <ck.hu@mediatek.com>
and what title would you like?
I could modify it when I apply this patch.
Regards,
CK
> >
> > > priv->num_pipes++;
> > > mutex_init(&mtk_crtc->hw_lock);
> > >
> >
> >
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 1/2] drm/mediatek: Fix gamma correction issue
@ 2019-12-13 8:09 ` CK Hu
0 siblings, 0 replies; 44+ messages in thread
From: CK Hu @ 2019-12-13 8:09 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel,
Rob Herring, linux-mediatek, Matthias Brugger, linux-arm-kernel
Hi, Yongqiang:
On Fri, 2019-12-13 at 16:03 +0800, Yongqiang Niu wrote:
> On Fri, 2019-12-13 at 15:48 +0800, CK Hu wrote:
> > Hi, Yongqiang:
> >
> > The title is too rough. Any bug of gamma would be this title. I would
> > like the title show explicitly what it does.
> >
> > On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> > > if there is no gamma function in the crtc
> > > display path, don't add gamma property
> > > for crtc
> > >
> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > > ---
> > > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++++++--
> > > 1 file changed, 8 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > index ca4fc47..9a8e1d4 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > @@ -734,6 +734,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > > int pipe = priv->num_pipes;
> > > int ret;
> > > int i;
> > > + uint gamma_lut_size = 0;
> > >
> > > if (!path)
> > > return 0;
> > > @@ -785,6 +786,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > > }
> > >
> > > mtk_crtc->ddp_comp[i] = comp;
> > > +
> > > + if (comp->funcs->gamma_set)
> > > + gamma_lut_size = MTK_LUT_SIZE;
> > > }
> > >
> > > for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> > > @@ -805,8 +809,10 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > > NULL, pipe);
> > > if (ret < 0)
> > > return ret;
> > > - drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
> > > - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);
> > > +
> > > + if (gamma_lut_size)
> > > + drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> > > + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
> >
> > If there is no gamma, shall we enable color management?
> >
> > Regards,
> > CK
>
> drm_crtc_enable_color_mgmt will check the gamma_lut_size parameter,
> if no gamma, gamma_lut_size will be 0, and gamma_lut_size will not attch
> gamma property for the crtc
OK, you're right. So
Reviewed-by: CK Hu <ck.hu@mediatek.com>
and what title would you like?
I could modify it when I apply this patch.
Regards,
CK
> >
> > > priv->num_pipes++;
> > > mutex_init(&mtk_crtc->hw_lock);
> > >
> >
> >
>
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 2/2] drm/mediatek: Add ctm property support
2019-12-13 7:57 ` CK Hu
(?)
(?)
@ 2019-12-13 8:11 ` Yongqiang Niu
-1 siblings, 0 replies; 44+ messages in thread
From: Yongqiang Niu @ 2019-12-13 8:11 UTC (permalink / raw)
To: CK Hu
Cc: Philipp Zabel, Rob Herring, Matthias Brugger, David Airlie,
Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
On Fri, 2019-12-13 at 15:57 +0800, CK Hu wrote:
> On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> > Add ctm property support
> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++-
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
> > 3 files changed, 78 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > index 9a8e1d4..db3031e 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > @@ -614,8 +614,10 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
> > if (mtk_crtc->event)
> > mtk_crtc->pending_needs_vblank = true;
> > if (crtc->state->color_mgmt_changed)
> > - for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> > + for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
> > mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
> > + mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
> > + }
> > mtk_drm_crtc_hw_config(mtk_crtc);
> > }
> >
> > @@ -734,6 +736,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > int pipe = priv->num_pipes;
> > int ret;
> > int i;
> > + bool has_ctm = false;
> > uint gamma_lut_size = 0;
> >
> > if (!path)
> > @@ -787,6 +790,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> >
> > mtk_crtc->ddp_comp[i] = comp;
> >
> > + if (comp->funcs->ctm_set)
> > + has_ctm = true;
> > +
> > if (comp->funcs->gamma_set)
> > gamma_lut_size = MTK_LUT_SIZE;
> > }
> > @@ -812,7 +818,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> >
> > if (gamma_lut_size)
> > drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> > - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
> > + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
>
> May enable color management when has gamma or ctm.
>
> Regards,
> CK
>
drm_crtc_enable_color_mgmt will check the parameter validation.
if has_ctm is false, will not attach ctm property.
if gamma_lut_size is zero, will not attach gamma property.
> > priv->num_pipes++;
> > mutex_init(&mtk_crtc->hw_lock);
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index cb3296f..182990a 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -37,7 +37,15 @@
> > #define CCORR_EN BIT(0)
> > #define DISP_CCORR_CFG 0x0020
> > #define CCORR_RELAY_MODE BIT(0)
> > +#define CCORR_ENGINE_EN BIT(1)
> > +#define CCORR_GAMMA_OFF BIT(2)
> > +#define CCORR_WGAMUT_SRC_CLIP BIT(3)
> > #define DISP_CCORR_SIZE 0x0030
> > +#define DISP_CCORR_COEF_0 0x0080
> > +#define DISP_CCORR_COEF_1 0x0084
> > +#define DISP_CCORR_COEF_2 0x0088
> > +#define DISP_CCORR_COEF_3 0x008C
> > +#define DISP_CCORR_COEF_4 0x0090
> >
> > #define DISP_DITHER_EN 0x0000
> > #define DITHER_EN BIT(0)
> > @@ -188,7 +196,7 @@ static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
> > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > {
> > mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
> > - mtk_ddp_write(cmdq_pkt, CCORR_RELAY_MODE, comp, DISP_CCORR_CFG);
> > + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
> > }
> >
> > static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
> > @@ -201,6 +209,57 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
> > writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
> > }
> >
> > +/* Converts a DRM S31.32 value to the HW S1.10 format. */
> > +static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
> > +{
> > + u16 r;
> > +
> > + /* Sign bit. */
> > + r = in & BIT_ULL(63) ? BIT(11) : 0;
> > +
> > + if ((in & GENMASK_ULL(62, 33)) > 0) {
> > + /* identity value 0x100000000 -> 0x400, */
> > + /* if bigger this, set it to max 0x7ff. */
> > + r |= GENMASK(10, 0);
> > + } else {
> > + /* take the 11 most important bits. */
> > + r |= (in >> 22) & GENMASK(10, 0);
> > + }
> > +
> > + return r;
> > +}
> > +
> > +static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
> > + struct drm_crtc_state *state)
> > +{
> > + struct drm_property_blob *blob = state->ctm;
> > + struct drm_color_ctm *ctm;
> > + const u64 *input;
> > + uint16_t coeffs[9] = { 0 };
> > + int i;
> > + struct cmdq_pkt *cmdq_pkt = NULL;
> > +
> > + if (!blob)
> > + return;
> > +
> > + ctm = (struct drm_color_ctm *)blob->data;
> > + input = ctm->matrix;
> > +
> > + for (i = 0; i < ARRAY_SIZE(coeffs); i++)
> > + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
> > +
> > + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
> > + comp, DISP_CCORR_COEF_0);
> > + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
> > + comp, DISP_CCORR_COEF_1);
> > + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
> > + comp, DISP_CCORR_COEF_2);
> > + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
> > + comp, DISP_CCORR_COEF_3);
> > + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
> > + comp, DISP_CCORR_COEF_4);
> > +}
> > +
> > static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
> > unsigned int h, unsigned int vrefresh,
> > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > @@ -271,6 +330,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
> > .config = mtk_ccorr_config,
> > .start = mtk_ccorr_start,
> > .stop = mtk_ccorr_stop,
> > + .ctm_set = mtk_ccorr_ctm_set,
> > };
> >
> > static const struct mtk_ddp_comp_funcs ddp_dither = {
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index 384abae..20fe55d 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -92,6 +92,8 @@ struct mtk_ddp_comp_funcs {
> > struct drm_crtc_state *state);
> > void (*bgclr_in_on)(struct mtk_ddp_comp *comp);
> > void (*bgclr_in_off)(struct mtk_ddp_comp *comp);
> > + void (*ctm_set)(struct mtk_ddp_comp *comp,
> > + struct drm_crtc_state *state);
> > };
> >
> > struct mtk_ddp_comp {
> > @@ -205,6 +207,13 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp)
> > comp->funcs->bgclr_in_off(comp);
> > }
> >
> > +static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
> > + struct drm_crtc_state *state)
> > +{
> > + if (comp->funcs && comp->funcs->ctm_set)
> > + comp->funcs->ctm_set(comp, state);
> > +}
> > +
> > int mtk_ddp_comp_get_id(struct device_node *node,
> > enum mtk_ddp_comp_type comp_type);
> > int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
>
>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 2/2] drm/mediatek: Add ctm property support
@ 2019-12-13 8:11 ` Yongqiang Niu
0 siblings, 0 replies; 44+ messages in thread
From: Yongqiang Niu @ 2019-12-13 8:11 UTC (permalink / raw)
To: CK Hu
Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Daniel Vetter, Matthias Brugger, linux-arm-kernel
On Fri, 2019-12-13 at 15:57 +0800, CK Hu wrote:
> On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> > Add ctm property support
> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++-
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
> > 3 files changed, 78 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > index 9a8e1d4..db3031e 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > @@ -614,8 +614,10 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
> > if (mtk_crtc->event)
> > mtk_crtc->pending_needs_vblank = true;
> > if (crtc->state->color_mgmt_changed)
> > - for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> > + for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
> > mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
> > + mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
> > + }
> > mtk_drm_crtc_hw_config(mtk_crtc);
> > }
> >
> > @@ -734,6 +736,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > int pipe = priv->num_pipes;
> > int ret;
> > int i;
> > + bool has_ctm = false;
> > uint gamma_lut_size = 0;
> >
> > if (!path)
> > @@ -787,6 +790,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> >
> > mtk_crtc->ddp_comp[i] = comp;
> >
> > + if (comp->funcs->ctm_set)
> > + has_ctm = true;
> > +
> > if (comp->funcs->gamma_set)
> > gamma_lut_size = MTK_LUT_SIZE;
> > }
> > @@ -812,7 +818,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> >
> > if (gamma_lut_size)
> > drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> > - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
> > + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
>
> May enable color management when has gamma or ctm.
>
> Regards,
> CK
>
drm_crtc_enable_color_mgmt will check the parameter validation.
if has_ctm is false, will not attach ctm property.
if gamma_lut_size is zero, will not attach gamma property.
> > priv->num_pipes++;
> > mutex_init(&mtk_crtc->hw_lock);
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index cb3296f..182990a 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -37,7 +37,15 @@
> > #define CCORR_EN BIT(0)
> > #define DISP_CCORR_CFG 0x0020
> > #define CCORR_RELAY_MODE BIT(0)
> > +#define CCORR_ENGINE_EN BIT(1)
> > +#define CCORR_GAMMA_OFF BIT(2)
> > +#define CCORR_WGAMUT_SRC_CLIP BIT(3)
> > #define DISP_CCORR_SIZE 0x0030
> > +#define DISP_CCORR_COEF_0 0x0080
> > +#define DISP_CCORR_COEF_1 0x0084
> > +#define DISP_CCORR_COEF_2 0x0088
> > +#define DISP_CCORR_COEF_3 0x008C
> > +#define DISP_CCORR_COEF_4 0x0090
> >
> > #define DISP_DITHER_EN 0x0000
> > #define DITHER_EN BIT(0)
> > @@ -188,7 +196,7 @@ static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
> > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > {
> > mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
> > - mtk_ddp_write(cmdq_pkt, CCORR_RELAY_MODE, comp, DISP_CCORR_CFG);
> > + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
> > }
> >
> > static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
> > @@ -201,6 +209,57 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
> > writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
> > }
> >
> > +/* Converts a DRM S31.32 value to the HW S1.10 format. */
> > +static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
> > +{
> > + u16 r;
> > +
> > + /* Sign bit. */
> > + r = in & BIT_ULL(63) ? BIT(11) : 0;
> > +
> > + if ((in & GENMASK_ULL(62, 33)) > 0) {
> > + /* identity value 0x100000000 -> 0x400, */
> > + /* if bigger this, set it to max 0x7ff. */
> > + r |= GENMASK(10, 0);
> > + } else {
> > + /* take the 11 most important bits. */
> > + r |= (in >> 22) & GENMASK(10, 0);
> > + }
> > +
> > + return r;
> > +}
> > +
> > +static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
> > + struct drm_crtc_state *state)
> > +{
> > + struct drm_property_blob *blob = state->ctm;
> > + struct drm_color_ctm *ctm;
> > + const u64 *input;
> > + uint16_t coeffs[9] = { 0 };
> > + int i;
> > + struct cmdq_pkt *cmdq_pkt = NULL;
> > +
> > + if (!blob)
> > + return;
> > +
> > + ctm = (struct drm_color_ctm *)blob->data;
> > + input = ctm->matrix;
> > +
> > + for (i = 0; i < ARRAY_SIZE(coeffs); i++)
> > + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
> > +
> > + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
> > + comp, DISP_CCORR_COEF_0);
> > + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
> > + comp, DISP_CCORR_COEF_1);
> > + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
> > + comp, DISP_CCORR_COEF_2);
> > + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
> > + comp, DISP_CCORR_COEF_3);
> > + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
> > + comp, DISP_CCORR_COEF_4);
> > +}
> > +
> > static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
> > unsigned int h, unsigned int vrefresh,
> > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > @@ -271,6 +330,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
> > .config = mtk_ccorr_config,
> > .start = mtk_ccorr_start,
> > .stop = mtk_ccorr_stop,
> > + .ctm_set = mtk_ccorr_ctm_set,
> > };
> >
> > static const struct mtk_ddp_comp_funcs ddp_dither = {
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index 384abae..20fe55d 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -92,6 +92,8 @@ struct mtk_ddp_comp_funcs {
> > struct drm_crtc_state *state);
> > void (*bgclr_in_on)(struct mtk_ddp_comp *comp);
> > void (*bgclr_in_off)(struct mtk_ddp_comp *comp);
> > + void (*ctm_set)(struct mtk_ddp_comp *comp,
> > + struct drm_crtc_state *state);
> > };
> >
> > struct mtk_ddp_comp {
> > @@ -205,6 +207,13 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp)
> > comp->funcs->bgclr_in_off(comp);
> > }
> >
> > +static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
> > + struct drm_crtc_state *state)
> > +{
> > + if (comp->funcs && comp->funcs->ctm_set)
> > + comp->funcs->ctm_set(comp, state);
> > +}
> > +
> > int mtk_ddp_comp_get_id(struct device_node *node,
> > enum mtk_ddp_comp_type comp_type);
> > int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
>
>
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^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 2/2] drm/mediatek: Add ctm property support
@ 2019-12-13 8:11 ` Yongqiang Niu
0 siblings, 0 replies; 44+ messages in thread
From: Yongqiang Niu @ 2019-12-13 8:11 UTC (permalink / raw)
To: CK Hu
Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Daniel Vetter, Matthias Brugger, linux-arm-kernel
On Fri, 2019-12-13 at 15:57 +0800, CK Hu wrote:
> On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> > Add ctm property support
> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++-
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
> > 3 files changed, 78 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > index 9a8e1d4..db3031e 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > @@ -614,8 +614,10 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
> > if (mtk_crtc->event)
> > mtk_crtc->pending_needs_vblank = true;
> > if (crtc->state->color_mgmt_changed)
> > - for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> > + for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
> > mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
> > + mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
> > + }
> > mtk_drm_crtc_hw_config(mtk_crtc);
> > }
> >
> > @@ -734,6 +736,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > int pipe = priv->num_pipes;
> > int ret;
> > int i;
> > + bool has_ctm = false;
> > uint gamma_lut_size = 0;
> >
> > if (!path)
> > @@ -787,6 +790,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> >
> > mtk_crtc->ddp_comp[i] = comp;
> >
> > + if (comp->funcs->ctm_set)
> > + has_ctm = true;
> > +
> > if (comp->funcs->gamma_set)
> > gamma_lut_size = MTK_LUT_SIZE;
> > }
> > @@ -812,7 +818,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> >
> > if (gamma_lut_size)
> > drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> > - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
> > + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
>
> May enable color management when has gamma or ctm.
>
> Regards,
> CK
>
drm_crtc_enable_color_mgmt will check the parameter validation.
if has_ctm is false, will not attach ctm property.
if gamma_lut_size is zero, will not attach gamma property.
> > priv->num_pipes++;
> > mutex_init(&mtk_crtc->hw_lock);
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index cb3296f..182990a 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -37,7 +37,15 @@
> > #define CCORR_EN BIT(0)
> > #define DISP_CCORR_CFG 0x0020
> > #define CCORR_RELAY_MODE BIT(0)
> > +#define CCORR_ENGINE_EN BIT(1)
> > +#define CCORR_GAMMA_OFF BIT(2)
> > +#define CCORR_WGAMUT_SRC_CLIP BIT(3)
> > #define DISP_CCORR_SIZE 0x0030
> > +#define DISP_CCORR_COEF_0 0x0080
> > +#define DISP_CCORR_COEF_1 0x0084
> > +#define DISP_CCORR_COEF_2 0x0088
> > +#define DISP_CCORR_COEF_3 0x008C
> > +#define DISP_CCORR_COEF_4 0x0090
> >
> > #define DISP_DITHER_EN 0x0000
> > #define DITHER_EN BIT(0)
> > @@ -188,7 +196,7 @@ static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
> > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > {
> > mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
> > - mtk_ddp_write(cmdq_pkt, CCORR_RELAY_MODE, comp, DISP_CCORR_CFG);
> > + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
> > }
> >
> > static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
> > @@ -201,6 +209,57 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
> > writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
> > }
> >
> > +/* Converts a DRM S31.32 value to the HW S1.10 format. */
> > +static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
> > +{
> > + u16 r;
> > +
> > + /* Sign bit. */
> > + r = in & BIT_ULL(63) ? BIT(11) : 0;
> > +
> > + if ((in & GENMASK_ULL(62, 33)) > 0) {
> > + /* identity value 0x100000000 -> 0x400, */
> > + /* if bigger this, set it to max 0x7ff. */
> > + r |= GENMASK(10, 0);
> > + } else {
> > + /* take the 11 most important bits. */
> > + r |= (in >> 22) & GENMASK(10, 0);
> > + }
> > +
> > + return r;
> > +}
> > +
> > +static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
> > + struct drm_crtc_state *state)
> > +{
> > + struct drm_property_blob *blob = state->ctm;
> > + struct drm_color_ctm *ctm;
> > + const u64 *input;
> > + uint16_t coeffs[9] = { 0 };
> > + int i;
> > + struct cmdq_pkt *cmdq_pkt = NULL;
> > +
> > + if (!blob)
> > + return;
> > +
> > + ctm = (struct drm_color_ctm *)blob->data;
> > + input = ctm->matrix;
> > +
> > + for (i = 0; i < ARRAY_SIZE(coeffs); i++)
> > + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
> > +
> > + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
> > + comp, DISP_CCORR_COEF_0);
> > + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
> > + comp, DISP_CCORR_COEF_1);
> > + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
> > + comp, DISP_CCORR_COEF_2);
> > + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
> > + comp, DISP_CCORR_COEF_3);
> > + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
> > + comp, DISP_CCORR_COEF_4);
> > +}
> > +
> > static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
> > unsigned int h, unsigned int vrefresh,
> > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > @@ -271,6 +330,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
> > .config = mtk_ccorr_config,
> > .start = mtk_ccorr_start,
> > .stop = mtk_ccorr_stop,
> > + .ctm_set = mtk_ccorr_ctm_set,
> > };
> >
> > static const struct mtk_ddp_comp_funcs ddp_dither = {
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index 384abae..20fe55d 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -92,6 +92,8 @@ struct mtk_ddp_comp_funcs {
> > struct drm_crtc_state *state);
> > void (*bgclr_in_on)(struct mtk_ddp_comp *comp);
> > void (*bgclr_in_off)(struct mtk_ddp_comp *comp);
> > + void (*ctm_set)(struct mtk_ddp_comp *comp,
> > + struct drm_crtc_state *state);
> > };
> >
> > struct mtk_ddp_comp {
> > @@ -205,6 +207,13 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp)
> > comp->funcs->bgclr_in_off(comp);
> > }
> >
> > +static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
> > + struct drm_crtc_state *state)
> > +{
> > + if (comp->funcs && comp->funcs->ctm_set)
> > + comp->funcs->ctm_set(comp, state);
> > +}
> > +
> > int mtk_ddp_comp_get_id(struct device_node *node,
> > enum mtk_ddp_comp_type comp_type);
> > int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
>
>
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^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 2/2] drm/mediatek: Add ctm property support
@ 2019-12-13 8:11 ` Yongqiang Niu
0 siblings, 0 replies; 44+ messages in thread
From: Yongqiang Niu @ 2019-12-13 8:11 UTC (permalink / raw)
To: CK Hu
Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel,
Rob Herring, linux-mediatek, Matthias Brugger, linux-arm-kernel
On Fri, 2019-12-13 at 15:57 +0800, CK Hu wrote:
> On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> > Add ctm property support
> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++-
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
> > 3 files changed, 78 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > index 9a8e1d4..db3031e 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > @@ -614,8 +614,10 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
> > if (mtk_crtc->event)
> > mtk_crtc->pending_needs_vblank = true;
> > if (crtc->state->color_mgmt_changed)
> > - for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> > + for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
> > mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
> > + mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
> > + }
> > mtk_drm_crtc_hw_config(mtk_crtc);
> > }
> >
> > @@ -734,6 +736,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > int pipe = priv->num_pipes;
> > int ret;
> > int i;
> > + bool has_ctm = false;
> > uint gamma_lut_size = 0;
> >
> > if (!path)
> > @@ -787,6 +790,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> >
> > mtk_crtc->ddp_comp[i] = comp;
> >
> > + if (comp->funcs->ctm_set)
> > + has_ctm = true;
> > +
> > if (comp->funcs->gamma_set)
> > gamma_lut_size = MTK_LUT_SIZE;
> > }
> > @@ -812,7 +818,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> >
> > if (gamma_lut_size)
> > drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> > - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
> > + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
>
> May enable color management when has gamma or ctm.
>
> Regards,
> CK
>
drm_crtc_enable_color_mgmt will check the parameter validation.
if has_ctm is false, will not attach ctm property.
if gamma_lut_size is zero, will not attach gamma property.
> > priv->num_pipes++;
> > mutex_init(&mtk_crtc->hw_lock);
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index cb3296f..182990a 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -37,7 +37,15 @@
> > #define CCORR_EN BIT(0)
> > #define DISP_CCORR_CFG 0x0020
> > #define CCORR_RELAY_MODE BIT(0)
> > +#define CCORR_ENGINE_EN BIT(1)
> > +#define CCORR_GAMMA_OFF BIT(2)
> > +#define CCORR_WGAMUT_SRC_CLIP BIT(3)
> > #define DISP_CCORR_SIZE 0x0030
> > +#define DISP_CCORR_COEF_0 0x0080
> > +#define DISP_CCORR_COEF_1 0x0084
> > +#define DISP_CCORR_COEF_2 0x0088
> > +#define DISP_CCORR_COEF_3 0x008C
> > +#define DISP_CCORR_COEF_4 0x0090
> >
> > #define DISP_DITHER_EN 0x0000
> > #define DITHER_EN BIT(0)
> > @@ -188,7 +196,7 @@ static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
> > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > {
> > mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
> > - mtk_ddp_write(cmdq_pkt, CCORR_RELAY_MODE, comp, DISP_CCORR_CFG);
> > + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
> > }
> >
> > static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
> > @@ -201,6 +209,57 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
> > writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
> > }
> >
> > +/* Converts a DRM S31.32 value to the HW S1.10 format. */
> > +static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
> > +{
> > + u16 r;
> > +
> > + /* Sign bit. */
> > + r = in & BIT_ULL(63) ? BIT(11) : 0;
> > +
> > + if ((in & GENMASK_ULL(62, 33)) > 0) {
> > + /* identity value 0x100000000 -> 0x400, */
> > + /* if bigger this, set it to max 0x7ff. */
> > + r |= GENMASK(10, 0);
> > + } else {
> > + /* take the 11 most important bits. */
> > + r |= (in >> 22) & GENMASK(10, 0);
> > + }
> > +
> > + return r;
> > +}
> > +
> > +static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
> > + struct drm_crtc_state *state)
> > +{
> > + struct drm_property_blob *blob = state->ctm;
> > + struct drm_color_ctm *ctm;
> > + const u64 *input;
> > + uint16_t coeffs[9] = { 0 };
> > + int i;
> > + struct cmdq_pkt *cmdq_pkt = NULL;
> > +
> > + if (!blob)
> > + return;
> > +
> > + ctm = (struct drm_color_ctm *)blob->data;
> > + input = ctm->matrix;
> > +
> > + for (i = 0; i < ARRAY_SIZE(coeffs); i++)
> > + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
> > +
> > + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
> > + comp, DISP_CCORR_COEF_0);
> > + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
> > + comp, DISP_CCORR_COEF_1);
> > + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
> > + comp, DISP_CCORR_COEF_2);
> > + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
> > + comp, DISP_CCORR_COEF_3);
> > + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
> > + comp, DISP_CCORR_COEF_4);
> > +}
> > +
> > static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
> > unsigned int h, unsigned int vrefresh,
> > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > @@ -271,6 +330,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
> > .config = mtk_ccorr_config,
> > .start = mtk_ccorr_start,
> > .stop = mtk_ccorr_stop,
> > + .ctm_set = mtk_ccorr_ctm_set,
> > };
> >
> > static const struct mtk_ddp_comp_funcs ddp_dither = {
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index 384abae..20fe55d 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -92,6 +92,8 @@ struct mtk_ddp_comp_funcs {
> > struct drm_crtc_state *state);
> > void (*bgclr_in_on)(struct mtk_ddp_comp *comp);
> > void (*bgclr_in_off)(struct mtk_ddp_comp *comp);
> > + void (*ctm_set)(struct mtk_ddp_comp *comp,
> > + struct drm_crtc_state *state);
> > };
> >
> > struct mtk_ddp_comp {
> > @@ -205,6 +207,13 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp)
> > comp->funcs->bgclr_in_off(comp);
> > }
> >
> > +static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
> > + struct drm_crtc_state *state)
> > +{
> > + if (comp->funcs && comp->funcs->ctm_set)
> > + comp->funcs->ctm_set(comp, state);
> > +}
> > +
> > int mtk_ddp_comp_get_id(struct device_node *node,
> > enum mtk_ddp_comp_type comp_type);
> > int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
>
>
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^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 2/2] drm/mediatek: Add ctm property support
2019-12-13 8:11 ` Yongqiang Niu
(?)
(?)
@ 2019-12-13 8:13 ` CK Hu
-1 siblings, 0 replies; 44+ messages in thread
From: CK Hu @ 2019-12-13 8:13 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Philipp Zabel, Rob Herring, Matthias Brugger, David Airlie,
Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
Hi, Yongqiang:
On Fri, 2019-12-13 at 16:11 +0800, Yongqiang Niu wrote:
> On Fri, 2019-12-13 at 15:57 +0800, CK Hu wrote:
> > On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> > > Add ctm property support
> > >
> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > > ---
> > > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++-
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
> > > 3 files changed, 78 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > index 9a8e1d4..db3031e 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > @@ -614,8 +614,10 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
> > > if (mtk_crtc->event)
> > > mtk_crtc->pending_needs_vblank = true;
> > > if (crtc->state->color_mgmt_changed)
> > > - for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> > > + for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
> > > mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
> > > + mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
> > > + }
> > > mtk_drm_crtc_hw_config(mtk_crtc);
> > > }
> > >
> > > @@ -734,6 +736,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > > int pipe = priv->num_pipes;
> > > int ret;
> > > int i;
> > > + bool has_ctm = false;
> > > uint gamma_lut_size = 0;
> > >
> > > if (!path)
> > > @@ -787,6 +790,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > >
> > > mtk_crtc->ddp_comp[i] = comp;
> > >
> > > + if (comp->funcs->ctm_set)
> > > + has_ctm = true;
> > > +
> > > if (comp->funcs->gamma_set)
> > > gamma_lut_size = MTK_LUT_SIZE;
> > > }
> > > @@ -812,7 +818,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > >
> > > if (gamma_lut_size)
> > > drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> > > - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
> > > + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
> >
> > May enable color management when has gamma or ctm.
> >
> > Regards,
> > CK
> >
> drm_crtc_enable_color_mgmt will check the parameter validation.
> if has_ctm is false, will not attach ctm property.
> if gamma_lut_size is zero, will not attach gamma property.
You're right. So
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
>
> > > priv->num_pipes++;
> > > mutex_init(&mtk_crtc->hw_lock);
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > index cb3296f..182990a 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > @@ -37,7 +37,15 @@
> > > #define CCORR_EN BIT(0)
> > > #define DISP_CCORR_CFG 0x0020
> > > #define CCORR_RELAY_MODE BIT(0)
> > > +#define CCORR_ENGINE_EN BIT(1)
> > > +#define CCORR_GAMMA_OFF BIT(2)
> > > +#define CCORR_WGAMUT_SRC_CLIP BIT(3)
> > > #define DISP_CCORR_SIZE 0x0030
> > > +#define DISP_CCORR_COEF_0 0x0080
> > > +#define DISP_CCORR_COEF_1 0x0084
> > > +#define DISP_CCORR_COEF_2 0x0088
> > > +#define DISP_CCORR_COEF_3 0x008C
> > > +#define DISP_CCORR_COEF_4 0x0090
> > >
> > > #define DISP_DITHER_EN 0x0000
> > > #define DITHER_EN BIT(0)
> > > @@ -188,7 +196,7 @@ static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
> > > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > > {
> > > mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
> > > - mtk_ddp_write(cmdq_pkt, CCORR_RELAY_MODE, comp, DISP_CCORR_CFG);
> > > + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
> > > }
> > >
> > > static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
> > > @@ -201,6 +209,57 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
> > > writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
> > > }
> > >
> > > +/* Converts a DRM S31.32 value to the HW S1.10 format. */
> > > +static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
> > > +{
> > > + u16 r;
> > > +
> > > + /* Sign bit. */
> > > + r = in & BIT_ULL(63) ? BIT(11) : 0;
> > > +
> > > + if ((in & GENMASK_ULL(62, 33)) > 0) {
> > > + /* identity value 0x100000000 -> 0x400, */
> > > + /* if bigger this, set it to max 0x7ff. */
> > > + r |= GENMASK(10, 0);
> > > + } else {
> > > + /* take the 11 most important bits. */
> > > + r |= (in >> 22) & GENMASK(10, 0);
> > > + }
> > > +
> > > + return r;
> > > +}
> > > +
> > > +static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
> > > + struct drm_crtc_state *state)
> > > +{
> > > + struct drm_property_blob *blob = state->ctm;
> > > + struct drm_color_ctm *ctm;
> > > + const u64 *input;
> > > + uint16_t coeffs[9] = { 0 };
> > > + int i;
> > > + struct cmdq_pkt *cmdq_pkt = NULL;
> > > +
> > > + if (!blob)
> > > + return;
> > > +
> > > + ctm = (struct drm_color_ctm *)blob->data;
> > > + input = ctm->matrix;
> > > +
> > > + for (i = 0; i < ARRAY_SIZE(coeffs); i++)
> > > + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
> > > +
> > > + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
> > > + comp, DISP_CCORR_COEF_0);
> > > + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
> > > + comp, DISP_CCORR_COEF_1);
> > > + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
> > > + comp, DISP_CCORR_COEF_2);
> > > + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
> > > + comp, DISP_CCORR_COEF_3);
> > > + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
> > > + comp, DISP_CCORR_COEF_4);
> > > +}
> > > +
> > > static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
> > > unsigned int h, unsigned int vrefresh,
> > > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > > @@ -271,6 +330,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
> > > .config = mtk_ccorr_config,
> > > .start = mtk_ccorr_start,
> > > .stop = mtk_ccorr_stop,
> > > + .ctm_set = mtk_ccorr_ctm_set,
> > > };
> > >
> > > static const struct mtk_ddp_comp_funcs ddp_dither = {
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > > index 384abae..20fe55d 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > > @@ -92,6 +92,8 @@ struct mtk_ddp_comp_funcs {
> > > struct drm_crtc_state *state);
> > > void (*bgclr_in_on)(struct mtk_ddp_comp *comp);
> > > void (*bgclr_in_off)(struct mtk_ddp_comp *comp);
> > > + void (*ctm_set)(struct mtk_ddp_comp *comp,
> > > + struct drm_crtc_state *state);
> > > };
> > >
> > > struct mtk_ddp_comp {
> > > @@ -205,6 +207,13 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp)
> > > comp->funcs->bgclr_in_off(comp);
> > > }
> > >
> > > +static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
> > > + struct drm_crtc_state *state)
> > > +{
> > > + if (comp->funcs && comp->funcs->ctm_set)
> > > + comp->funcs->ctm_set(comp, state);
> > > +}
> > > +
> > > int mtk_ddp_comp_get_id(struct device_node *node,
> > > enum mtk_ddp_comp_type comp_type);
> > > int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
> >
> >
>
>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 2/2] drm/mediatek: Add ctm property support
@ 2019-12-13 8:13 ` CK Hu
0 siblings, 0 replies; 44+ messages in thread
From: CK Hu @ 2019-12-13 8:13 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Daniel Vetter, Matthias Brugger, linux-arm-kernel
Hi, Yongqiang:
On Fri, 2019-12-13 at 16:11 +0800, Yongqiang Niu wrote:
> On Fri, 2019-12-13 at 15:57 +0800, CK Hu wrote:
> > On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> > > Add ctm property support
> > >
> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > > ---
> > > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++-
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
> > > 3 files changed, 78 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > index 9a8e1d4..db3031e 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > @@ -614,8 +614,10 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
> > > if (mtk_crtc->event)
> > > mtk_crtc->pending_needs_vblank = true;
> > > if (crtc->state->color_mgmt_changed)
> > > - for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> > > + for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
> > > mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
> > > + mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
> > > + }
> > > mtk_drm_crtc_hw_config(mtk_crtc);
> > > }
> > >
> > > @@ -734,6 +736,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > > int pipe = priv->num_pipes;
> > > int ret;
> > > int i;
> > > + bool has_ctm = false;
> > > uint gamma_lut_size = 0;
> > >
> > > if (!path)
> > > @@ -787,6 +790,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > >
> > > mtk_crtc->ddp_comp[i] = comp;
> > >
> > > + if (comp->funcs->ctm_set)
> > > + has_ctm = true;
> > > +
> > > if (comp->funcs->gamma_set)
> > > gamma_lut_size = MTK_LUT_SIZE;
> > > }
> > > @@ -812,7 +818,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > >
> > > if (gamma_lut_size)
> > > drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> > > - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
> > > + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
> >
> > May enable color management when has gamma or ctm.
> >
> > Regards,
> > CK
> >
> drm_crtc_enable_color_mgmt will check the parameter validation.
> if has_ctm is false, will not attach ctm property.
> if gamma_lut_size is zero, will not attach gamma property.
You're right. So
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
>
> > > priv->num_pipes++;
> > > mutex_init(&mtk_crtc->hw_lock);
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > index cb3296f..182990a 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > @@ -37,7 +37,15 @@
> > > #define CCORR_EN BIT(0)
> > > #define DISP_CCORR_CFG 0x0020
> > > #define CCORR_RELAY_MODE BIT(0)
> > > +#define CCORR_ENGINE_EN BIT(1)
> > > +#define CCORR_GAMMA_OFF BIT(2)
> > > +#define CCORR_WGAMUT_SRC_CLIP BIT(3)
> > > #define DISP_CCORR_SIZE 0x0030
> > > +#define DISP_CCORR_COEF_0 0x0080
> > > +#define DISP_CCORR_COEF_1 0x0084
> > > +#define DISP_CCORR_COEF_2 0x0088
> > > +#define DISP_CCORR_COEF_3 0x008C
> > > +#define DISP_CCORR_COEF_4 0x0090
> > >
> > > #define DISP_DITHER_EN 0x0000
> > > #define DITHER_EN BIT(0)
> > > @@ -188,7 +196,7 @@ static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
> > > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > > {
> > > mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
> > > - mtk_ddp_write(cmdq_pkt, CCORR_RELAY_MODE, comp, DISP_CCORR_CFG);
> > > + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
> > > }
> > >
> > > static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
> > > @@ -201,6 +209,57 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
> > > writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
> > > }
> > >
> > > +/* Converts a DRM S31.32 value to the HW S1.10 format. */
> > > +static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
> > > +{
> > > + u16 r;
> > > +
> > > + /* Sign bit. */
> > > + r = in & BIT_ULL(63) ? BIT(11) : 0;
> > > +
> > > + if ((in & GENMASK_ULL(62, 33)) > 0) {
> > > + /* identity value 0x100000000 -> 0x400, */
> > > + /* if bigger this, set it to max 0x7ff. */
> > > + r |= GENMASK(10, 0);
> > > + } else {
> > > + /* take the 11 most important bits. */
> > > + r |= (in >> 22) & GENMASK(10, 0);
> > > + }
> > > +
> > > + return r;
> > > +}
> > > +
> > > +static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
> > > + struct drm_crtc_state *state)
> > > +{
> > > + struct drm_property_blob *blob = state->ctm;
> > > + struct drm_color_ctm *ctm;
> > > + const u64 *input;
> > > + uint16_t coeffs[9] = { 0 };
> > > + int i;
> > > + struct cmdq_pkt *cmdq_pkt = NULL;
> > > +
> > > + if (!blob)
> > > + return;
> > > +
> > > + ctm = (struct drm_color_ctm *)blob->data;
> > > + input = ctm->matrix;
> > > +
> > > + for (i = 0; i < ARRAY_SIZE(coeffs); i++)
> > > + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
> > > +
> > > + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
> > > + comp, DISP_CCORR_COEF_0);
> > > + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
> > > + comp, DISP_CCORR_COEF_1);
> > > + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
> > > + comp, DISP_CCORR_COEF_2);
> > > + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
> > > + comp, DISP_CCORR_COEF_3);
> > > + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
> > > + comp, DISP_CCORR_COEF_4);
> > > +}
> > > +
> > > static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
> > > unsigned int h, unsigned int vrefresh,
> > > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > > @@ -271,6 +330,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
> > > .config = mtk_ccorr_config,
> > > .start = mtk_ccorr_start,
> > > .stop = mtk_ccorr_stop,
> > > + .ctm_set = mtk_ccorr_ctm_set,
> > > };
> > >
> > > static const struct mtk_ddp_comp_funcs ddp_dither = {
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > > index 384abae..20fe55d 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > > @@ -92,6 +92,8 @@ struct mtk_ddp_comp_funcs {
> > > struct drm_crtc_state *state);
> > > void (*bgclr_in_on)(struct mtk_ddp_comp *comp);
> > > void (*bgclr_in_off)(struct mtk_ddp_comp *comp);
> > > + void (*ctm_set)(struct mtk_ddp_comp *comp,
> > > + struct drm_crtc_state *state);
> > > };
> > >
> > > struct mtk_ddp_comp {
> > > @@ -205,6 +207,13 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp)
> > > comp->funcs->bgclr_in_off(comp);
> > > }
> > >
> > > +static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
> > > + struct drm_crtc_state *state)
> > > +{
> > > + if (comp->funcs && comp->funcs->ctm_set)
> > > + comp->funcs->ctm_set(comp, state);
> > > +}
> > > +
> > > int mtk_ddp_comp_get_id(struct device_node *node,
> > > enum mtk_ddp_comp_type comp_type);
> > > int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
> >
> >
>
>
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^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 2/2] drm/mediatek: Add ctm property support
@ 2019-12-13 8:13 ` CK Hu
0 siblings, 0 replies; 44+ messages in thread
From: CK Hu @ 2019-12-13 8:13 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Daniel Vetter, Matthias Brugger, linux-arm-kernel
Hi, Yongqiang:
On Fri, 2019-12-13 at 16:11 +0800, Yongqiang Niu wrote:
> On Fri, 2019-12-13 at 15:57 +0800, CK Hu wrote:
> > On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> > > Add ctm property support
> > >
> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > > ---
> > > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++-
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
> > > 3 files changed, 78 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > index 9a8e1d4..db3031e 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > @@ -614,8 +614,10 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
> > > if (mtk_crtc->event)
> > > mtk_crtc->pending_needs_vblank = true;
> > > if (crtc->state->color_mgmt_changed)
> > > - for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> > > + for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
> > > mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
> > > + mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
> > > + }
> > > mtk_drm_crtc_hw_config(mtk_crtc);
> > > }
> > >
> > > @@ -734,6 +736,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > > int pipe = priv->num_pipes;
> > > int ret;
> > > int i;
> > > + bool has_ctm = false;
> > > uint gamma_lut_size = 0;
> > >
> > > if (!path)
> > > @@ -787,6 +790,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > >
> > > mtk_crtc->ddp_comp[i] = comp;
> > >
> > > + if (comp->funcs->ctm_set)
> > > + has_ctm = true;
> > > +
> > > if (comp->funcs->gamma_set)
> > > gamma_lut_size = MTK_LUT_SIZE;
> > > }
> > > @@ -812,7 +818,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > >
> > > if (gamma_lut_size)
> > > drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> > > - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
> > > + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
> >
> > May enable color management when has gamma or ctm.
> >
> > Regards,
> > CK
> >
> drm_crtc_enable_color_mgmt will check the parameter validation.
> if has_ctm is false, will not attach ctm property.
> if gamma_lut_size is zero, will not attach gamma property.
You're right. So
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
>
> > > priv->num_pipes++;
> > > mutex_init(&mtk_crtc->hw_lock);
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > index cb3296f..182990a 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > @@ -37,7 +37,15 @@
> > > #define CCORR_EN BIT(0)
> > > #define DISP_CCORR_CFG 0x0020
> > > #define CCORR_RELAY_MODE BIT(0)
> > > +#define CCORR_ENGINE_EN BIT(1)
> > > +#define CCORR_GAMMA_OFF BIT(2)
> > > +#define CCORR_WGAMUT_SRC_CLIP BIT(3)
> > > #define DISP_CCORR_SIZE 0x0030
> > > +#define DISP_CCORR_COEF_0 0x0080
> > > +#define DISP_CCORR_COEF_1 0x0084
> > > +#define DISP_CCORR_COEF_2 0x0088
> > > +#define DISP_CCORR_COEF_3 0x008C
> > > +#define DISP_CCORR_COEF_4 0x0090
> > >
> > > #define DISP_DITHER_EN 0x0000
> > > #define DITHER_EN BIT(0)
> > > @@ -188,7 +196,7 @@ static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
> > > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > > {
> > > mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
> > > - mtk_ddp_write(cmdq_pkt, CCORR_RELAY_MODE, comp, DISP_CCORR_CFG);
> > > + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
> > > }
> > >
> > > static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
> > > @@ -201,6 +209,57 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
> > > writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
> > > }
> > >
> > > +/* Converts a DRM S31.32 value to the HW S1.10 format. */
> > > +static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
> > > +{
> > > + u16 r;
> > > +
> > > + /* Sign bit. */
> > > + r = in & BIT_ULL(63) ? BIT(11) : 0;
> > > +
> > > + if ((in & GENMASK_ULL(62, 33)) > 0) {
> > > + /* identity value 0x100000000 -> 0x400, */
> > > + /* if bigger this, set it to max 0x7ff. */
> > > + r |= GENMASK(10, 0);
> > > + } else {
> > > + /* take the 11 most important bits. */
> > > + r |= (in >> 22) & GENMASK(10, 0);
> > > + }
> > > +
> > > + return r;
> > > +}
> > > +
> > > +static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
> > > + struct drm_crtc_state *state)
> > > +{
> > > + struct drm_property_blob *blob = state->ctm;
> > > + struct drm_color_ctm *ctm;
> > > + const u64 *input;
> > > + uint16_t coeffs[9] = { 0 };
> > > + int i;
> > > + struct cmdq_pkt *cmdq_pkt = NULL;
> > > +
> > > + if (!blob)
> > > + return;
> > > +
> > > + ctm = (struct drm_color_ctm *)blob->data;
> > > + input = ctm->matrix;
> > > +
> > > + for (i = 0; i < ARRAY_SIZE(coeffs); i++)
> > > + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
> > > +
> > > + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
> > > + comp, DISP_CCORR_COEF_0);
> > > + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
> > > + comp, DISP_CCORR_COEF_1);
> > > + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
> > > + comp, DISP_CCORR_COEF_2);
> > > + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
> > > + comp, DISP_CCORR_COEF_3);
> > > + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
> > > + comp, DISP_CCORR_COEF_4);
> > > +}
> > > +
> > > static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
> > > unsigned int h, unsigned int vrefresh,
> > > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > > @@ -271,6 +330,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
> > > .config = mtk_ccorr_config,
> > > .start = mtk_ccorr_start,
> > > .stop = mtk_ccorr_stop,
> > > + .ctm_set = mtk_ccorr_ctm_set,
> > > };
> > >
> > > static const struct mtk_ddp_comp_funcs ddp_dither = {
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > > index 384abae..20fe55d 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > > @@ -92,6 +92,8 @@ struct mtk_ddp_comp_funcs {
> > > struct drm_crtc_state *state);
> > > void (*bgclr_in_on)(struct mtk_ddp_comp *comp);
> > > void (*bgclr_in_off)(struct mtk_ddp_comp *comp);
> > > + void (*ctm_set)(struct mtk_ddp_comp *comp,
> > > + struct drm_crtc_state *state);
> > > };
> > >
> > > struct mtk_ddp_comp {
> > > @@ -205,6 +207,13 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp)
> > > comp->funcs->bgclr_in_off(comp);
> > > }
> > >
> > > +static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
> > > + struct drm_crtc_state *state)
> > > +{
> > > + if (comp->funcs && comp->funcs->ctm_set)
> > > + comp->funcs->ctm_set(comp, state);
> > > +}
> > > +
> > > int mtk_ddp_comp_get_id(struct device_node *node,
> > > enum mtk_ddp_comp_type comp_type);
> > > int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
> >
> >
>
>
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^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 2/2] drm/mediatek: Add ctm property support
@ 2019-12-13 8:13 ` CK Hu
0 siblings, 0 replies; 44+ messages in thread
From: CK Hu @ 2019-12-13 8:13 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel,
Rob Herring, linux-mediatek, Matthias Brugger, linux-arm-kernel
Hi, Yongqiang:
On Fri, 2019-12-13 at 16:11 +0800, Yongqiang Niu wrote:
> On Fri, 2019-12-13 at 15:57 +0800, CK Hu wrote:
> > On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> > > Add ctm property support
> > >
> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > > ---
> > > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++-
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
> > > 3 files changed, 78 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > index 9a8e1d4..db3031e 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > @@ -614,8 +614,10 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
> > > if (mtk_crtc->event)
> > > mtk_crtc->pending_needs_vblank = true;
> > > if (crtc->state->color_mgmt_changed)
> > > - for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> > > + for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
> > > mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
> > > + mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
> > > + }
> > > mtk_drm_crtc_hw_config(mtk_crtc);
> > > }
> > >
> > > @@ -734,6 +736,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > > int pipe = priv->num_pipes;
> > > int ret;
> > > int i;
> > > + bool has_ctm = false;
> > > uint gamma_lut_size = 0;
> > >
> > > if (!path)
> > > @@ -787,6 +790,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > >
> > > mtk_crtc->ddp_comp[i] = comp;
> > >
> > > + if (comp->funcs->ctm_set)
> > > + has_ctm = true;
> > > +
> > > if (comp->funcs->gamma_set)
> > > gamma_lut_size = MTK_LUT_SIZE;
> > > }
> > > @@ -812,7 +818,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > >
> > > if (gamma_lut_size)
> > > drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> > > - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
> > > + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
> >
> > May enable color management when has gamma or ctm.
> >
> > Regards,
> > CK
> >
> drm_crtc_enable_color_mgmt will check the parameter validation.
> if has_ctm is false, will not attach ctm property.
> if gamma_lut_size is zero, will not attach gamma property.
You're right. So
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
>
> > > priv->num_pipes++;
> > > mutex_init(&mtk_crtc->hw_lock);
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > index cb3296f..182990a 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > @@ -37,7 +37,15 @@
> > > #define CCORR_EN BIT(0)
> > > #define DISP_CCORR_CFG 0x0020
> > > #define CCORR_RELAY_MODE BIT(0)
> > > +#define CCORR_ENGINE_EN BIT(1)
> > > +#define CCORR_GAMMA_OFF BIT(2)
> > > +#define CCORR_WGAMUT_SRC_CLIP BIT(3)
> > > #define DISP_CCORR_SIZE 0x0030
> > > +#define DISP_CCORR_COEF_0 0x0080
> > > +#define DISP_CCORR_COEF_1 0x0084
> > > +#define DISP_CCORR_COEF_2 0x0088
> > > +#define DISP_CCORR_COEF_3 0x008C
> > > +#define DISP_CCORR_COEF_4 0x0090
> > >
> > > #define DISP_DITHER_EN 0x0000
> > > #define DITHER_EN BIT(0)
> > > @@ -188,7 +196,7 @@ static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
> > > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > > {
> > > mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
> > > - mtk_ddp_write(cmdq_pkt, CCORR_RELAY_MODE, comp, DISP_CCORR_CFG);
> > > + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
> > > }
> > >
> > > static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
> > > @@ -201,6 +209,57 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
> > > writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
> > > }
> > >
> > > +/* Converts a DRM S31.32 value to the HW S1.10 format. */
> > > +static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
> > > +{
> > > + u16 r;
> > > +
> > > + /* Sign bit. */
> > > + r = in & BIT_ULL(63) ? BIT(11) : 0;
> > > +
> > > + if ((in & GENMASK_ULL(62, 33)) > 0) {
> > > + /* identity value 0x100000000 -> 0x400, */
> > > + /* if bigger this, set it to max 0x7ff. */
> > > + r |= GENMASK(10, 0);
> > > + } else {
> > > + /* take the 11 most important bits. */
> > > + r |= (in >> 22) & GENMASK(10, 0);
> > > + }
> > > +
> > > + return r;
> > > +}
> > > +
> > > +static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
> > > + struct drm_crtc_state *state)
> > > +{
> > > + struct drm_property_blob *blob = state->ctm;
> > > + struct drm_color_ctm *ctm;
> > > + const u64 *input;
> > > + uint16_t coeffs[9] = { 0 };
> > > + int i;
> > > + struct cmdq_pkt *cmdq_pkt = NULL;
> > > +
> > > + if (!blob)
> > > + return;
> > > +
> > > + ctm = (struct drm_color_ctm *)blob->data;
> > > + input = ctm->matrix;
> > > +
> > > + for (i = 0; i < ARRAY_SIZE(coeffs); i++)
> > > + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
> > > +
> > > + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
> > > + comp, DISP_CCORR_COEF_0);
> > > + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
> > > + comp, DISP_CCORR_COEF_1);
> > > + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
> > > + comp, DISP_CCORR_COEF_2);
> > > + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
> > > + comp, DISP_CCORR_COEF_3);
> > > + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
> > > + comp, DISP_CCORR_COEF_4);
> > > +}
> > > +
> > > static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
> > > unsigned int h, unsigned int vrefresh,
> > > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > > @@ -271,6 +330,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
> > > .config = mtk_ccorr_config,
> > > .start = mtk_ccorr_start,
> > > .stop = mtk_ccorr_stop,
> > > + .ctm_set = mtk_ccorr_ctm_set,
> > > };
> > >
> > > static const struct mtk_ddp_comp_funcs ddp_dither = {
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > > index 384abae..20fe55d 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > > @@ -92,6 +92,8 @@ struct mtk_ddp_comp_funcs {
> > > struct drm_crtc_state *state);
> > > void (*bgclr_in_on)(struct mtk_ddp_comp *comp);
> > > void (*bgclr_in_off)(struct mtk_ddp_comp *comp);
> > > + void (*ctm_set)(struct mtk_ddp_comp *comp,
> > > + struct drm_crtc_state *state);
> > > };
> > >
> > > struct mtk_ddp_comp {
> > > @@ -205,6 +207,13 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp)
> > > comp->funcs->bgclr_in_off(comp);
> > > }
> > >
> > > +static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
> > > + struct drm_crtc_state *state)
> > > +{
> > > + if (comp->funcs && comp->funcs->ctm_set)
> > > + comp->funcs->ctm_set(comp, state);
> > > +}
> > > +
> > > int mtk_ddp_comp_get_id(struct device_node *node,
> > > enum mtk_ddp_comp_type comp_type);
> > > int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
> >
> >
>
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 0/2] drm/mediatek: Add ctm property support
2019-12-13 7:28 ` Yongqiang Niu
(?)
(?)
@ 2019-12-24 2:18 ` CK Hu
-1 siblings, 0 replies; 44+ messages in thread
From: CK Hu @ 2019-12-24 2:18 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Philipp Zabel, Rob Herring, Matthias Brugger, David Airlie,
Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
Hi, Yongqiang:
On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> Changes since v1:
> -separate gamma patch
> -remove cmdq support for ctm setting
>
For this series, applied to mediatek-drm-next-5.6 [1], thanks.
[1]
https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.6
Regards,
CK
>
> Yongqiang Niu (2):
> drm/mediatek: Fix gamma correction issue
> drm/mediatek: Add ctm property support
>
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +++++++--
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
> 3 files changed, 85 insertions(+), 4 deletions(-)
>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 0/2] drm/mediatek: Add ctm property support
@ 2019-12-24 2:18 ` CK Hu
0 siblings, 0 replies; 44+ messages in thread
From: CK Hu @ 2019-12-24 2:18 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Daniel Vetter, Matthias Brugger, linux-arm-kernel
Hi, Yongqiang:
On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> Changes since v1:
> -separate gamma patch
> -remove cmdq support for ctm setting
>
For this series, applied to mediatek-drm-next-5.6 [1], thanks.
[1]
https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.6
Regards,
CK
>
> Yongqiang Niu (2):
> drm/mediatek: Fix gamma correction issue
> drm/mediatek: Add ctm property support
>
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +++++++--
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
> 3 files changed, 85 insertions(+), 4 deletions(-)
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 0/2] drm/mediatek: Add ctm property support
@ 2019-12-24 2:18 ` CK Hu
0 siblings, 0 replies; 44+ messages in thread
From: CK Hu @ 2019-12-24 2:18 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Daniel Vetter, Matthias Brugger, linux-arm-kernel
Hi, Yongqiang:
On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> Changes since v1:
> -separate gamma patch
> -remove cmdq support for ctm setting
>
For this series, applied to mediatek-drm-next-5.6 [1], thanks.
[1]
https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.6
Regards,
CK
>
> Yongqiang Niu (2):
> drm/mediatek: Fix gamma correction issue
> drm/mediatek: Add ctm property support
>
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +++++++--
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
> 3 files changed, 85 insertions(+), 4 deletions(-)
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2, 0/2] drm/mediatek: Add ctm property support
@ 2019-12-24 2:18 ` CK Hu
0 siblings, 0 replies; 44+ messages in thread
From: CK Hu @ 2019-12-24 2:18 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel,
Rob Herring, linux-mediatek, Matthias Brugger, linux-arm-kernel
Hi, Yongqiang:
On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> Changes since v1:
> -separate gamma patch
> -remove cmdq support for ctm setting
>
For this series, applied to mediatek-drm-next-5.6 [1], thanks.
[1]
https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.6
Regards,
CK
>
> Yongqiang Niu (2):
> drm/mediatek: Fix gamma correction issue
> drm/mediatek: Add ctm property support
>
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +++++++--
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
> 3 files changed, 85 insertions(+), 4 deletions(-)
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 44+ messages in thread
end of thread, other threads:[~2019-12-24 2:18 UTC | newest]
Thread overview: 44+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-12-13 7:28 [PATCH v2, 0/2] drm/mediatek: Add ctm property support Yongqiang Niu
2019-12-13 7:28 ` Yongqiang Niu
2019-12-13 7:28 ` Yongqiang Niu
2019-12-13 7:28 ` Yongqiang Niu
2019-12-13 7:28 ` [PATCH v2, 1/2] drm/mediatek: Fix gamma correction issue Yongqiang Niu
2019-12-13 7:28 ` Yongqiang Niu
2019-12-13 7:28 ` Yongqiang Niu
2019-12-13 7:28 ` Yongqiang Niu
2019-12-13 7:48 ` CK Hu
2019-12-13 7:48 ` CK Hu
2019-12-13 7:48 ` CK Hu
2019-12-13 7:48 ` CK Hu
2019-12-13 8:03 ` Yongqiang Niu
2019-12-13 8:03 ` Yongqiang Niu
2019-12-13 8:03 ` Yongqiang Niu
2019-12-13 8:03 ` Yongqiang Niu
2019-12-13 8:09 ` CK Hu
2019-12-13 8:09 ` CK Hu
2019-12-13 8:09 ` CK Hu
2019-12-13 8:09 ` CK Hu
2019-12-13 7:28 ` [PATCH v2, 2/2] drm/mediatek: Add ctm property support Yongqiang Niu
2019-12-13 7:28 ` Yongqiang Niu
2019-12-13 7:28 ` Yongqiang Niu
2019-12-13 7:28 ` Yongqiang Niu
2019-12-13 7:57 ` CK Hu
2019-12-13 7:57 ` CK Hu
2019-12-13 7:57 ` CK Hu
2019-12-13 7:57 ` CK Hu
2019-12-13 8:11 ` Yongqiang Niu
2019-12-13 8:11 ` Yongqiang Niu
2019-12-13 8:11 ` Yongqiang Niu
2019-12-13 8:11 ` Yongqiang Niu
2019-12-13 8:13 ` CK Hu
2019-12-13 8:13 ` CK Hu
2019-12-13 8:13 ` CK Hu
2019-12-13 8:13 ` CK Hu
2019-12-13 7:49 ` [PATCH v2, 0/2] " CK Hu
2019-12-13 7:49 ` CK Hu
2019-12-13 7:49 ` CK Hu
2019-12-13 7:49 ` CK Hu
2019-12-24 2:18 ` CK Hu
2019-12-24 2:18 ` CK Hu
2019-12-24 2:18 ` CK Hu
2019-12-24 2:18 ` CK Hu
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