* [PATCH 0/2] Convert QSPI binding to YAML and add interconnect doc @ 2020-02-17 9:49 Akash Asthana 2020-02-17 9:49 ` [PATCH 1/2] dt-bindings: spi: Convert QSPI bindings to YAML Akash Asthana 2020-02-17 9:49 ` [PATCH 2/2] dt-bindings: spi: Add interconnect binding for QSPI Akash Asthana 0 siblings, 2 replies; 6+ messages in thread From: Akash Asthana @ 2020-02-17 9:49 UTC (permalink / raw) To: robh+dt, agross, mark.rutland Cc: linux-arm-msm, devicetree, linux-kernel, mgautam, rojay, skakit, swboyd, Akash Asthana Akash Asthana (2): dt-bindings: spi: Convert QSPI bindings to YAML dt-bindings: spi: Add interconnect binding for QSPI .../devicetree/bindings/spi/qcom,spi-qcom-qspi.txt | 36 -------- .../bindings/spi/qcom,spi-qcom-qspi.yaml | 97 ++++++++++++++++++++++ 2 files changed, 97 insertions(+), 36 deletions(-) delete mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] dt-bindings: spi: Convert QSPI bindings to YAML 2020-02-17 9:49 [PATCH 0/2] Convert QSPI binding to YAML and add interconnect doc Akash Asthana @ 2020-02-17 9:49 ` Akash Asthana 2020-02-20 2:29 ` Stephen Boyd 2020-02-17 9:49 ` [PATCH 2/2] dt-bindings: spi: Add interconnect binding for QSPI Akash Asthana 1 sibling, 1 reply; 6+ messages in thread From: Akash Asthana @ 2020-02-17 9:49 UTC (permalink / raw) To: robh+dt, agross, mark.rutland Cc: linux-arm-msm, devicetree, linux-kernel, mgautam, rojay, skakit, swboyd, Akash Asthana Convert QSPI bindings to DT schema format using json-schema. Signed-off-by: Akash Asthana <akashast@codeaurora.org> --- .../devicetree/bindings/spi/qcom,spi-qcom-qspi.txt | 36 --------- .../bindings/spi/qcom,spi-qcom-qspi.yaml | 89 ++++++++++++++++++++++ 2 files changed, 89 insertions(+), 36 deletions(-) delete mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt deleted file mode 100644 index 1d64b61..0000000 --- a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt +++ /dev/null @@ -1,36 +0,0 @@ -Qualcomm Quad Serial Peripheral Interface (QSPI) - -The QSPI controller allows SPI protocol communication in single, dual, or quad -wire transmission modes for read/write access to slaves such as NOR flash. - -Required properties: -- compatible: An SoC specific identifier followed by "qcom,qspi-v1", such as - "qcom,sdm845-qspi", "qcom,qspi-v1" -- reg: Should contain the base register location and length. -- interrupts: Interrupt number used by the controller. -- clocks: Should contain the core and AHB clock. -- clock-names: Should be "core" for core clock and "iface" for AHB clock. - -SPI slave nodes must be children of the SPI master node and can contain -properties described in Documentation/devicetree/bindings/spi/spi-bus.txt - -Example: - - qspi: spi@88df000 { - compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; - reg = <0x88df000 0x600>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "iface", "core"; - clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, - <&gcc GCC_QSPI_CORE_CLK>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <25000000>; - spi-tx-bus-width = <2>; - spi-rx-bus-width = <2>; - }; - }; diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml new file mode 100644 index 0000000..977070a --- /dev/null +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Quad Serial Peripheral Interface (QSPI) + +maintainers: + - Mukesh Savaliya <msavaliy@codeaurora.org> + - Akash Asthana <akashast@codeaurora.org> + +description: | + The QSPI controller allows SPI protocol communication in single, dual, or quad + wire transmission modes for read/write access to slaves such as NOR flash. + +allOf: + - $ref: /spi/spi-controller.yaml# + +properties: + compatible: + items: + - const: qcom,sdm845-qspi + - const: qcom,qspi-v1 + + reg: + description: Base register location and length. + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-names: + items: + - const: iface + - const: core + + clocks: + items: + - description: AHB clock + - description: QSPI core clock. + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +required: + - compatible + - reg + - interrupts + - clock-names + - clocks + - "#address-cells" + - "#size-cells" + + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc: soc@0 { + #address-cells = <2>; + #size-cells = <2>; + + qspi: spi@88df000 { + compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; + reg = <0 0x88df000 0 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "iface", "core"; + clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <&gcc GCC_QSPI_CORE_CLK>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; + }; + }; + +... -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] dt-bindings: spi: Convert QSPI bindings to YAML 2020-02-17 9:49 ` [PATCH 1/2] dt-bindings: spi: Convert QSPI bindings to YAML Akash Asthana @ 2020-02-20 2:29 ` Stephen Boyd 2020-03-13 10:51 ` Akash Asthana 0 siblings, 1 reply; 6+ messages in thread From: Stephen Boyd @ 2020-02-20 2:29 UTC (permalink / raw) To: Akash Asthana, agross, mark.rutland, robh+dt Cc: linux-arm-msm, devicetree, linux-kernel, mgautam, rojay, skakit, Akash Asthana Quoting Akash Asthana (2020-02-17 01:49:33) > diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml > new file mode 100644 > index 0000000..977070a > --- /dev/null > +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml > @@ -0,0 +1,89 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > + > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Qualcomm Quad Serial Peripheral Interface (QSPI) > + > +maintainers: > + - Mukesh Savaliya <msavaliy@codeaurora.org> > + - Akash Asthana <akashast@codeaurora.org> > + > +description: | Drop the | because it doesn't look like any formatting needs to be maintained in the text for the description. > + The QSPI controller allows SPI protocol communication in single, dual, or quad > + wire transmission modes for read/write access to slaves such as NOR flash. > + > +allOf: > + - $ref: /spi/spi-controller.yaml# > + > +properties: > + compatible: > + items: > + - const: qcom,sdm845-qspi > + - const: qcom,qspi-v1 > + > + reg: > + description: Base register location and length. Drop description? It doesn't seem useful. > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clock-names: > + items: > + - const: iface > + - const: core > + > + clocks: > + items: > + - description: AHB clock > + - description: QSPI core clock. Please drop the full-stop on core clock. > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 0 Aren't these two unnecessary because they're covered by the spi-controller.yaml binding? > + > +required: > + - compatible > + - reg > + - interrupts > + - clock-names > + - clocks > + - "#address-cells" > + - "#size-cells" These last two are also covered by spi-controller binding. > + > + Why two newlines instead of one? > +examples: > + - | > + #include <dt-bindings/clock/qcom,gcc-sdm845.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + soc: soc@0 { Remove this node from example please. > + #address-cells = <2>; > + #size-cells = <2>; > + > + qspi: spi@88df000 { > + compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; > + reg = <0 0x88df000 0 0x600>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "iface", "core"; > + clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, > + <&gcc GCC_QSPI_CORE_CLK>; Weird tabbing here. Just use spaces and align it up. > + > + flash@0 { > + compatible = "jedec,spi-nor"; > + reg = <0>; > + spi-max-frequency = <25000000>; > + spi-tx-bus-width = <2>; > + spi-rx-bus-width = <2>; > + }; Is this flash node necessary for the example? > + }; > + }; > + Nitpick: Why newline here? > +... ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] dt-bindings: spi: Convert QSPI bindings to YAML 2020-02-20 2:29 ` Stephen Boyd @ 2020-03-13 10:51 ` Akash Asthana 0 siblings, 0 replies; 6+ messages in thread From: Akash Asthana @ 2020-03-13 10:51 UTC (permalink / raw) To: Stephen Boyd, agross, mark.rutland, robh+dt Cc: linux-arm-msm, devicetree, linux-kernel, mgautam, rojay, skakit Hi Stephen, On 2/20/2020 7:59 AM, Stephen Boyd wrote: > Quoting Akash Asthana (2020-02-17 01:49:33) >> diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml >> new file mode 100644 >> index 0000000..977070a >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml >> @@ -0,0 +1,89 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> + >> +%YAML 1.2 >> +--- >> +$id:"http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#" >> +$schema:"http://devicetree.org/meta-schemas/core.yaml#" >> + >> +title: Qualcomm Quad Serial Peripheral Interface (QSPI) >> + >> +maintainers: >> + - Mukesh Savaliya<msavaliy@codeaurora.org> >> + - Akash Asthana<akashast@codeaurora.org> >> + >> +description: | > Drop the | because it doesn't look like any formatting needs to be > maintained in the text for the description. ok >> + The QSPI controller allows SPI protocol communication in single, dual, or quad >> + wire transmission modes for read/write access to slaves such as NOR flash. >> + >> +allOf: >> + - $ref: /spi/spi-controller.yaml# >> + >> +properties: >> + compatible: >> + items: >> + - const: qcom,sdm845-qspi >> + - const: qcom,qspi-v1 >> + >> + reg: >> + description: Base register location and length. > Drop description? It doesn't seem useful. ok >> + maxItems: 1 >> + >> + interrupts: >> + maxItems: 1 >> + >> + clock-names: >> + items: >> + - const: iface >> + - const: core >> + >> + clocks: >> + items: >> + - description: AHB clock >> + - description: QSPI core clock. > Please drop the full-stop on core clock. ok >> + >> + "#address-cells": >> + const: 1 >> + >> + "#size-cells": >> + const: 0 > Aren't these two unnecessary because they're covered by the > spi-controller.yaml binding? ok > >> + >> +required: >> + - compatible >> + - reg >> + - interrupts >> + - clock-names >> + - clocks >> + - "#address-cells" >> + - "#size-cells" > These last two are also covered by spi-controller binding. ok will remove >> + >> + > Why two newlines instead of one? > >> +examples: >> + - | >> + #include <dt-bindings/clock/qcom,gcc-sdm845.h> >> + #include <dt-bindings/interrupt-controller/arm-gic.h> >> + >> + soc: soc@0 { > Remove this node from example please. If I remove this node I am getting below compilation error. Error: Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.example.dts:46.1-2 syntax error FATAL ERROR: Unable to parse input tree scripts/Makefile.lib:311: recipe for target 'Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.example.dt.yaml' failed make[1]: *** [Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.example.dt.yaml] Error 1 Makefile:1264: recipe for target 'dt_binding_check' failed make: *** [dt_binding_check] Error 2 > >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + qspi: spi@88df000 { >> + compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; >> + reg = <0 0x88df000 0 0x600>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "iface", "core"; >> + clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, >> + <&gcc GCC_QSPI_CORE_CLK>; > Weird tabbing here. Just use spaces and align it up. Ok, I will align it better. > >> + >> + flash@0 { >> + compatible = "jedec,spi-nor"; >> + reg = <0>; >> + spi-max-frequency = <25000000>; >> + spi-tx-bus-width = <2>; >> + spi-rx-bus-width = <2>; >> + }; > Is this flash node necessary for the example? It's not neccessary. I just preserved the original example from .txt binding file. > >> + }; >> + }; >> + > Nitpick: Why newline here? Will remove it. Thankyou for reviewing the patch. Regards, Akash > >> +... -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] dt-bindings: spi: Add interconnect binding for QSPI 2020-02-17 9:49 [PATCH 0/2] Convert QSPI binding to YAML and add interconnect doc Akash Asthana 2020-02-17 9:49 ` [PATCH 1/2] dt-bindings: spi: Convert QSPI bindings to YAML Akash Asthana @ 2020-02-17 9:49 ` Akash Asthana 2020-02-20 2:30 ` Stephen Boyd 1 sibling, 1 reply; 6+ messages in thread From: Akash Asthana @ 2020-02-17 9:49 UTC (permalink / raw) To: robh+dt, agross, mark.rutland Cc: linux-arm-msm, devicetree, linux-kernel, mgautam, rojay, skakit, swboyd, Akash Asthana Add documentation for the interconnect and interconnect-names properties for QSPI. Signed-off-by: Akash Asthana <akashast@codeaurora.org> --- Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml index 977070a..b58bd73 100644 --- a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml @@ -47,6 +47,14 @@ properties: "#size-cells": const: 0 + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: qspi-config + - const: qspi-memory + required: - compatible - reg -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] dt-bindings: spi: Add interconnect binding for QSPI 2020-02-17 9:49 ` [PATCH 2/2] dt-bindings: spi: Add interconnect binding for QSPI Akash Asthana @ 2020-02-20 2:30 ` Stephen Boyd 0 siblings, 0 replies; 6+ messages in thread From: Stephen Boyd @ 2020-02-20 2:30 UTC (permalink / raw) To: Akash Asthana, agross, mark.rutland, robh+dt Cc: linux-arm-msm, devicetree, linux-kernel, mgautam, rojay, skakit, Akash Asthana Quoting Akash Asthana (2020-02-17 01:49:34) > Add documentation for the interconnect and interconnect-names > properties for QSPI. > > Signed-off-by: Akash Asthana <akashast@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org> ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-03-13 10:51 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-02-17 9:49 [PATCH 0/2] Convert QSPI binding to YAML and add interconnect doc Akash Asthana 2020-02-17 9:49 ` [PATCH 1/2] dt-bindings: spi: Convert QSPI bindings to YAML Akash Asthana 2020-02-20 2:29 ` Stephen Boyd 2020-03-13 10:51 ` Akash Asthana 2020-02-17 9:49 ` [PATCH 2/2] dt-bindings: spi: Add interconnect binding for QSPI Akash Asthana 2020-02-20 2:30 ` Stephen Boyd
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