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From: Chris Wilson <chris.p.wilson@intel.com>
To: akeem.g.abodunrin@intel.com, d.scott.phillips@intel.com,
	daniel.vetter@intel.com, david.c.stewart@intel.com,
	dri-devel@lists.freedesktop.org, francesco.balestrieri@intel.com,
	intel-gfx@lists.freedesktop.org, jani.nikula@intel.com,
	jon.bloomfield@intel.com, joonas.lahtinen@linux.intel.com,
	mika.kuoppala@intel.com, omer.aran@intel.com,
	pragyansri.pathi@intel.com, prathap.kumar.valsan@intel.com,
	sudeep.dutt@intel.com, tony.luck@intel.com
Subject: Re: [PATCH v4 1/2] drm/i915: Add mechanism to submit a context WA on ring submission
Date: Fri, 21 Feb 2020 14:48:28 +0000	[thread overview]
Message-ID: <158229650841.6499.5335926375673137684@skylake-alporthouse-com> (raw)
In-Reply-To: <20200220230023.18905-2-akeem.g.abodunrin@intel.com>

Quoting Akeem G Abodunrin (2020-02-20 23:00:22)
> From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> 
> This patch adds framework to submit an arbitrary batchbuffer on each
> context switch to clear residual state for render engine on Gen7/7.5
> devices.
> 
> The idea of always emitting the context and vm setup around each request
> is primary to make reset recovery easy, and not require rewriting the
> ringbuffer. As each request would set up its own context, leaving it to
> the HW to notice and elide no-op context switches, we could restart the
> ring at any point, and reorder the requests freely.
> 
> However, to avoid emitting clear_residuals() between consecutive requests
> in the ringbuffer of the same context, we do want to track the current
> context in the ring. In doing so, we need to be careful to only record a
> context switch when we are sure the next request will be emitted.
> 
> This security mitigation change does not trigger any performance
> regression. Performance is on par with current mainline/drm-tip.
> 
> v2: Update vm_alias params to point to correct address space "vm" due to
> changes made in the patch "f21613797bae98773"
> 
> v3-v4: none
> 
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Balestrieri Francesco <francesco.balestrieri@intel.com>
> Cc: Bloomfield Jon <jon.bloomfield@intel.com>
> Cc: Dutt Sudeep <sudeep.dutt@intel.com>
Reviewed-by: Chris Wilson <chris.p.wilson@intel.com>
-Chris
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Intel Corporation (UK) Limited
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Registered Office: Pipers Way, Swindon SN3 1RJ
VAT No: 860 2173 47

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WARNING: multiple messages have this Message-ID (diff)
From: Chris Wilson <chris.p.wilson@intel.com>
To: akeem.g.abodunrin@intel.com, d.scott.phillips@intel.com,
	daniel.vetter@intel.com, david.c.stewart@intel.com,
	dri-devel@lists.freedesktop.org, francesco.balestrieri@intel.com,
	intel-gfx@lists.freedesktop.org, jani.nikula@intel.com,
	jon.bloomfield@intel.com, joonas.lahtinen@linux.intel.com,
	mika.kuoppala@intel.com, omer.aran@intel.com,
	pragyansri.pathi@intel.com, prathap.kumar.valsan@intel.com,
	sudeep.dutt@intel.com, tony.luck@intel.com
Subject: Re: [Intel-gfx] [PATCH v4 1/2] drm/i915: Add mechanism to submit a context WA on ring submission
Date: Fri, 21 Feb 2020 14:48:28 +0000	[thread overview]
Message-ID: <158229650841.6499.5335926375673137684@skylake-alporthouse-com> (raw)
In-Reply-To: <20200220230023.18905-2-akeem.g.abodunrin@intel.com>

Quoting Akeem G Abodunrin (2020-02-20 23:00:22)
> From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> 
> This patch adds framework to submit an arbitrary batchbuffer on each
> context switch to clear residual state for render engine on Gen7/7.5
> devices.
> 
> The idea of always emitting the context and vm setup around each request
> is primary to make reset recovery easy, and not require rewriting the
> ringbuffer. As each request would set up its own context, leaving it to
> the HW to notice and elide no-op context switches, we could restart the
> ring at any point, and reorder the requests freely.
> 
> However, to avoid emitting clear_residuals() between consecutive requests
> in the ringbuffer of the same context, we do want to track the current
> context in the ring. In doing so, we need to be careful to only record a
> context switch when we are sure the next request will be emitted.
> 
> This security mitigation change does not trigger any performance
> regression. Performance is on par with current mainline/drm-tip.
> 
> v2: Update vm_alias params to point to correct address space "vm" due to
> changes made in the patch "f21613797bae98773"
> 
> v3-v4: none
> 
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Balestrieri Francesco <francesco.balestrieri@intel.com>
> Cc: Bloomfield Jon <jon.bloomfield@intel.com>
> Cc: Dutt Sudeep <sudeep.dutt@intel.com>
Reviewed-by: Chris Wilson <chris.p.wilson@intel.com>
-Chris
---------------------------------------------------------------------
Intel Corporation (UK) Limited
Registered No. 1134945 (England)
Registered Office: Pipers Way, Swindon SN3 1RJ
VAT No: 860 2173 47

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2020-02-21 14:48 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-20 23:00 [PATCH v4 0/2] Security mitigation for Intel Gen7/7.5 HWs Akeem G Abodunrin
2020-02-20 23:00 ` [Intel-gfx] " Akeem G Abodunrin
2020-02-20 23:00 ` [PATCH v4 1/2] drm/i915: Add mechanism to submit a context WA on ring submission Akeem G Abodunrin
2020-02-20 23:00   ` [Intel-gfx] " Akeem G Abodunrin
2020-02-21 14:48   ` Chris Wilson [this message]
2020-02-21 14:48     ` Chris Wilson
2020-02-20 23:00 ` [PATCH v4 2/2] drm/i915/gen7: Clear all EU/L3 residual contexts Akeem G Abodunrin
2020-02-20 23:00   ` [Intel-gfx] " Akeem G Abodunrin
2020-02-21 14:56   ` Chris Wilson
2020-02-21 14:56     ` [Intel-gfx] " Chris Wilson
2020-02-21  7:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Security mitigation for Intel Gen7/7.5 HWs Patchwork
2020-02-21  7:54 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-02-24  0:13 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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