From: Chris Wilson <chris.p.wilson@intel.com> To: akeem.g.abodunrin@intel.com, d.scott.phillips@intel.com, daniel.vetter@intel.com, david.c.stewart@intel.com, dri-devel@lists.freedesktop.org, francesco.balestrieri@intel.com, intel-gfx@lists.freedesktop.org, jani.nikula@intel.com, jon.bloomfield@intel.com, joonas.lahtinen@linux.intel.com, mika.kuoppala@intel.com, omer.aran@intel.com, pragyansri.pathi@intel.com, prathap.kumar.valsan@intel.com, sudeep.dutt@intel.com, tony.luck@intel.com Subject: Re: [PATCH v4 2/2] drm/i915/gen7: Clear all EU/L3 residual contexts Date: Fri, 21 Feb 2020 14:56:19 +0000 [thread overview] Message-ID: <158229697947.6499.9383893602491436028@skylake-alporthouse-com> (raw) In-Reply-To: <20200220230023.18905-3-akeem.g.abodunrin@intel.com> Quoting Akeem G Abodunrin (2020-02-20 23:00:23) > +static void emit_batch(struct i915_vma * const vma, > + u32 *start, > + const struct batch_vals *bv) > +{ > + struct drm_i915_private *i915 = vma->vm->i915; > + unsigned int desc_count = 64; > + const u32 urb_size = 112; > + struct batch_chunk cmds, state; > + u32 interface_descriptor; > + unsigned int i; > + > + batch_init(&cmds, vma, start, 0, bv->cmd_size); > + batch_init(&state, vma, start, bv->state_start, bv->state_size); > + > + interface_descriptor = > + gen7_fill_interface_descriptor(&state, bv, > + IS_HASWELL(i915) ? > + &cb_kernel_hsw : > + &cb_kernel_ivb, > + desc_count); Negligible in the grand scheme of things, but there was a STATE_CACHE_INVALIDATION flush just prior to this batch. > + gen7_emit_pipeline_flush(&cmds); > + batch_add(&cmds, PIPELINE_SELECT | PIPELINE_SELECT_MEDIA); > + batch_add(&cmds, MI_NOOP); What's the reason for the noop here? > + gen7_emit_state_base_address(&cmds, interface_descriptor); > + gen7_emit_pipeline_flush(&cmds); And iirc, this is recommended for SBI. Does this flush require a CS_STALL? > + gen7_emit_vfe_state(&cmds, bv, urb_size - 1, 0, 0); > + > + gen7_emit_interface_descriptor_load(&cmds, > + interface_descriptor, > + desc_count); > + > + for (i = 0; i < bv->max_primitives; i++) > + gen7_emit_media_object(&cmds, i); > + > + batch_add(&cmds, MI_BATCH_BUFFER_END); > +} I can't comment on the efficacy of the kernels, but the code is finally passing CI and the batch takes long enough that it has to be doing something! Just running a giant loop mostly. Acked-by: Chris Wilson <chris.p.wilson@intel.com> -Chris --------------------------------------------------------------------- Intel Corporation (UK) Limited Registered No. 1134945 (England) Registered Office: Pipers Way, Swindon SN3 1RJ VAT No: 860 2173 47 This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Chris Wilson <chris.p.wilson@intel.com> To: akeem.g.abodunrin@intel.com, d.scott.phillips@intel.com, daniel.vetter@intel.com, david.c.stewart@intel.com, dri-devel@lists.freedesktop.org, francesco.balestrieri@intel.com, intel-gfx@lists.freedesktop.org, jani.nikula@intel.com, jon.bloomfield@intel.com, joonas.lahtinen@linux.intel.com, mika.kuoppala@intel.com, omer.aran@intel.com, pragyansri.pathi@intel.com, prathap.kumar.valsan@intel.com, sudeep.dutt@intel.com, tony.luck@intel.com Subject: Re: [Intel-gfx] [PATCH v4 2/2] drm/i915/gen7: Clear all EU/L3 residual contexts Date: Fri, 21 Feb 2020 14:56:19 +0000 [thread overview] Message-ID: <158229697947.6499.9383893602491436028@skylake-alporthouse-com> (raw) In-Reply-To: <20200220230023.18905-3-akeem.g.abodunrin@intel.com> Quoting Akeem G Abodunrin (2020-02-20 23:00:23) > +static void emit_batch(struct i915_vma * const vma, > + u32 *start, > + const struct batch_vals *bv) > +{ > + struct drm_i915_private *i915 = vma->vm->i915; > + unsigned int desc_count = 64; > + const u32 urb_size = 112; > + struct batch_chunk cmds, state; > + u32 interface_descriptor; > + unsigned int i; > + > + batch_init(&cmds, vma, start, 0, bv->cmd_size); > + batch_init(&state, vma, start, bv->state_start, bv->state_size); > + > + interface_descriptor = > + gen7_fill_interface_descriptor(&state, bv, > + IS_HASWELL(i915) ? > + &cb_kernel_hsw : > + &cb_kernel_ivb, > + desc_count); Negligible in the grand scheme of things, but there was a STATE_CACHE_INVALIDATION flush just prior to this batch. > + gen7_emit_pipeline_flush(&cmds); > + batch_add(&cmds, PIPELINE_SELECT | PIPELINE_SELECT_MEDIA); > + batch_add(&cmds, MI_NOOP); What's the reason for the noop here? > + gen7_emit_state_base_address(&cmds, interface_descriptor); > + gen7_emit_pipeline_flush(&cmds); And iirc, this is recommended for SBI. Does this flush require a CS_STALL? > + gen7_emit_vfe_state(&cmds, bv, urb_size - 1, 0, 0); > + > + gen7_emit_interface_descriptor_load(&cmds, > + interface_descriptor, > + desc_count); > + > + for (i = 0; i < bv->max_primitives; i++) > + gen7_emit_media_object(&cmds, i); > + > + batch_add(&cmds, MI_BATCH_BUFFER_END); > +} I can't comment on the efficacy of the kernels, but the code is finally passing CI and the batch takes long enough that it has to be doing something! Just running a giant loop mostly. Acked-by: Chris Wilson <chris.p.wilson@intel.com> -Chris --------------------------------------------------------------------- Intel Corporation (UK) Limited Registered No. 1134945 (England) Registered Office: Pipers Way, Swindon SN3 1RJ VAT No: 860 2173 47 This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-02-21 14:56 UTC|newest] Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-02-20 23:00 [PATCH v4 0/2] Security mitigation for Intel Gen7/7.5 HWs Akeem G Abodunrin 2020-02-20 23:00 ` [Intel-gfx] " Akeem G Abodunrin 2020-02-20 23:00 ` [PATCH v4 1/2] drm/i915: Add mechanism to submit a context WA on ring submission Akeem G Abodunrin 2020-02-20 23:00 ` [Intel-gfx] " Akeem G Abodunrin 2020-02-21 14:48 ` Chris Wilson 2020-02-21 14:48 ` [Intel-gfx] " Chris Wilson 2020-02-20 23:00 ` [PATCH v4 2/2] drm/i915/gen7: Clear all EU/L3 residual contexts Akeem G Abodunrin 2020-02-20 23:00 ` [Intel-gfx] " Akeem G Abodunrin 2020-02-21 14:56 ` Chris Wilson [this message] 2020-02-21 14:56 ` Chris Wilson 2020-02-21 7:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Security mitigation for Intel Gen7/7.5 HWs Patchwork 2020-02-21 7:54 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-02-24 0:13 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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