[Intel-gfx] [PATCH 1/6] drm/i915: Nuke pointless div by 64bit

[Intel-gfx] [PATCH 1/6] drm/i915: Nuke pointless div by 64bit

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Bunch of places use a 64bit divisor needlessly. Switch
to 32bit divisor.

Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_perf.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2334c45f1d08..716fe6e4e56c 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1667,10 +1667,9 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
 	struct drm_i915_gem_object *bo;
 	struct i915_vma *vma;
 	const u64 delay_ticks = 0xffffffffffffffff -
-		DIV64_U64_ROUND_UP(
-			atomic64_read(&stream->perf->noa_programming_delay) *
-			RUNTIME_INFO(i915)->cs_timestamp_frequency_khz,
-			1000000ull);
+		DIV_ROUND_UP_ULL(atomic64_read(&stream->perf->noa_programming_delay) *
+				 RUNTIME_INFO(i915)->cs_timestamp_frequency_khz,
+				 1000000);
 	const u32 base = stream->engine->mmio_base;
 #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
 	u32 *batch, *ts0, *cs, *jump;
@@ -3467,8 +3466,8 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
 
 static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
 {
-	return div64_u64(1000000000ULL * (2ULL << exponent),
-			 1000ULL * RUNTIME_INFO(perf->i915)->cs_timestamp_frequency_khz);
+	return div_u64(1000000 * (2ULL << exponent),
+		       RUNTIME_INFO(perf->i915)->cs_timestamp_frequency_khz);
 }
 
 /**
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 2/6] drm/i915: Store CS timestamp frequency in Hz

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

kHz isn't accurate enough for storing the CS timestamp
frequency on some of the platforms. Store the value
in Hz instead.

Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c        |  6 ++--
 drivers/gpu/drm/i915/i915_getparam.c       |  2 +-
 drivers/gpu/drm/i915/i915_perf.c           | 12 ++++----
 drivers/gpu/drm/i915/intel_device_info.c   | 34 +++++++++++-----------
 drivers/gpu/drm/i915/intel_device_info.h   |  2 +-
 drivers/gpu/drm/i915/selftests/i915_perf.c |  4 +--
 6 files changed, 30 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 8f2525e4ce0f..c0e54c500017 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1790,8 +1790,8 @@ static int i915_engine_info(struct seq_file *m, void *unused)
 	seq_printf(m, "GT awake? %s [%d]\n",
 		   yesno(dev_priv->gt.awake),
 		   atomic_read(&dev_priv->gt.wakeref.count));
-	seq_printf(m, "CS timestamp frequency: %u kHz\n",
-		   RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz);
+	seq_printf(m, "CS timestamp frequency: %u Hz\n",
+		   RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_hz);
 
 	p = drm_seq_file_printer(m);
 	for_each_uabi_engine(engine, dev_priv)
@@ -1890,7 +1890,7 @@ static int
 i915_perf_noa_delay_set(void *data, u64 val)
 {
 	struct drm_i915_private *i915 = data;
-	const u32 clk = RUNTIME_INFO(i915)->cs_timestamp_frequency_khz;
+	const u32 clk = RUNTIME_INFO(i915)->cs_timestamp_frequency_hz / 1000;
 
 	/*
 	 * This would lead to infinite waits as we're doing timestamp
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index 54fce81d5724..d042644b9cd2 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -153,7 +153,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
 			return -ENODEV;
 		break;
 	case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
-		value = 1000 * RUNTIME_INFO(i915)->cs_timestamp_frequency_khz;
+		value = RUNTIME_INFO(i915)->cs_timestamp_frequency_hz;
 		break;
 	case I915_PARAM_MMAP_GTT_COHERENT:
 		value = INTEL_INFO(i915)->has_coherent_ggtt;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 716fe6e4e56c..a2f98fb08bf1 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1668,8 +1668,8 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
 	struct i915_vma *vma;
 	const u64 delay_ticks = 0xffffffffffffffff -
 		DIV_ROUND_UP_ULL(atomic64_read(&stream->perf->noa_programming_delay) *
-				 RUNTIME_INFO(i915)->cs_timestamp_frequency_khz,
-				 1000000);
+				 RUNTIME_INFO(i915)->cs_timestamp_frequency_hz,
+				 1000000000);
 	const u32 base = stream->engine->mmio_base;
 #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
 	u32 *batch, *ts0, *cs, *jump;
@@ -3466,8 +3466,8 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
 
 static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
 {
-	return div_u64(1000000 * (2ULL << exponent),
-		       RUNTIME_INFO(perf->i915)->cs_timestamp_frequency_khz);
+	return div_u64(1000000000 * (2ULL << exponent),
+		       RUNTIME_INFO(perf->i915)->cs_timestamp_frequency_hz);
 }
 
 /**
@@ -4359,8 +4359,8 @@ void i915_perf_init(struct drm_i915_private *i915)
 	if (perf->ops.enable_metric_set) {
 		mutex_init(&perf->lock);
 
-		oa_sample_rate_hard_limit = 1000 *
-			(RUNTIME_INFO(i915)->cs_timestamp_frequency_khz / 2);
+		oa_sample_rate_hard_limit =
+			RUNTIME_INFO(i915)->cs_timestamp_frequency_hz / 2;
 
 		mutex_init(&perf->metrics_lock);
 		idr_init(&perf->metrics_idr);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index d7fe12734db8..32733535964d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -135,8 +135,8 @@ void intel_device_info_print_runtime(const struct intel_runtime_info *info,
 	sseu_dump(&info->sseu, p);
 
 	drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq);
-	drm_printf(p, "CS timestamp frequency: %u kHz\n",
-		   info->cs_timestamp_frequency_khz);
+	drm_printf(p, "CS timestamp frequency: %u Hz\n",
+		   info->cs_timestamp_frequency_hz);
 }
 
 static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
@@ -677,12 +677,12 @@ static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv)
 
 	base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >>
 		     GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1;
-	base_freq *= 1000;
+	base_freq *= 1000000;
 
 	frac_freq = ((ts_override &
 		      GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >>
 		     GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT);
-	frac_freq = 1000 / (frac_freq + 1);
+	frac_freq = 1000000 / (frac_freq + 1);
 
 	return base_freq + frac_freq;
 }
@@ -690,8 +690,8 @@ static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv)
 static u32 gen10_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
 					u32 rpm_config_reg)
 {
-	u32 f19_2_mhz = 19200;
-	u32 f24_mhz = 24000;
+	u32 f19_2_mhz = 19200000;
+	u32 f24_mhz = 24000000;
 	u32 crystal_clock = (rpm_config_reg &
 			     GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
 			    GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
@@ -710,10 +710,10 @@ static u32 gen10_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
 static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
 					u32 rpm_config_reg)
 {
-	u32 f19_2_mhz = 19200;
-	u32 f24_mhz = 24000;
-	u32 f25_mhz = 25000;
-	u32 f38_4_mhz = 38400;
+	u32 f19_2_mhz = 19200000;
+	u32 f24_mhz = 24000000;
+	u32 f25_mhz = 25000000;
+	u32 f38_4_mhz = 38400000;
 	u32 crystal_clock = (rpm_config_reg &
 			     GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
 			    GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
@@ -735,9 +735,9 @@ static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
 
 static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 {
-	u32 f12_5_mhz = 12500;
-	u32 f19_2_mhz = 19200;
-	u32 f24_mhz = 24000;
+	u32 f12_5_mhz = 12500000;
+	u32 f19_2_mhz = 19200000;
+	u32 f24_mhz = 24000000;
 
 	if (INTEL_GEN(dev_priv) <= 4) {
 		/* PRMs say:
@@ -746,7 +746,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 		 *      hclks." (through the “Clocking Configuration”
 		 *      (“CLKCFG”) MCHBAR register)
 		 */
-		return RUNTIME_INFO(dev_priv)->rawclk_freq / 16;
+		return RUNTIME_INFO(dev_priv)->rawclk_freq * 1000 / 16;
 	} else if (INTEL_GEN(dev_priv) <= 8) {
 		/* PRMs say:
 		 *
@@ -1050,11 +1050,11 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 	drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
 
 	/* Initialize command stream timestamp frequency */
-	runtime->cs_timestamp_frequency_khz =
+	runtime->cs_timestamp_frequency_hz =
 		read_timestamp_frequency(dev_priv);
-	if (runtime->cs_timestamp_frequency_khz) {
+	if (runtime->cs_timestamp_frequency_hz) {
 		runtime->cs_timestamp_period_ns =
-			div_u64(1e6, runtime->cs_timestamp_frequency_khz);
+			div_u64(1e9, runtime->cs_timestamp_frequency_hz);
 		drm_dbg(&dev_priv->drm,
 			"CS timestamp wraparound in %lldms\n",
 			div_u64(mul_u32_u32(runtime->cs_timestamp_period_ns,
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 1ecb9df2de91..432e9c7c0fe7 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -218,7 +218,7 @@ struct intel_runtime_info {
 
 	u32 rawclk_freq;
 
-	u32 cs_timestamp_frequency_khz;
+	u32 cs_timestamp_frequency_hz;
 	u32 cs_timestamp_period_ns;
 
 	/* Media engine access to SFC per instance */
diff --git a/drivers/gpu/drm/i915/selftests/i915_perf.c b/drivers/gpu/drm/i915/selftests/i915_perf.c
index d1a1568c47ba..dea0c5dd2739 100644
--- a/drivers/gpu/drm/i915/selftests/i915_perf.c
+++ b/drivers/gpu/drm/i915/selftests/i915_perf.c
@@ -180,8 +180,8 @@ static int live_noa_delay(void *arg)
 
 	delay = intel_read_status_page(stream->engine, 0x102);
 	delay -= intel_read_status_page(stream->engine, 0x100);
-	delay = div_u64(mul_u32_u32(delay, 1000 * 1000),
-			RUNTIME_INFO(i915)->cs_timestamp_frequency_khz);
+	delay = div_u64(mul_u32_u32(delay, 1000000000),
+			RUNTIME_INFO(i915)->cs_timestamp_frequency_hz);
 	pr_info("GPU delay: %uns, expected %lluns\n",
 		delay, expected);
 
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 2/6] drm/i915: Store CS timestamp frequency in Hz

[Chris Wilson]

Quoting Ville Syrjala (2020-03-02 14:39:39)
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> kHz isn't accurate enough for storing the CS timestamp
> frequency on some of the platforms. Store the value
> in Hz instead.
> 
> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c        |  6 ++--
>  drivers/gpu/drm/i915/i915_getparam.c       |  2 +-
>  drivers/gpu/drm/i915/i915_perf.c           | 12 ++++----
>  drivers/gpu/drm/i915/intel_device_info.c   | 34 +++++++++++-----------
>  drivers/gpu/drm/i915/intel_device_info.h   |  2 +-
>  drivers/gpu/drm/i915/selftests/i915_perf.c |  4 +--
>  6 files changed, 30 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 8f2525e4ce0f..c0e54c500017 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1790,8 +1790,8 @@ static int i915_engine_info(struct seq_file *m, void *unused)
>         seq_printf(m, "GT awake? %s [%d]\n",
>                    yesno(dev_priv->gt.awake),
>                    atomic_read(&dev_priv->gt.wakeref.count));
> -       seq_printf(m, "CS timestamp frequency: %u kHz\n",
> -                  RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz);
> +       seq_printf(m, "CS timestamp frequency: %u Hz\n",
> +                  RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_hz);
>  
>         p = drm_seq_file_printer(m);
>         for_each_uabi_engine(engine, dev_priv)
> @@ -1890,7 +1890,7 @@ static int
>  i915_perf_noa_delay_set(void *data, u64 val)
>  {
>         struct drm_i915_private *i915 = data;
> -       const u32 clk = RUNTIME_INFO(i915)->cs_timestamp_frequency_khz;
> +       const u32 clk = RUNTIME_INFO(i915)->cs_timestamp_frequency_hz / 1000;
>  
>         /*
>          * This would lead to infinite waits as we're doing timestamp
> diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
> index 54fce81d5724..d042644b9cd2 100644
> --- a/drivers/gpu/drm/i915/i915_getparam.c
> +++ b/drivers/gpu/drm/i915/i915_getparam.c
> @@ -153,7 +153,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
>                         return -ENODEV;
>                 break;
>         case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
> -               value = 1000 * RUNTIME_INFO(i915)->cs_timestamp_frequency_khz;
> +               value = RUNTIME_INFO(i915)->cs_timestamp_frequency_hz;
>                 break;
>         case I915_PARAM_MMAP_GTT_COHERENT:
>                 value = INTEL_INFO(i915)->has_coherent_ggtt;
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 716fe6e4e56c..a2f98fb08bf1 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1668,8 +1668,8 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
>         struct i915_vma *vma;
>         const u64 delay_ticks = 0xffffffffffffffff -
>                 DIV_ROUND_UP_ULL(atomic64_read(&stream->perf->noa_programming_delay) *
> -                                RUNTIME_INFO(i915)->cs_timestamp_frequency_khz,
> -                                1000000);
> +                                RUNTIME_INFO(i915)->cs_timestamp_frequency_hz,
> +                                1000000000);
>         const u32 base = stream->engine->mmio_base;
>  #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
>         u32 *batch, *ts0, *cs, *jump;
> @@ -3466,8 +3466,8 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
>  
>  static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
>  {
> -       return div_u64(1000000 * (2ULL << exponent),
> -                      RUNTIME_INFO(perf->i915)->cs_timestamp_frequency_khz);
> +       return div_u64(1000000000 * (2ULL << exponent),
> +                      RUNTIME_INFO(perf->i915)->cs_timestamp_frequency_hz);
>  }
>  
>  /**
> @@ -4359,8 +4359,8 @@ void i915_perf_init(struct drm_i915_private *i915)
>         if (perf->ops.enable_metric_set) {
>                 mutex_init(&perf->lock);
>  
> -               oa_sample_rate_hard_limit = 1000 *
> -                       (RUNTIME_INFO(i915)->cs_timestamp_frequency_khz / 2);
> +               oa_sample_rate_hard_limit =
> +                       RUNTIME_INFO(i915)->cs_timestamp_frequency_hz / 2;
>  
>                 mutex_init(&perf->metrics_lock);
>                 idr_init(&perf->metrics_idr);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index d7fe12734db8..32733535964d 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -135,8 +135,8 @@ void intel_device_info_print_runtime(const struct intel_runtime_info *info,
>         sseu_dump(&info->sseu, p);
>  
>         drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq);
> -       drm_printf(p, "CS timestamp frequency: %u kHz\n",
> -                  info->cs_timestamp_frequency_khz);
> +       drm_printf(p, "CS timestamp frequency: %u Hz\n",
> +                  info->cs_timestamp_frequency_hz);
>  }
>  
>  static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
> @@ -677,12 +677,12 @@ static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv)
>  
>         base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >>
>                      GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1;
> -       base_freq *= 1000;
> +       base_freq *= 1000000;
>  
>         frac_freq = ((ts_override &
>                       GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >>
>                      GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT);
> -       frac_freq = 1000 / (frac_freq + 1);
> +       frac_freq = 1000000 / (frac_freq + 1);
>  
>         return base_freq + frac_freq;
>  }
> @@ -690,8 +690,8 @@ static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv)
>  static u32 gen10_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
>                                         u32 rpm_config_reg)
>  {
> -       u32 f19_2_mhz = 19200;
> -       u32 f24_mhz = 24000;
> +       u32 f19_2_mhz = 19200000;
> +       u32 f24_mhz = 24000000;
>         u32 crystal_clock = (rpm_config_reg &
>                              GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
>                             GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
> @@ -710,10 +710,10 @@ static u32 gen10_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
>  static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
>                                         u32 rpm_config_reg)
>  {
> -       u32 f19_2_mhz = 19200;
> -       u32 f24_mhz = 24000;
> -       u32 f25_mhz = 25000;
> -       u32 f38_4_mhz = 38400;
> +       u32 f19_2_mhz = 19200000;
> +       u32 f24_mhz = 24000000;
> +       u32 f25_mhz = 25000000;
> +       u32 f38_4_mhz = 38400000;
>         u32 crystal_clock = (rpm_config_reg &
>                              GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
>                             GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
> @@ -735,9 +735,9 @@ static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
>  
>  static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
>  {
> -       u32 f12_5_mhz = 12500;
> -       u32 f19_2_mhz = 19200;
> -       u32 f24_mhz = 24000;
> +       u32 f12_5_mhz = 12500000;
> +       u32 f19_2_mhz = 19200000;
> +       u32 f24_mhz = 24000000;
>  
>         if (INTEL_GEN(dev_priv) <= 4) {
>                 /* PRMs say:
> @@ -746,7 +746,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
>                  *      hclks." (through the “Clocking Configuration”
>                  *      (“CLKCFG”) MCHBAR register)
>                  */
> -               return RUNTIME_INFO(dev_priv)->rawclk_freq / 16;
> +               return RUNTIME_INFO(dev_priv)->rawclk_freq * 1000 / 16;
>         } else if (INTEL_GEN(dev_priv) <= 8) {
>                 /* PRMs say:
>                  *
> @@ -1050,11 +1050,11 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>         drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
>  
>         /* Initialize command stream timestamp frequency */
> -       runtime->cs_timestamp_frequency_khz =
> +       runtime->cs_timestamp_frequency_hz =
>                 read_timestamp_frequency(dev_priv);
> -       if (runtime->cs_timestamp_frequency_khz) {
> +       if (runtime->cs_timestamp_frequency_hz) {
>                 runtime->cs_timestamp_period_ns =
> -                       div_u64(1e6, runtime->cs_timestamp_frequency_khz);
> +                       div_u64(1e9, runtime->cs_timestamp_frequency_hz);
>                 drm_dbg(&dev_priv->drm,
>                         "CS timestamp wraparound in %lldms\n",
>                         div_u64(mul_u32_u32(runtime->cs_timestamp_period_ns,
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 1ecb9df2de91..432e9c7c0fe7 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -218,7 +218,7 @@ struct intel_runtime_info {
>  
>         u32 rawclk_freq;
>  
> -       u32 cs_timestamp_frequency_khz;
> +       u32 cs_timestamp_frequency_hz;

As far as I'm aware, there are no plans for GHz crystals.

Counted all the zeros, which are a lot :)

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 2/6] drm/i915: Store CS timestamp frequency in Hz

[Lionel Landwerlin]

On 02/03/2020 16:39, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> kHz isn't accurate enough for storing the CS timestamp
> frequency on some of the platforms. Store the value
> in Hz instead.
>
> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Probably the only patch in this series where I'm qualified to review :)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>


> ---
>   drivers/gpu/drm/i915/i915_debugfs.c        |  6 ++--
>   drivers/gpu/drm/i915/i915_getparam.c       |  2 +-
>   drivers/gpu/drm/i915/i915_perf.c           | 12 ++++----
>   drivers/gpu/drm/i915/intel_device_info.c   | 34 +++++++++++-----------
>   drivers/gpu/drm/i915/intel_device_info.h   |  2 +-
>   drivers/gpu/drm/i915/selftests/i915_perf.c |  4 +--
>   6 files changed, 30 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 8f2525e4ce0f..c0e54c500017 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1790,8 +1790,8 @@ static int i915_engine_info(struct seq_file *m, void *unused)
>   	seq_printf(m, "GT awake? %s [%d]\n",
>   		   yesno(dev_priv->gt.awake),
>   		   atomic_read(&dev_priv->gt.wakeref.count));
> -	seq_printf(m, "CS timestamp frequency: %u kHz\n",
> -		   RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz);
> +	seq_printf(m, "CS timestamp frequency: %u Hz\n",
> +		   RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_hz);
>   
>   	p = drm_seq_file_printer(m);
>   	for_each_uabi_engine(engine, dev_priv)
> @@ -1890,7 +1890,7 @@ static int
>   i915_perf_noa_delay_set(void *data, u64 val)
>   {
>   	struct drm_i915_private *i915 = data;
> -	const u32 clk = RUNTIME_INFO(i915)->cs_timestamp_frequency_khz;
> +	const u32 clk = RUNTIME_INFO(i915)->cs_timestamp_frequency_hz / 1000;
>   
>   	/*
>   	 * This would lead to infinite waits as we're doing timestamp
> diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
> index 54fce81d5724..d042644b9cd2 100644
> --- a/drivers/gpu/drm/i915/i915_getparam.c
> +++ b/drivers/gpu/drm/i915/i915_getparam.c
> @@ -153,7 +153,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
>   			return -ENODEV;
>   		break;
>   	case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
> -		value = 1000 * RUNTIME_INFO(i915)->cs_timestamp_frequency_khz;
> +		value = RUNTIME_INFO(i915)->cs_timestamp_frequency_hz;
>   		break;
>   	case I915_PARAM_MMAP_GTT_COHERENT:
>   		value = INTEL_INFO(i915)->has_coherent_ggtt;
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 716fe6e4e56c..a2f98fb08bf1 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1668,8 +1668,8 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
>   	struct i915_vma *vma;
>   	const u64 delay_ticks = 0xffffffffffffffff -
>   		DIV_ROUND_UP_ULL(atomic64_read(&stream->perf->noa_programming_delay) *
> -				 RUNTIME_INFO(i915)->cs_timestamp_frequency_khz,
> -				 1000000);
> +				 RUNTIME_INFO(i915)->cs_timestamp_frequency_hz,
> +				 1000000000);
>   	const u32 base = stream->engine->mmio_base;
>   #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
>   	u32 *batch, *ts0, *cs, *jump;
> @@ -3466,8 +3466,8 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
>   
>   static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
>   {
> -	return div_u64(1000000 * (2ULL << exponent),
> -		       RUNTIME_INFO(perf->i915)->cs_timestamp_frequency_khz);
> +	return div_u64(1000000000 * (2ULL << exponent),
> +		       RUNTIME_INFO(perf->i915)->cs_timestamp_frequency_hz);
>   }
>   
>   /**
> @@ -4359,8 +4359,8 @@ void i915_perf_init(struct drm_i915_private *i915)
>   	if (perf->ops.enable_metric_set) {
>   		mutex_init(&perf->lock);
>   
> -		oa_sample_rate_hard_limit = 1000 *
> -			(RUNTIME_INFO(i915)->cs_timestamp_frequency_khz / 2);
> +		oa_sample_rate_hard_limit =
> +			RUNTIME_INFO(i915)->cs_timestamp_frequency_hz / 2;
>   
>   		mutex_init(&perf->metrics_lock);
>   		idr_init(&perf->metrics_idr);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index d7fe12734db8..32733535964d 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -135,8 +135,8 @@ void intel_device_info_print_runtime(const struct intel_runtime_info *info,
>   	sseu_dump(&info->sseu, p);
>   
>   	drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq);
> -	drm_printf(p, "CS timestamp frequency: %u kHz\n",
> -		   info->cs_timestamp_frequency_khz);
> +	drm_printf(p, "CS timestamp frequency: %u Hz\n",
> +		   info->cs_timestamp_frequency_hz);
>   }
>   
>   static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
> @@ -677,12 +677,12 @@ static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv)
>   
>   	base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >>
>   		     GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1;
> -	base_freq *= 1000;
> +	base_freq *= 1000000;
>   
>   	frac_freq = ((ts_override &
>   		      GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >>
>   		     GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT);
> -	frac_freq = 1000 / (frac_freq + 1);
> +	frac_freq = 1000000 / (frac_freq + 1);
>   
>   	return base_freq + frac_freq;
>   }
> @@ -690,8 +690,8 @@ static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv)
>   static u32 gen10_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
>   					u32 rpm_config_reg)
>   {
> -	u32 f19_2_mhz = 19200;
> -	u32 f24_mhz = 24000;
> +	u32 f19_2_mhz = 19200000;
> +	u32 f24_mhz = 24000000;
>   	u32 crystal_clock = (rpm_config_reg &
>   			     GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
>   			    GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
> @@ -710,10 +710,10 @@ static u32 gen10_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
>   static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
>   					u32 rpm_config_reg)
>   {
> -	u32 f19_2_mhz = 19200;
> -	u32 f24_mhz = 24000;
> -	u32 f25_mhz = 25000;
> -	u32 f38_4_mhz = 38400;
> +	u32 f19_2_mhz = 19200000;
> +	u32 f24_mhz = 24000000;
> +	u32 f25_mhz = 25000000;
> +	u32 f38_4_mhz = 38400000;
>   	u32 crystal_clock = (rpm_config_reg &
>   			     GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
>   			    GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
> @@ -735,9 +735,9 @@ static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
>   
>   static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
>   {
> -	u32 f12_5_mhz = 12500;
> -	u32 f19_2_mhz = 19200;
> -	u32 f24_mhz = 24000;
> +	u32 f12_5_mhz = 12500000;
> +	u32 f19_2_mhz = 19200000;
> +	u32 f24_mhz = 24000000;
>   
>   	if (INTEL_GEN(dev_priv) <= 4) {
>   		/* PRMs say:
> @@ -746,7 +746,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
>   		 *      hclks." (through the “Clocking Configuration”
>   		 *      (“CLKCFG”) MCHBAR register)
>   		 */
> -		return RUNTIME_INFO(dev_priv)->rawclk_freq / 16;
> +		return RUNTIME_INFO(dev_priv)->rawclk_freq * 1000 / 16;
>   	} else if (INTEL_GEN(dev_priv) <= 8) {
>   		/* PRMs say:
>   		 *
> @@ -1050,11 +1050,11 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>   	drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
>   
>   	/* Initialize command stream timestamp frequency */
> -	runtime->cs_timestamp_frequency_khz =
> +	runtime->cs_timestamp_frequency_hz =
>   		read_timestamp_frequency(dev_priv);
> -	if (runtime->cs_timestamp_frequency_khz) {
> +	if (runtime->cs_timestamp_frequency_hz) {
>   		runtime->cs_timestamp_period_ns =
> -			div_u64(1e6, runtime->cs_timestamp_frequency_khz);
> +			div_u64(1e9, runtime->cs_timestamp_frequency_hz);
>   		drm_dbg(&dev_priv->drm,
>   			"CS timestamp wraparound in %lldms\n",
>   			div_u64(mul_u32_u32(runtime->cs_timestamp_period_ns,
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 1ecb9df2de91..432e9c7c0fe7 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -218,7 +218,7 @@ struct intel_runtime_info {
>   
>   	u32 rawclk_freq;
>   
> -	u32 cs_timestamp_frequency_khz;
> +	u32 cs_timestamp_frequency_hz;
>   	u32 cs_timestamp_period_ns;
>   
>   	/* Media engine access to SFC per instance */
> diff --git a/drivers/gpu/drm/i915/selftests/i915_perf.c b/drivers/gpu/drm/i915/selftests/i915_perf.c
> index d1a1568c47ba..dea0c5dd2739 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_perf.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_perf.c
> @@ -180,8 +180,8 @@ static int live_noa_delay(void *arg)
>   
>   	delay = intel_read_status_page(stream->engine, 0x102);
>   	delay -= intel_read_status_page(stream->engine, 0x100);
> -	delay = div_u64(mul_u32_u32(delay, 1000 * 1000),
> -			RUNTIME_INFO(i915)->cs_timestamp_frequency_khz);
> +	delay = div_u64(mul_u32_u32(delay, 1000000000),
> +			RUNTIME_INFO(i915)->cs_timestamp_frequency_hz);
>   	pr_info("GPU delay: %uns, expected %lluns\n",
>   		delay, expected);
>   


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 3/6] drm/i915: Fix cs_timestamp_frequency_hz for ctg/elk/ilk

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On ilk the UDW of TIMESTAMP increments every 1000 ns,
LDW is mbz. In order to represent cs_timestamp_frequency_hz
for that we'd need 52 bits, but we only have 32 bits.
Even worse most things want to only deak with the low
32 bits of timestamp. So let's just set up cs_timestamp_frequency_hz
as if we only had the UDW.

On ctg/elk 63:20 of TIMESTAMP increments every 1/4 ns, 19:0
are mbz. To make life simpler let's ignore the LDW and set up
cs_timestamp_frequency_hz based on the UDW only (increments
evert 1024 ns).

Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_device_info.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 32733535964d..b756e8fb7682 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -739,7 +739,10 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 	u32 f19_2_mhz = 19200000;
 	u32 f24_mhz = 24000000;
 
-	if (INTEL_GEN(dev_priv) <= 4) {
+	if (INTEL_GEN(dev_priv) < 4)
+		return 0;
+
+	if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
 		/* PRMs say:
 		 *
 		 *     "The value in this register increments once every 16
@@ -747,6 +750,20 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 		 *      (“CLKCFG”) MCHBAR register)
 		 */
 		return RUNTIME_INFO(dev_priv)->rawclk_freq * 1000 / 16;
+	} else if (IS_G4X(dev_priv)) {
+		/*
+		 * 63:20 increments every 1/4 ns
+		 * 19:0 mbz
+		 *
+		 * -> 63:32 increments every 1024 ns
+		 */
+		return 1000000000 / 1024;
+	} else if (IS_GEN(dev_priv, 5)) {
+		/*
+		 * 63:32 increments every 1000 ns
+		 * 31:0 mbz
+		 */
+		return 1000000000 / 1000;
 	} else if (INTEL_GEN(dev_priv) <= 8) {
 		/* PRMs say:
 		 *
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 4/6] drm/i915: Fix cs_timestamp_frequency_hz for cl/bw

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Despite what the spec says the TIMESTAMP register seems to tick
once every hrawclk (confirmed on i965gm and g35).

Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_device_info.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index b756e8fb7682..be88eb41035a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -748,8 +748,10 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 		 *     "The value in this register increments once every 16
 		 *      hclks." (through the “Clocking Configuration”
 		 *      (“CLKCFG”) MCHBAR register)
+		 *
+		 * Testing on actual hardware has shown there is no /16.
 		 */
-		return RUNTIME_INFO(dev_priv)->rawclk_freq * 1000 / 16;
+		return RUNTIME_INFO(dev_priv)->rawclk_freq * 1000;
 	} else if (IS_G4X(dev_priv)) {
 		/*
 		 * 63:20 increments every 1/4 ns
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 5/6] drm/i915: Extract i915_cs_timestamp_{ns_to_ticks, tick_to_ns}()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pull the code to do the CS timestamp ns<->ticks conversion into
helpers and use them all over.

The check in i915_perf_noa_delay_set() seems a bit dubious,
so we switch it to do what I assume it wanted to do all along
(ie. make sure the resulting delay in CS timestamp ticks
doesn't exceed 32bits)?

Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c        |  3 +--
 drivers/gpu/drm/i915/i915_drv.h            | 12 ++++++++++++
 drivers/gpu/drm/i915/i915_perf.c           |  7 ++-----
 drivers/gpu/drm/i915/intel_device_info.c   |  2 +-
 drivers/gpu/drm/i915/selftests/i915_perf.c |  3 +--
 5 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index c0e54c500017..4bfa70b94e8f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1890,13 +1890,12 @@ static int
 i915_perf_noa_delay_set(void *data, u64 val)
 {
 	struct drm_i915_private *i915 = data;
-	const u32 clk = RUNTIME_INFO(i915)->cs_timestamp_frequency_hz / 1000;
 
 	/*
 	 * This would lead to infinite waits as we're doing timestamp
 	 * difference on the CS with only 32bits.
 	 */
-	if (val > mul_u32_u32(U32_MAX, clk))
+	if (i915_cs_timestamp_ns_to_ticks(i915, val) > U32_MAX)
 		return -EINVAL;
 
 	atomic64_set(&i915->perf.noa_programming_delay, val);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1f5dda38e7b4..7640eccdc46c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1955,4 +1955,16 @@ i915_coherent_map_type(struct drm_i915_private *i915)
 	return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
 }
 
+static inline u64 i915_cs_timestamp_ns_to_ticks(struct drm_i915_private *i915, u64 val)
+{
+	return DIV_ROUND_UP_ULL(val * RUNTIME_INFO(i915)->cs_timestamp_frequency_hz,
+				1000000000);
+}
+
+static inline u64 i915_cs_timestamp_ticks_to_ns(struct drm_i915_private *i915, u64 val)
+{
+	return div_u64(val * 1000000000,
+		       RUNTIME_INFO(i915)->cs_timestamp_frequency_hz);
+}
+
 #endif
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index a2f98fb08bf1..f53e2c72ae97 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1667,9 +1667,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
 	struct drm_i915_gem_object *bo;
 	struct i915_vma *vma;
 	const u64 delay_ticks = 0xffffffffffffffff -
-		DIV_ROUND_UP_ULL(atomic64_read(&stream->perf->noa_programming_delay) *
-				 RUNTIME_INFO(i915)->cs_timestamp_frequency_hz,
-				 1000000000);
+		i915_cs_timestamp_ns_to_ticks(i915, atomic64_read(&stream->perf->noa_programming_delay));
 	const u32 base = stream->engine->mmio_base;
 #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
 	u32 *batch, *ts0, *cs, *jump;
@@ -3466,8 +3464,7 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
 
 static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
 {
-	return div_u64(1000000000 * (2ULL << exponent),
-		       RUNTIME_INFO(perf->i915)->cs_timestamp_frequency_hz);
+	return i915_cs_timestamp_ticks_to_ns(perf->i915, 2ULL << exponent);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index be88eb41035a..d97a0e09b6b2 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -1073,7 +1073,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 		read_timestamp_frequency(dev_priv);
 	if (runtime->cs_timestamp_frequency_hz) {
 		runtime->cs_timestamp_period_ns =
-			div_u64(1e9, runtime->cs_timestamp_frequency_hz);
+			i915_cs_timestamp_ticks_to_ns(dev_priv, 1);
 		drm_dbg(&dev_priv->drm,
 			"CS timestamp wraparound in %lldms\n",
 			div_u64(mul_u32_u32(runtime->cs_timestamp_period_ns,
diff --git a/drivers/gpu/drm/i915/selftests/i915_perf.c b/drivers/gpu/drm/i915/selftests/i915_perf.c
index dea0c5dd2739..c6f3374062c5 100644
--- a/drivers/gpu/drm/i915/selftests/i915_perf.c
+++ b/drivers/gpu/drm/i915/selftests/i915_perf.c
@@ -180,8 +180,7 @@ static int live_noa_delay(void *arg)
 
 	delay = intel_read_status_page(stream->engine, 0x102);
 	delay -= intel_read_status_page(stream->engine, 0x100);
-	delay = div_u64(mul_u32_u32(delay, 1000000000),
-			RUNTIME_INFO(i915)->cs_timestamp_frequency_hz);
+	delay = i915_cs_timestamp_ticks_to_ns(i915, delay);
 	pr_info("GPU delay: %uns, expected %lluns\n",
 		delay, expected);
 
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 5/6] drm/i915: Extract i915_cs_timestamp_{ns_to_ticks, tick_to_ns}()

[Chris Wilson]

Quoting Ville Syrjala (2020-03-02 14:39:42)
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Pull the code to do the CS timestamp ns<->ticks conversion into
> helpers and use them all over.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
 
> The check in i915_perf_noa_delay_set() seems a bit dubious,
> so we switch it to do what I assume it wanted to do all along
> (ie. make sure the resulting delay in CS timestamp ticks
> doesn't exceed 32bits)?

Yes. The MI_MATH operates on just 32b of the timestamp, and so wants a
delay in that range.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 6/6] drm/i915/selftests: Make the CS timestamp tests work on gen4-snb (sort of)

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On pre-ivb the CS timestamp register is only present on RCS (despite
what snb bspec claims). Let's test it.

Also on ctg/elk/ilk the usable part of the timestamp is the UDW so
let's read that instead of the LDW. On ctg/elk the 10 msbs of the LDW
do actually work, but we configure cs_timestamp_frequency_hz as if
they didn't so  that we can treat ctg/elk the same as ilk.

TODO: figure out why the results we get aren't reliable. On some
iterations we can get totally wrong (though consistent) values,
on other iterations the values are correct. And somehow changing
the offsets into the hwsp also seems to affect the behaviour.
Manually reading the register always seems fine, so feels like
the problem has something to do with the store rather than the actual
register read.

Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 27 +++++++++++++++++---
 1 file changed, 24 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
index f88e445a1cae..f92542e6b5b8 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
@@ -52,7 +52,10 @@ static int write_timestamp(struct i915_request *rq, int slot)
 	if (INTEL_GEN(rq->i915) >= 8)
 		cmd++;
 	*cs++ = cmd;
-	*cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base));
+	if (IS_GEN(rq->i915, 5) || IS_G4X(rq->i915))
+		*cs++ = i915_mmio_reg_offset(RING_TIMESTAMP_UDW(rq->engine->mmio_base));
+	else
+		*cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base));
 	*cs++ = i915_request_timeline(rq)->hwsp_offset + slot * sizeof(u32);
 	*cs++ = 0;
 
@@ -122,7 +125,8 @@ static int perf_mi_bb_start(void *arg)
 	enum intel_engine_id id;
 	int err = 0;
 
-	if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
+	/* Do we have any CS_TIMESTAMP? */
+	if (INTEL_GEN(gt->i915) < 4)
 		return 0;
 
 	perf_begin(gt);
@@ -132,6 +136,14 @@ static int perf_mi_bb_start(void *arg)
 		u32 cycles[COUNT];
 		int i;
 
+		/*
+		 * Do we have CS_TIMESTAMP for this engine?
+		 * Despite what bspec says SNB does not have this
+		 * for other engines.
+		 */
+		if (INTEL_GEN(gt->i915) < 7 && id != RCS0)
+			continue;
+
 		intel_engine_pm_get(engine);
 
 		batch = create_empty_batch(ce);
@@ -246,7 +258,8 @@ static int perf_mi_noop(void *arg)
 	enum intel_engine_id id;
 	int err = 0;
 
-	if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
+	/* Do we have any CS_TIMESTAMP? */
+	if (INTEL_GEN(gt->i915) < 4)
 		return 0;
 
 	perf_begin(gt);
@@ -256,6 +269,14 @@ static int perf_mi_noop(void *arg)
 		u32 cycles[COUNT];
 		int i;
 
+		/*
+		 * Do we have CS_TIMESTAMP for this engine?
+		 * Despite what bspec says SNB does not have this
+		 * for other engines.
+		 */
+		if (INTEL_GEN(gt->i915) < 7 && id != RCS0)
+			continue;
+
 		intel_engine_pm_get(engine);
 
 		base = create_empty_batch(ce);
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 6/6] drm/i915/selftests: Make the CS timestamp tests work on gen4-snb (sort of)

[Chris Wilson]

Quoting Ville Syrjala (2020-03-02 14:39:43)
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On pre-ivb the CS timestamp register is only present on RCS (despite
> what snb bspec claims). Let's test it.
> 
> Also on ctg/elk/ilk the usable part of the timestamp is the UDW so
> let's read that instead of the LDW. On ctg/elk the 10 msbs of the LDW
> do actually work, but we configure cs_timestamp_frequency_hz as if
> they didn't so  that we can treat ctg/elk the same as ilk.
> 
> TODO: figure out why the results we get aren't reliable. On some
> iterations we can get totally wrong (though consistent) values,
> on other iterations the values are correct. And somehow changing
> the offsets into the hwsp also seems to affect the behaviour.
> Manually reading the register always seems fine, so feels like
> the problem has something to do with the store rather than the actual
> register read.

On i965gm, I get fairly random output from reading the CS_TIMESTAMP.

One step at a time, first let's get the test results for reading
CS_TIMESTAMP vs the updated rawclk and see how well we fare across the
farm. Then we might see if there's a pattern here.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915: Nuke pointless div by 64bit

[Patchwork]

== Series Details ==

Series: series starting with [1/6] drm/i915: Nuke pointless div by 64bit
URL   : https://patchwork.freedesktop.org/series/74145/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
6cf1345486f2 drm/i915: Nuke pointless div by 64bit
03152bdf42be drm/i915: Store CS timestamp frequency in Hz
bf4eb53970e1 drm/i915: Fix cs_timestamp_frequency_hz for ctg/elk/ilk
3a7310b7ff08 drm/i915: Fix cs_timestamp_frequency_hz for cl/bw
13e9499b1424 drm/i915: Extract i915_cs_timestamp_{ns_to_ticks, tick_to_ns}()
-:72: WARNING:LONG_LINE: line over 100 characters
#72: FILE: drivers/gpu/drm/i915/i915_perf.c:1670:
+		i915_cs_timestamp_ns_to_ticks(i915, atomic64_read(&stream->perf->noa_programming_delay));

total: 0 errors, 1 warnings, 0 checks, 66 lines checked
a49c4e236c8f drm/i915/selftests: Make the CS timestamp tests work on gen4-snb (sort of)

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/6] drm/i915: Nuke pointless div by 64bit

[Patchwork]

== Series Details ==

Series: series starting with [1/6] drm/i915: Nuke pointless div by 64bit
URL   : https://patchwork.freedesktop.org/series/74145/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
Error: Cannot open file ./drivers/gpu/drm/i915/intel_csr.c
Error: Cannot open file ./drivers/gpu/drm/i915/intel_csr.c
Error: Cannot open file ./drivers/gpu/drm/i915/intel_csr.c
./drivers/gpu/drm/i915/i915_vma.h:1: warning: 'Virtual Memory Address' not found
./drivers/gpu/drm/i915/i915_gem_gtt.c:1: warning: 'Global GTT views' not found
WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function csr support for dmc ./drivers/gpu/drm/i915/intel_csr.c' failed with return code 1
WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -internal ./drivers/gpu/drm/i915/intel_csr.c' failed with return code 2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Nuke pointless div by 64bit

[Patchwork]

== Series Details ==

Series: series starting with [1/6] drm/i915: Nuke pointless div by 64bit
URL   : https://patchwork.freedesktop.org/series/74145/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8043 -> Patchwork_16780
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/index.html

Known issues
------------

  Here are the changes found in Patchwork_16780 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@gem_contexts:
    - fi-cml-s:           [PASS][1] -> [DMESG-FAIL][2] ([i915#877])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/fi-cml-s/igt@i915_selftest@live@gem_contexts.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/fi-cml-s/igt@i915_selftest@live@gem_contexts.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [PASS][3] -> [FAIL][4] ([fdo#111096] / [i915#323])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@vgem_basic@debugfs:
    - fi-tgl-y:           [PASS][5] -> [DMESG-WARN][6] ([CI#94] / [i915#402])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/fi-tgl-y/igt@vgem_basic@debugfs.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/fi-tgl-y/igt@vgem_basic@debugfs.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@execlists:
    - fi-icl-y:           [DMESG-FAIL][7] ([fdo#108569]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/fi-icl-y/igt@i915_selftest@live@execlists.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/fi-icl-y/igt@i915_selftest@live@execlists.html

  * igt@kms_addfb_basic@bad-pitch-999:
    - fi-tgl-y:           [DMESG-WARN][9] ([CI#94] / [i915#402]) -> [PASS][10] +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/fi-tgl-y/igt@kms_addfb_basic@bad-pitch-999.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/fi-tgl-y/igt@kms_addfb_basic@bad-pitch-999.html

  
#### Warnings ####

  * igt@runner@aborted:
    - fi-kbl-8809g:       [FAIL][11] ([i915#192] / [i915#193] / [i915#194]) -> [FAIL][12] ([i915#1209])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/fi-kbl-8809g/igt@runner@aborted.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/fi-kbl-8809g/igt@runner@aborted.html

  
  [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [i915#1209]: https://gitlab.freedesktop.org/drm/intel/issues/1209
  [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192
  [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193
  [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194
  [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877


Participating hosts (48 -> 38)
------------------------------

  Additional (3): fi-glk-dsi fi-byt-n2820 fi-elk-e7500 
  Missing    (13): fi-ilk-m540 fi-bdw-samus fi-bsw-n3050 fi-hsw-4200u fi-bdw-gvtdvm fi-byt-squawks fi-bsw-cyan fi-ilk-650 fi-kbl-guc fi-ctg-p8600 fi-bsw-kefka fi-blb-e6850 fi-skl-6700k2 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8043 -> Patchwork_16780

  CI-20190529: 20190529
  CI_DRM_8043: 7e5119254441cdf0764418bbf3f43f6547d30a8a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5483: 1707153df224ffb6333c6c660a792b7f334eb3d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16780: a49c4e236c8f13c67eca85aa1e03b4e6adc9f1d4 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

a49c4e236c8f drm/i915/selftests: Make the CS timestamp tests work on gen4-snb (sort of)
13e9499b1424 drm/i915: Extract i915_cs_timestamp_{ns_to_ticks, tick_to_ns}()
3a7310b7ff08 drm/i915: Fix cs_timestamp_frequency_hz for cl/bw
bf4eb53970e1 drm/i915: Fix cs_timestamp_frequency_hz for ctg/elk/ilk
03152bdf42be drm/i915: Store CS timestamp frequency in Hz
6cf1345486f2 drm/i915: Nuke pointless div by 64bit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/6] drm/i915: Nuke pointless div by 64bit

[Patchwork]

== Series Details ==

Series: series starting with [1/6] drm/i915: Nuke pointless div by 64bit
URL   : https://patchwork.freedesktop.org/series/74145/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8043_full -> Patchwork_16780_full
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with Patchwork_16780_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_16780_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_16780_full:

### IGT changes ###

#### Warnings ####

  * igt@kms_color_chamelium@pipe-c-ctm-green-to-red:
    - shard-tglb:         [SKIP][1] ([fdo#111827]) -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-tglb8/igt@kms_color_chamelium@pipe-c-ctm-green-to-red.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-tglb6/igt@kms_color_chamelium@pipe-c-ctm-green-to-red.html

  
Known issues
------------

  Here are the changes found in Patchwork_16780_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@vcs1-nonpriv:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#112080]) +10 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-iclb7/igt@gem_ctx_isolation@vcs1-nonpriv.html

  * igt@gem_ctx_persistence@close-replace-race:
    - shard-kbl:          [PASS][5] -> [INCOMPLETE][6] ([fdo#103665] / [i915#1291])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-kbl1/igt@gem_ctx_persistence@close-replace-race.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-kbl1/igt@gem_ctx_persistence@close-replace-race.html

  * igt@gem_ctx_persistence@legacy-engines-mixed-process@default:
    - shard-glk:          [PASS][7] -> [FAIL][8] ([i915#679])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-glk9/igt@gem_ctx_persistence@legacy-engines-mixed-process@default.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-glk6/igt@gem_ctx_persistence@legacy-engines-mixed-process@default.html

  * igt@gem_ctx_persistence@legacy-engines-mixed-process@render:
    - shard-glk:          [PASS][9] -> [INCOMPLETE][10] ([i915#1239] / [i915#58] / [k.org#198133])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-glk9/igt@gem_ctx_persistence@legacy-engines-mixed-process@render.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-glk6/igt@gem_ctx_persistence@legacy-engines-mixed-process@render.html

  * igt@gem_exec_schedule@implicit-read-write-bsd1:
    - shard-iclb:         [PASS][11] -> [SKIP][12] ([fdo#109276] / [i915#677])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-iclb2/igt@gem_exec_schedule@implicit-read-write-bsd1.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-iclb5/igt@gem_exec_schedule@implicit-read-write-bsd1.html

  * igt@gem_exec_schedule@preempt-queue-bsd:
    - shard-iclb:         [PASS][13] -> [SKIP][14] ([fdo#112146]) +5 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-iclb6/igt@gem_exec_schedule@preempt-queue-bsd.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-kbl:          [PASS][15] -> [FAIL][16] ([i915#644])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-kbl3/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-kbl6/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@gem_userptr_blits@sync-unmap-after-close:
    - shard-skl:          [PASS][17] -> [DMESG-WARN][18] ([fdo#111870] / [i915#836])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-skl10/igt@gem_userptr_blits@sync-unmap-after-close.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-skl7/igt@gem_userptr_blits@sync-unmap-after-close.html

  * igt@i915_suspend@fence-restore-untiled:
    - shard-kbl:          [PASS][19] -> [INCOMPLETE][20] ([fdo#103665])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-kbl3/igt@i915_suspend@fence-restore-untiled.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-kbl6/igt@i915_suspend@fence-restore-untiled.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-kbl:          [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +2 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-c-cursor-dpms:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([i915#54])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-skl5/igt@kms_cursor_crc@pipe-c-cursor-dpms.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-skl5/igt@kms_cursor_crc@pipe-c-cursor-dpms.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-glk:          [PASS][25] -> [FAIL][26] ([i915#72])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-glk2/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-glk2/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-skl:          [PASS][27] -> [INCOMPLETE][28] ([i915#221])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-skl2/igt@kms_flip@flip-vs-suspend-interruptible.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-apl:          [PASS][29] -> [DMESG-WARN][30] ([i915#180]) +4 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-apl6/igt@kms_hdr@bpc-switch-suspend.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-apl1/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][31] -> [FAIL][32] ([fdo#108145] / [i915#265]) +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [PASS][33] -> [SKIP][34] ([fdo#109642] / [fdo#111068]) +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-iclb4/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_cursor_plane_move:
    - shard-iclb:         [PASS][35] -> [SKIP][36] ([fdo#109441]) +2 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-iclb7/igt@kms_psr@psr2_cursor_plane_move.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][37] -> [FAIL][38] ([i915#31])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-apl7/igt@kms_setmode@basic.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-apl4/igt@kms_setmode@basic.html

  * igt@prime_busy@after-bsd2:
    - shard-iclb:         [PASS][39] -> [SKIP][40] ([fdo#109276]) +17 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-iclb2/igt@prime_busy@after-bsd2.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-iclb3/igt@prime_busy@after-bsd2.html

  
#### Possible fixes ####

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [SKIP][41] ([fdo#110841]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-iclb6/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [SKIP][43] ([fdo#110854]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-iclb8/igt@gem_exec_balancer@smoke.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-iclb2/igt@gem_exec_balancer@smoke.html

  * igt@gem_exec_schedule@implicit-both-bsd2:
    - shard-iclb:         [SKIP][45] ([fdo#109276] / [i915#677]) -> [PASS][46] +1 similar issue
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-iclb3/igt@gem_exec_schedule@implicit-both-bsd2.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-iclb2/igt@gem_exec_schedule@implicit-both-bsd2.html

  * igt@gem_exec_schedule@reorder-wide-bsd:
    - shard-iclb:         [SKIP][47] ([fdo#112146]) -> [PASS][48] +4 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-iclb7/igt@gem_exec_schedule@reorder-wide-bsd.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-glk:          [DMESG-WARN][49] ([i915#716]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-glk2/igt@gen9_exec_parse@allowed-all.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-glk1/igt@gen9_exec_parse@allowed-all.html

  * igt@i915_pm_rps@waitboost:
    - shard-iclb:         [FAIL][51] ([i915#413]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-iclb6/igt@i915_pm_rps@waitboost.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-iclb8/igt@i915_pm_rps@waitboost.html

  * igt@i915_suspend@forcewake:
    - shard-kbl:          [DMESG-WARN][53] ([i915#180]) -> [PASS][54] +4 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-kbl3/igt@i915_suspend@forcewake.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-kbl7/igt@i915_suspend@forcewake.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible:
    - shard-skl:          [FAIL][55] ([i915#34]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-skl9/igt@kms_flip@plain-flip-fb-recreate-interruptible.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [FAIL][57] ([i915#1188]) -> [PASS][58] +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-skl3/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-apl:          [DMESG-WARN][59] ([i915#180]) -> [PASS][60] +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [FAIL][61] ([fdo#108145]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-glk:          [FAIL][63] ([i915#899]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-glk4/igt@kms_plane_lowres@pipe-a-tiling-x.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-glk8/igt@kms_plane_lowres@pipe-a-tiling-x.html

  * igt@kms_psr@no_drrs:
    - shard-iclb:         [FAIL][65] ([i915#173]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-iclb1/igt@kms_psr@no_drrs.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-iclb4/igt@kms_psr@no_drrs.html

  * igt@kms_psr@psr2_primary_blt:
    - shard-iclb:         [SKIP][67] ([fdo#109441]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-iclb3/igt@kms_psr@psr2_primary_blt.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-iclb2/igt@kms_psr@psr2_primary_blt.html

  * igt@perf_pmu@busy-vcs1:
    - shard-iclb:         [SKIP][69] ([fdo#112080]) -> [PASS][70] +15 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-iclb3/igt@perf_pmu@busy-vcs1.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-iclb1/igt@perf_pmu@busy-vcs1.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [SKIP][71] ([fdo#109276]) -> [PASS][72] +17 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-iclb6/igt@prime_busy@hang-bsd2.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-iclb4/igt@prime_busy@hang-bsd2.html

  * igt@prime_vgem@sync-bsd:
    - shard-skl:          [INCOMPLETE][73] ([i915#409]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-skl9/igt@prime_vgem@sync-bsd.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-skl10/igt@prime_vgem@sync-bsd.html

  
#### Warnings ####

  * igt@i915_pm_rpm@cursor-dpms:
    - shard-snb:          [INCOMPLETE][75] ([i915#82]) -> [SKIP][76] ([fdo#109271])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-snb2/igt@i915_pm_rpm@cursor-dpms.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-snb6/igt@i915_pm_rpm@cursor-dpms.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-iclb:         [FAIL][77] -> [SKIP][78] ([fdo#110725] / [fdo#111614])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-iclb2/igt@kms_big_fb@linear-16bpp-rotate-90.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-iclb8/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@runner@aborted:
    - shard-glk:          [FAIL][79] ([k.org#202321]) -> [FAIL][80] ([i915#1356] / [k.org#202321])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-glk2/igt@runner@aborted.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-glk5/igt@runner@aborted.html
    - shard-skl:          [FAIL][81] ([i915#69]) -> ([FAIL][82], [FAIL][83]) ([fdo#111870] / [i915#1356] / [i915#69])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8043/shard-skl9/igt@runner@aborted.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-skl7/igt@runner@aborted.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/shard-skl5/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
  [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
  [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1239]: https://gitlab.freedesktop.org/drm/intel/issues/1239
  [i915#1291]: https://gitlab.freedesktop.org/drm/intel/issues/1291
  [i915#1356]: https://gitlab.freedesktop.org/drm/intel/issues/1356
  [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#221]: https://gitlab.freedesktop.org/drm/intel/issues/221
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
  [i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
  [i915#409]: https://gitlab.freedesktop.org/drm/intel/issues/409
  [i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
  [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
  [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
  [i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679
  [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
  [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
  [i915#836]: https://gitlab.freedesktop.org/drm/intel/issues/836
  [i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
  [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8043 -> Patchwork_16780

  CI-20190529: 20190529
  CI_DRM_8043: 7e5119254441cdf0764418bbf3f43f6547d30a8a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5483: 1707153df224ffb6333c6c660a792b7f334eb3d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16780: a49c4e236c8f13c67eca85aa1e03b4e6adc9f1d4 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16780/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/6] drm/i915: Nuke pointless div by 64bit

[Chris Wilson]

Quoting Ville Syrjala (2020-03-02 14:39:38)
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Bunch of places use a 64bit divisor needlessly. Switch
> to 32bit divisor.
> 
> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_perf.c | 11 +++++------
>  1 file changed, 5 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 2334c45f1d08..716fe6e4e56c 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1667,10 +1667,9 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
>         struct drm_i915_gem_object *bo;
>         struct i915_vma *vma;
>         const u64 delay_ticks = 0xffffffffffffffff -
> -               DIV64_U64_ROUND_UP(
> -                       atomic64_read(&stream->perf->noa_programming_delay) *
> -                       RUNTIME_INFO(i915)->cs_timestamp_frequency_khz,
> -                       1000000ull);
> +               DIV_ROUND_UP_ULL(atomic64_read(&stream->perf->noa_programming_delay) *
> +                                RUNTIME_INFO(i915)->cs_timestamp_frequency_khz,
> +                                1000000);
>         const u32 base = stream->engine->mmio_base;
>  #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
>         u32 *batch, *ts0, *cs, *jump;
> @@ -3467,8 +3466,8 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
>  
>  static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
>  {
> -       return div64_u64(1000000000ULL * (2ULL << exponent),
> -                        1000ULL * RUNTIME_INFO(perf->i915)->cs_timestamp_frequency_khz);
> +       return div_u64(1000000 * (2ULL << exponent),
> +                      RUNTIME_INFO(perf->i915)->cs_timestamp_frequency_khz);
>  }

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx