From: Akash Asthana <akashast@codeaurora.org> To: gregkh@linuxfoundation.org, agross@kernel.org, bjorn.andersson@linaro.org, wsa@the-dreams.de, broonie@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, georgi.djakov@linaro.org Cc: linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, swboyd@chromium.org, mgautam@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, mka@chromium.org, dianders@chromium.org, evgreen@chromium.org, Akash Asthana <akashast@codeaurora.org> Subject: [PATCH V3 6/8] tty: serial: qcom_geni_serial: Add interconnect support Date: Tue, 31 Mar 2020 16:39:34 +0530 [thread overview] Message-ID: <1585652976-17481-7-git-send-email-akashast@codeaurora.org> (raw) In-Reply-To: <1585652976-17481-1-git-send-email-akashast@codeaurora.org> Get the interconnect paths for Uart based Serial Engine device and vote according to the baud rate requirement of the driver. Signed-off-by: Akash Asthana <akashast@codeaurora.org> --- Changes in V2: - As per Bjorn's comment, removed se == NULL check from geni_serial_icc_get - As per Bjorn's comment, removed code to set se->icc_path* to NULL in failure - As per Bjorn's comment, introduced and using devm_of_icc_get API for getting path handle - As per Matthias comment, added error handling for icc_set_bw call Changes in V3: - As per Matthias comment, use common library APIs defined in geni-se driver for ICC functionality. drivers/tty/serial/qcom_geni_serial.c | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 8c5d97c..2befe72 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -965,6 +965,14 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, ser_clk_cfg = SER_CLK_EN; ser_clk_cfg |= clk_div << CLK_DIV_SHFT; + /* + * Bump up BW vote on CPU path as driver supports FIFO mode only. + * Assume peak_bw as twice of avg_bw. + */ + port->se.from_cpu.avg_bw = Bps_to_icc(baud); + port->se.from_cpu.peak_bw = Bps_to_icc(2 * baud); + geni_icc_vote_on(&port->se); + /* parity */ tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); @@ -1202,11 +1210,14 @@ static void qcom_geni_serial_pm(struct uart_port *uport, if (old_state == UART_PM_STATE_UNDEFINED) old_state = UART_PM_STATE_OFF; - if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) + if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) { + geni_icc_vote_on(&port->se); geni_se_resources_on(&port->se); - else if (new_state == UART_PM_STATE_OFF && - old_state == UART_PM_STATE_ON) + } else if (new_state == UART_PM_STATE_OFF && + old_state == UART_PM_STATE_ON) { geni_se_resources_off(&port->se); + geni_icc_vote_off(&port->se); + } } static const struct uart_ops qcom_geni_console_pops = { @@ -1304,6 +1315,17 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) return -ENOMEM; } + ret = geni_icc_get(&port->se, "qup-core", "qup-config", NULL); + if (ret) + return ret; + /* Set the bus quota to a reasonable value */ + port->se.to_core.avg_bw = console ? GENI_DEFAULT_BW : + Bps_to_icc(CORE_2X_50_MHZ); + port->se.to_core.peak_bw = console ? GENI_DEFAULT_BW : + Bps_to_icc(CORE_2X_100_MHZ); + port->se.from_cpu.avg_bw = GENI_DEFAULT_BW; + port->se.from_cpu.peak_bw = GENI_DEFAULT_BW; + port->name = devm_kasprintf(uport->dev, GFP_KERNEL, "qcom_geni_serial_%s%d", uart_console(uport) ? "console" : "uart", uport->line); -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
WARNING: multiple messages have this Message-ID (diff)
From: Akash Asthana <akashast-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> To: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org, agross-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org, broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, georgi.djakov-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org Cc: linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, swboyd-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, mgautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-serial-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, mka-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, evgreen-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, Akash Asthana <akashast-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> Subject: [PATCH V3 6/8] tty: serial: qcom_geni_serial: Add interconnect support Date: Tue, 31 Mar 2020 16:39:34 +0530 [thread overview] Message-ID: <1585652976-17481-7-git-send-email-akashast@codeaurora.org> (raw) In-Reply-To: <1585652976-17481-1-git-send-email-akashast-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> Get the interconnect paths for Uart based Serial Engine device and vote according to the baud rate requirement of the driver. Signed-off-by: Akash Asthana <akashast-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> --- Changes in V2: - As per Bjorn's comment, removed se == NULL check from geni_serial_icc_get - As per Bjorn's comment, removed code to set se->icc_path* to NULL in failure - As per Bjorn's comment, introduced and using devm_of_icc_get API for getting path handle - As per Matthias comment, added error handling for icc_set_bw call Changes in V3: - As per Matthias comment, use common library APIs defined in geni-se driver for ICC functionality. drivers/tty/serial/qcom_geni_serial.c | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 8c5d97c..2befe72 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -965,6 +965,14 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, ser_clk_cfg = SER_CLK_EN; ser_clk_cfg |= clk_div << CLK_DIV_SHFT; + /* + * Bump up BW vote on CPU path as driver supports FIFO mode only. + * Assume peak_bw as twice of avg_bw. + */ + port->se.from_cpu.avg_bw = Bps_to_icc(baud); + port->se.from_cpu.peak_bw = Bps_to_icc(2 * baud); + geni_icc_vote_on(&port->se); + /* parity */ tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); @@ -1202,11 +1210,14 @@ static void qcom_geni_serial_pm(struct uart_port *uport, if (old_state == UART_PM_STATE_UNDEFINED) old_state = UART_PM_STATE_OFF; - if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) + if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) { + geni_icc_vote_on(&port->se); geni_se_resources_on(&port->se); - else if (new_state == UART_PM_STATE_OFF && - old_state == UART_PM_STATE_ON) + } else if (new_state == UART_PM_STATE_OFF && + old_state == UART_PM_STATE_ON) { geni_se_resources_off(&port->se); + geni_icc_vote_off(&port->se); + } } static const struct uart_ops qcom_geni_console_pops = { @@ -1304,6 +1315,17 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) return -ENOMEM; } + ret = geni_icc_get(&port->se, "qup-core", "qup-config", NULL); + if (ret) + return ret; + /* Set the bus quota to a reasonable value */ + port->se.to_core.avg_bw = console ? GENI_DEFAULT_BW : + Bps_to_icc(CORE_2X_50_MHZ); + port->se.to_core.peak_bw = console ? GENI_DEFAULT_BW : + Bps_to_icc(CORE_2X_100_MHZ); + port->se.from_cpu.avg_bw = GENI_DEFAULT_BW; + port->se.from_cpu.peak_bw = GENI_DEFAULT_BW; + port->name = devm_kasprintf(uport->dev, GFP_KERNEL, "qcom_geni_serial_%s%d", uart_console(uport) ? "console" : "uart", uport->line); -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
next prev parent reply other threads:[~2020-03-31 11:12 UTC|newest] Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-03-31 11:09 [PATCH V3 0/8] Add interconnect support to QSPI and QUP drivers Akash Asthana 2020-03-31 11:09 ` [PATCH V3 1/8] interconnect: Add devm_of_icc_get() as exported API for users Akash Asthana 2020-03-31 11:09 ` Akash Asthana 2020-03-31 11:09 ` [PATCH V3 2/8] soc: qcom: geni: Support for ICC voting Akash Asthana 2020-03-31 17:52 ` Matthias Kaehlcke 2020-03-31 17:52 ` Matthias Kaehlcke 2020-04-02 13:46 ` Akash Asthana 2020-04-02 13:46 ` Akash Asthana 2020-03-31 23:32 ` Bjorn Andersson 2020-03-31 23:32 ` Bjorn Andersson 2020-04-01 16:26 ` Evan Green 2020-04-01 16:26 ` Evan Green 2020-04-07 6:46 ` Akash Asthana 2020-04-07 9:58 ` Georgi Djakov 2020-04-08 11:13 ` Akash Asthana 2020-04-07 6:45 ` Akash Asthana 2020-04-07 22:07 ` Bjorn Andersson 2020-03-31 11:09 ` [PATCH V3 3/8] soc: qcom-geni-se: Add interconnect support to fix earlycon crash Akash Asthana 2020-03-31 18:24 ` Matthias Kaehlcke 2020-03-31 18:24 ` Matthias Kaehlcke 2020-04-01 19:46 ` Matthias Kaehlcke 2020-04-01 19:46 ` Matthias Kaehlcke 2020-04-07 6:52 ` Akash Asthana 2020-04-07 11:34 ` Akash Asthana 2020-04-07 17:26 ` Matthias Kaehlcke 2020-04-08 11:38 ` Akash Asthana 2020-04-08 17:09 ` Matthias Kaehlcke 2020-03-31 11:09 ` [PATCH V3 4/8] i2c: i2c-qcom-geni: Add interconnect support Akash Asthana 2020-03-31 18:49 ` Matthias Kaehlcke 2020-03-31 18:49 ` Matthias Kaehlcke 2020-04-07 7:04 ` Akash Asthana 2020-03-31 11:09 ` [PATCH V3 5/8] spi: spi-geni-qcom: " Akash Asthana 2020-03-31 19:02 ` Matthias Kaehlcke 2020-03-31 19:02 ` Matthias Kaehlcke 2020-04-07 7:11 ` Akash Asthana 2020-03-31 11:09 ` Akash Asthana [this message] 2020-03-31 11:09 ` [PATCH V3 6/8] tty: serial: qcom_geni_serial: " Akash Asthana 2020-03-31 19:39 ` Matthias Kaehlcke 2020-03-31 19:39 ` Matthias Kaehlcke 2020-04-07 9:19 ` Akash Asthana 2020-04-07 9:40 ` Akash Asthana 2020-03-31 11:09 ` [PATCH V3 7/8] spi: spi-qcom-qspi: " Akash Asthana 2020-03-31 11:23 ` Mark Brown 2020-03-31 11:23 ` Mark Brown 2020-04-07 9:54 ` Akash Asthana 2020-04-07 10:55 ` Mark Brown 2020-04-08 12:17 ` Akash Asthana 2020-04-09 13:17 ` Georgi Djakov 2020-04-09 13:20 ` Mark Brown 2020-04-15 10:34 ` Georgi Djakov [not found] ` <eca0e6a7-effe-022c-e90e-c0672991251d@codeaurora.org> 2020-04-15 10:54 ` Georgi Djakov 2020-03-31 19:45 ` Matthias Kaehlcke 2020-03-31 19:45 ` Matthias Kaehlcke 2020-03-31 11:09 ` [PATCH V3 8/8] arm64: dts: sc7180: Add interconnect for QUP and QSPI Akash Asthana 2020-03-31 11:09 ` Akash Asthana
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1585652976-17481-7-git-send-email-akashast@codeaurora.org \ --to=akashast@codeaurora.org \ --cc=agross@kernel.org \ --cc=bjorn.andersson@linaro.org \ --cc=broonie@kernel.org \ --cc=devicetree@vger.kernel.org \ --cc=dianders@chromium.org \ --cc=evgreen@chromium.org \ --cc=georgi.djakov@linaro.org \ --cc=gregkh@linuxfoundation.org \ --cc=linux-arm-msm@vger.kernel.org \ --cc=linux-i2c@vger.kernel.org \ --cc=linux-serial@vger.kernel.org \ --cc=linux-spi@vger.kernel.org \ --cc=mark.rutland@arm.com \ --cc=mgautam@codeaurora.org \ --cc=mka@chromium.org \ --cc=robh+dt@kernel.org \ --cc=swboyd@chromium.org \ --cc=wsa@the-dreams.de \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.