From: Matthias Kaehlcke <mka@chromium.org> To: Akash Asthana <akashast@codeaurora.org> Cc: gregkh@linuxfoundation.org, agross@kernel.org, bjorn.andersson@linaro.org, wsa@the-dreams.de, broonie@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, georgi.djakov@linaro.org, linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, swboyd@chromium.org, mgautam@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, dianders@chromium.org, evgreen@chromium.org Subject: Re: [PATCH V3 5/8] spi: spi-geni-qcom: Add interconnect support Date: Tue, 31 Mar 2020 12:02:49 -0700 [thread overview] Message-ID: <20200331190249.GJ199755@google.com> (raw) In-Reply-To: <1585652976-17481-6-git-send-email-akashast@codeaurora.org> On Tue, Mar 31, 2020 at 04:39:33PM +0530, Akash Asthana wrote: > Get the interconnect paths for SPI based Serial Engine device > and vote according to the current bus speed of the driver. > > Signed-off-by: Akash Asthana <akashast@codeaurora.org> > --- > Changes in V2: > - As per Bjorn's comment, removed se == NULL check from geni_spi_icc_get > - As per Bjorn's comment, removed code to set se->icc_path* to NULL in failure > - As per Bjorn's comment, introduced and using devm_of_icc_get API for getting > path handle > - As per Matthias comment, added error handling for icc_set_bw call > > Changes in V3: > - As per Matthias's comment, use helper ICC function from geni-se driver. > > drivers/spi/spi-geni-qcom.c | 31 ++++++++++++++++++++++++++++++- > 1 file changed, 30 insertions(+), 1 deletion(-) > > diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c > index c397242..f1dae2d 100644 > --- a/drivers/spi/spi-geni-qcom.c > +++ b/drivers/spi/spi-geni-qcom.c > @@ -234,6 +234,16 @@ static int setup_fifo_params(struct spi_device *spi_slv, > return ret; > } > > + /* > + * Set BW quota for CPU as driver supports FIFO mode only. > + * Assume peak bw as twice of avg bw. > + */ > + se->from_cpu.avg_bw = Bps_to_icc(mas->cur_speed_hz); > + se->from_cpu.peak_bw = Bps_to_icc(2 * mas->cur_speed_hz); > + ret = geni_icc_vote_on(se); > + if (ret) > + return ret; > + > clk_sel = idx & CLK_SEL_MSK; > m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN; > spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word); > @@ -578,6 +588,15 @@ static int spi_geni_probe(struct platform_device *pdev) > spin_lock_init(&mas->lock); > pm_runtime_enable(dev); > > + ret = geni_icc_get(&mas->se, "qup-core", "qup-config", NULL); > + if (ret) > + goto spi_geni_probe_runtime_disable; This fails without providing any hints why, besides the error code. It might be worth to add error logging to geni_icc_get(). > + /* Set the bus quota to a reasonable value for register access */ > + mas->se.to_core.avg_bw = Bps_to_icc(CORE_2X_50_MHZ); > + mas->se.to_core.peak_bw = Bps_to_icc(CORE_2X_100_MHZ); > + mas->se.from_cpu.avg_bw = GENI_DEFAULT_BW; > + mas->se.from_cpu.peak_bw = GENI_DEFAULT_BW; > + > ret = spi_geni_init(mas); > if (ret) > goto spi_geni_probe_runtime_disable; > @@ -616,14 +635,24 @@ static int __maybe_unused spi_geni_runtime_suspend(struct device *dev) > { > struct spi_master *spi = dev_get_drvdata(dev); > struct spi_geni_master *mas = spi_master_get_devdata(spi); > + int ret; > + > + ret = geni_se_resources_off(&mas->se); > + if (ret) > + return ret; > > - return geni_se_resources_off(&mas->se); > + return geni_icc_vote_off(&mas->se); > } > > static int __maybe_unused spi_geni_runtime_resume(struct device *dev) > { > struct spi_master *spi = dev_get_drvdata(dev); > struct spi_geni_master *mas = spi_master_get_devdata(spi); > + int ret; > + > + ret = geni_icc_vote_on(&mas->se); > + if (ret) > + return ret; > > return geni_se_resources_on(&mas->se); > } Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
WARNING: multiple messages have this Message-ID (diff)
From: Matthias Kaehlcke <mka-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> To: Akash Asthana <akashast-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> Cc: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org, agross-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org, broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, georgi.djakov-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, swboyd-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, mgautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-serial-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, evgreen-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org Subject: Re: [PATCH V3 5/8] spi: spi-geni-qcom: Add interconnect support Date: Tue, 31 Mar 2020 12:02:49 -0700 [thread overview] Message-ID: <20200331190249.GJ199755@google.com> (raw) In-Reply-To: <1585652976-17481-6-git-send-email-akashast-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> On Tue, Mar 31, 2020 at 04:39:33PM +0530, Akash Asthana wrote: > Get the interconnect paths for SPI based Serial Engine device > and vote according to the current bus speed of the driver. > > Signed-off-by: Akash Asthana <akashast-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> > --- > Changes in V2: > - As per Bjorn's comment, removed se == NULL check from geni_spi_icc_get > - As per Bjorn's comment, removed code to set se->icc_path* to NULL in failure > - As per Bjorn's comment, introduced and using devm_of_icc_get API for getting > path handle > - As per Matthias comment, added error handling for icc_set_bw call > > Changes in V3: > - As per Matthias's comment, use helper ICC function from geni-se driver. > > drivers/spi/spi-geni-qcom.c | 31 ++++++++++++++++++++++++++++++- > 1 file changed, 30 insertions(+), 1 deletion(-) > > diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c > index c397242..f1dae2d 100644 > --- a/drivers/spi/spi-geni-qcom.c > +++ b/drivers/spi/spi-geni-qcom.c > @@ -234,6 +234,16 @@ static int setup_fifo_params(struct spi_device *spi_slv, > return ret; > } > > + /* > + * Set BW quota for CPU as driver supports FIFO mode only. > + * Assume peak bw as twice of avg bw. > + */ > + se->from_cpu.avg_bw = Bps_to_icc(mas->cur_speed_hz); > + se->from_cpu.peak_bw = Bps_to_icc(2 * mas->cur_speed_hz); > + ret = geni_icc_vote_on(se); > + if (ret) > + return ret; > + > clk_sel = idx & CLK_SEL_MSK; > m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN; > spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word); > @@ -578,6 +588,15 @@ static int spi_geni_probe(struct platform_device *pdev) > spin_lock_init(&mas->lock); > pm_runtime_enable(dev); > > + ret = geni_icc_get(&mas->se, "qup-core", "qup-config", NULL); > + if (ret) > + goto spi_geni_probe_runtime_disable; This fails without providing any hints why, besides the error code. It might be worth to add error logging to geni_icc_get(). > + /* Set the bus quota to a reasonable value for register access */ > + mas->se.to_core.avg_bw = Bps_to_icc(CORE_2X_50_MHZ); > + mas->se.to_core.peak_bw = Bps_to_icc(CORE_2X_100_MHZ); > + mas->se.from_cpu.avg_bw = GENI_DEFAULT_BW; > + mas->se.from_cpu.peak_bw = GENI_DEFAULT_BW; > + > ret = spi_geni_init(mas); > if (ret) > goto spi_geni_probe_runtime_disable; > @@ -616,14 +635,24 @@ static int __maybe_unused spi_geni_runtime_suspend(struct device *dev) > { > struct spi_master *spi = dev_get_drvdata(dev); > struct spi_geni_master *mas = spi_master_get_devdata(spi); > + int ret; > + > + ret = geni_se_resources_off(&mas->se); > + if (ret) > + return ret; > > - return geni_se_resources_off(&mas->se); > + return geni_icc_vote_off(&mas->se); > } > > static int __maybe_unused spi_geni_runtime_resume(struct device *dev) > { > struct spi_master *spi = dev_get_drvdata(dev); > struct spi_geni_master *mas = spi_master_get_devdata(spi); > + int ret; > + > + ret = geni_icc_vote_on(&mas->se); > + if (ret) > + return ret; > > return geni_se_resources_on(&mas->se); > } Reviewed-by: Matthias Kaehlcke <mka-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
next prev parent reply other threads:[~2020-03-31 19:02 UTC|newest] Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-03-31 11:09 [PATCH V3 0/8] Add interconnect support to QSPI and QUP drivers Akash Asthana 2020-03-31 11:09 ` [PATCH V3 1/8] interconnect: Add devm_of_icc_get() as exported API for users Akash Asthana 2020-03-31 11:09 ` Akash Asthana 2020-03-31 11:09 ` [PATCH V3 2/8] soc: qcom: geni: Support for ICC voting Akash Asthana 2020-03-31 17:52 ` Matthias Kaehlcke 2020-03-31 17:52 ` Matthias Kaehlcke 2020-04-02 13:46 ` Akash Asthana 2020-04-02 13:46 ` Akash Asthana 2020-03-31 23:32 ` Bjorn Andersson 2020-03-31 23:32 ` Bjorn Andersson 2020-04-01 16:26 ` Evan Green 2020-04-01 16:26 ` Evan Green 2020-04-07 6:46 ` Akash Asthana 2020-04-07 9:58 ` Georgi Djakov 2020-04-08 11:13 ` Akash Asthana 2020-04-07 6:45 ` Akash Asthana 2020-04-07 22:07 ` Bjorn Andersson 2020-03-31 11:09 ` [PATCH V3 3/8] soc: qcom-geni-se: Add interconnect support to fix earlycon crash Akash Asthana 2020-03-31 18:24 ` Matthias Kaehlcke 2020-03-31 18:24 ` Matthias Kaehlcke 2020-04-01 19:46 ` Matthias Kaehlcke 2020-04-01 19:46 ` Matthias Kaehlcke 2020-04-07 6:52 ` Akash Asthana 2020-04-07 11:34 ` Akash Asthana 2020-04-07 17:26 ` Matthias Kaehlcke 2020-04-08 11:38 ` Akash Asthana 2020-04-08 17:09 ` Matthias Kaehlcke 2020-03-31 11:09 ` [PATCH V3 4/8] i2c: i2c-qcom-geni: Add interconnect support Akash Asthana 2020-03-31 18:49 ` Matthias Kaehlcke 2020-03-31 18:49 ` Matthias Kaehlcke 2020-04-07 7:04 ` Akash Asthana 2020-03-31 11:09 ` [PATCH V3 5/8] spi: spi-geni-qcom: " Akash Asthana 2020-03-31 19:02 ` Matthias Kaehlcke [this message] 2020-03-31 19:02 ` Matthias Kaehlcke 2020-04-07 7:11 ` Akash Asthana 2020-03-31 11:09 ` [PATCH V3 6/8] tty: serial: qcom_geni_serial: " Akash Asthana 2020-03-31 11:09 ` Akash Asthana 2020-03-31 19:39 ` Matthias Kaehlcke 2020-03-31 19:39 ` Matthias Kaehlcke 2020-04-07 9:19 ` Akash Asthana 2020-04-07 9:40 ` Akash Asthana 2020-03-31 11:09 ` [PATCH V3 7/8] spi: spi-qcom-qspi: " Akash Asthana 2020-03-31 11:23 ` Mark Brown 2020-03-31 11:23 ` Mark Brown 2020-04-07 9:54 ` Akash Asthana 2020-04-07 10:55 ` Mark Brown 2020-04-08 12:17 ` Akash Asthana 2020-04-09 13:17 ` Georgi Djakov 2020-04-09 13:20 ` Mark Brown 2020-04-15 10:34 ` Georgi Djakov [not found] ` <eca0e6a7-effe-022c-e90e-c0672991251d@codeaurora.org> 2020-04-15 10:54 ` Georgi Djakov 2020-03-31 19:45 ` Matthias Kaehlcke 2020-03-31 19:45 ` Matthias Kaehlcke 2020-03-31 11:09 ` [PATCH V3 8/8] arm64: dts: sc7180: Add interconnect for QUP and QSPI Akash Asthana 2020-03-31 11:09 ` Akash Asthana
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