* [PATCH v5 01/12] net: cadence_gem: Fix debug statements
2020-05-12 14:54 [PATCH v5 00/12] Cadence GEM Fixes Sai Pavan Boddu
@ 2020-05-12 14:54 ` Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 02/12] net: cadence_gem: Fix the queue address update during wrap around Sai Pavan Boddu
` (11 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Sai Pavan Boddu @ 2020-05-12 14:54 UTC (permalink / raw)
To: Edgar E. Iglesias, Alistair Francis, Peter Maydell, Jason Wang,
Markus Armbruster, Philippe Mathieu-Daudé,
Tong Ho, Ramon Fried
Cc: qemu-arm, qemu-devel
Enabling debug breaks the build, Fix them and make debug statements
always compilable. Fix few statements to use sized integer casting.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
hw/net/cadence_gem.c | 27 +++++++++++++--------------
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 22a0b1b..5476c62 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -35,14 +35,13 @@
#include "sysemu/dma.h"
#include "net/checksum.h"
-#ifdef CADENCE_GEM_ERR_DEBUG
-#define DB_PRINT(...) do { \
- fprintf(stderr, ": %s: ", __func__); \
- fprintf(stderr, ## __VA_ARGS__); \
- } while (0)
-#else
- #define DB_PRINT(...)
-#endif
+#define CADENCE_GEM_ERR_DEBUG 0
+#define DB_PRINT(...) do {\
+ if (CADENCE_GEM_ERR_DEBUG) { \
+ qemu_log(": %s: ", __func__); \
+ qemu_log(__VA_ARGS__); \
+ } \
+} while (0)
#define GEM_NWCTRL (0x00000000/4) /* Network Control reg */
#define GEM_NWCFG (0x00000004/4) /* Network Config reg */
@@ -979,7 +978,7 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
size += 4;
}
- DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size);
+ DB_PRINT("config bufsize: %u packet size: %zd\n", rxbufsize, size);
/* Find which queue we are targeting */
q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize);
@@ -992,9 +991,9 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
return -1;
}
- DB_PRINT("copy %u bytes to 0x%" PRIx64 "\n",
- MIN(bytes_to_copy, rxbufsize),
- rx_desc_get_buffer(s, s->rx_desc[q]));
+ DB_PRINT("copy %" PRIu32 " bytes to 0x%" PRIx64 "\n",
+ MIN(bytes_to_copy, rxbufsize),
+ rx_desc_get_buffer(s, s->rx_desc[q]));
/* Copy packet data to emulated DMA buffer */
address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) +
@@ -1160,8 +1159,8 @@ static void gem_transmit(CadenceGEMState *s)
*/
if ((tx_desc_get_buffer(s, desc) == 0) ||
(tx_desc_get_length(desc) == 0)) {
- DB_PRINT("Invalid TX descriptor @ 0x%x\n",
- (unsigned)packet_desc_addr);
+ DB_PRINT("Invalid TX descriptor @ 0x%" HWADDR_PRIx "\n",
+ packet_desc_addr);
break;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 02/12] net: cadence_gem: Fix the queue address update during wrap around
2020-05-12 14:54 [PATCH v5 00/12] Cadence GEM Fixes Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 01/12] net: cadence_gem: Fix debug statements Sai Pavan Boddu
@ 2020-05-12 14:54 ` Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 03/12] net: cadence_gem: Fix irq update w.r.t queue Sai Pavan Boddu
` (10 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Sai Pavan Boddu @ 2020-05-12 14:54 UTC (permalink / raw)
To: Edgar E. Iglesias, Alistair Francis, Peter Maydell, Jason Wang,
Markus Armbruster, Philippe Mathieu-Daudé,
Tong Ho, Ramon Fried
Cc: qemu-arm, qemu-devel
During wrap around and reset, queues are pointing to initial base
address of queue 0, irrespective of what queue we are dealing with.
Fix it by assigning proper base address every time.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
hw/net/cadence_gem.c | 37 +++++++++++++++++++++++++++++++++----
1 file changed, 33 insertions(+), 4 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 5476c62..c3536ce 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -845,6 +845,35 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
return 0;
}
+static uint32_t gem_get_queue_base_addr(CadenceGEMState *s, bool tx, int q)
+{
+ uint32_t base_addr = 0;
+
+ switch (q) {
+ case 0:
+ base_addr = s->regs[tx ? GEM_TXQBASE : GEM_RXQBASE];
+ break;
+ case 1 ... (MAX_PRIORITY_QUEUES - 1):
+ base_addr = s->regs[(tx ? GEM_TRANSMIT_Q1_PTR :
+ GEM_RECEIVE_Q1_PTR) + q - 1];
+ break;
+ default:
+ g_assert_not_reached();
+ };
+
+ return base_addr;
+}
+
+static inline uint32_t gem_get_tx_queue_base_addr(CadenceGEMState *s, int q)
+{
+ return gem_get_queue_base_addr(s, true, q);
+}
+
+static inline uint32_t gem_get_rx_queue_base_addr(CadenceGEMState *s, int q)
+{
+ return gem_get_queue_base_addr(s, false, q);
+}
+
static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q)
{
hwaddr desc_addr = 0;
@@ -1043,7 +1072,7 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
/* Next descriptor */
if (rx_desc_get_wrap(s->rx_desc[q])) {
DB_PRINT("wrapping RX descriptor list\n");
- s->rx_desc_addr[q] = s->regs[GEM_RXQBASE];
+ s->rx_desc_addr[q] = gem_get_rx_queue_base_addr(s, q);
} else {
DB_PRINT("incrementing RX descriptor list\n");
s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true);
@@ -1199,7 +1228,7 @@ static void gem_transmit(CadenceGEMState *s)
sizeof(desc_first));
/* Advance the hardware current descriptor past this packet */
if (tx_desc_get_wrap(desc)) {
- s->tx_desc_addr[q] = s->regs[GEM_TXQBASE];
+ s->tx_desc_addr[q] = gem_get_tx_queue_base_addr(s, q);
} else {
s->tx_desc_addr[q] = packet_desc_addr +
4 * gem_get_desc_len(s, false);
@@ -1251,7 +1280,7 @@ static void gem_transmit(CadenceGEMState *s)
} else {
packet_desc_addr = 0;
}
- packet_desc_addr |= s->regs[GEM_TXQBASE];
+ packet_desc_addr |= gem_get_tx_queue_base_addr(s, q);
} else {
packet_desc_addr += 4 * gem_get_desc_len(s, false);
}
@@ -1457,7 +1486,7 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
if (!(val & GEM_NWCTRL_TXENA)) {
/* Reset to start of Q when transmit disabled. */
for (i = 0; i < s->num_priority_queues; i++) {
- s->tx_desc_addr[i] = s->regs[GEM_TXQBASE];
+ s->tx_desc_addr[i] = gem_get_tx_queue_base_addr(s, i);
}
}
if (gem_can_receive(qemu_get_queue(s->nic))) {
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 03/12] net: cadence_gem: Fix irq update w.r.t queue
2020-05-12 14:54 [PATCH v5 00/12] Cadence GEM Fixes Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 01/12] net: cadence_gem: Fix debug statements Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 02/12] net: cadence_gem: Fix the queue address update during wrap around Sai Pavan Boddu
@ 2020-05-12 14:54 ` Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 04/12] net: cadence_gem: Define access permission for interrupt registers Sai Pavan Boddu
` (9 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Sai Pavan Boddu @ 2020-05-12 14:54 UTC (permalink / raw)
To: Edgar E. Iglesias, Alistair Francis, Peter Maydell, Jason Wang,
Markus Armbruster, Philippe Mathieu-Daudé,
Tong Ho, Ramon Fried
Cc: qemu-arm, qemu-devel
Set irq's specific to a queue, present implementation is setting q1 irq
based on q0 status.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
hw/net/cadence_gem.c | 25 +++----------------------
1 file changed, 3 insertions(+), 22 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index c3536ce..76c11a1 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -554,29 +554,10 @@ static void gem_update_int_status(CadenceGEMState *s)
{
int i;
- if (!s->regs[GEM_ISR]) {
- /* ISR isn't set, clear all the interrupts */
- for (i = 0; i < s->num_priority_queues; ++i) {
- qemu_set_irq(s->irq[i], 0);
- }
- return;
- }
+ qemu_set_irq(s->irq[0], !!s->regs[GEM_ISR]);
- /* If we get here we know s->regs[GEM_ISR] is set, so we don't need to
- * check it again.
- */
- if (s->num_priority_queues == 1) {
- /* No priority queues, just trigger the interrupt */
- DB_PRINT("asserting int.\n");
- qemu_set_irq(s->irq[0], 1);
- return;
- }
-
- for (i = 0; i < s->num_priority_queues; ++i) {
- if (s->regs[GEM_INT_Q1_STATUS + i]) {
- DB_PRINT("asserting int. (q=%d)\n", i);
- qemu_set_irq(s->irq[i], 1);
- }
+ for (i = 1; i < s->num_priority_queues; ++i) {
+ qemu_set_irq(s->irq[i], !!s->regs[GEM_INT_Q1_STATUS + i - 1]);
}
}
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 04/12] net: cadence_gem: Define access permission for interrupt registers
2020-05-12 14:54 [PATCH v5 00/12] Cadence GEM Fixes Sai Pavan Boddu
` (2 preceding siblings ...)
2020-05-12 14:54 ` [PATCH v5 03/12] net: cadence_gem: Fix irq update w.r.t queue Sai Pavan Boddu
@ 2020-05-12 14:54 ` Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 05/12] net: cadence_gem: Set ISR according to queue in use Sai Pavan Boddu
` (8 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Sai Pavan Boddu @ 2020-05-12 14:54 UTC (permalink / raw)
To: Edgar E. Iglesias, Alistair Francis, Peter Maydell, Jason Wang,
Markus Armbruster, Philippe Mathieu-Daudé,
Tong Ho, Ramon Fried
Cc: qemu-arm, qemu-devel
Q1 to Q7 ISR's are clear-on-read, IER/IDR registers
are write-only, mask reg are read-only.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
hw/net/cadence_gem.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 76c11a1..40bfa5b 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -458,6 +458,7 @@ static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
*/
static void gem_init_register_masks(CadenceGEMState *s)
{
+ unsigned int i;
/* Mask of register bits which are read only */
memset(&s->regs_ro[0], 0, sizeof(s->regs_ro));
s->regs_ro[GEM_NWCTRL] = 0xFFF80000;
@@ -470,10 +471,19 @@ static void gem_init_register_masks(CadenceGEMState *s)
s->regs_ro[GEM_ISR] = 0xFFFFFFFF;
s->regs_ro[GEM_IMR] = 0xFFFFFFFF;
s->regs_ro[GEM_MODID] = 0xFFFFFFFF;
+ for (i = 0; i < s->num_priority_queues; i++) {
+ s->regs_ro[GEM_INT_Q1_STATUS + i] = 0xFFFFFFFF;
+ s->regs_ro[GEM_INT_Q1_ENABLE + i] = 0xFFFFF319;
+ s->regs_ro[GEM_INT_Q1_DISABLE + i] = 0xFFFFF319;
+ s->regs_ro[GEM_INT_Q1_MASK + i] = 0xFFFFFFFF;
+ }
/* Mask of register bits which are clear on read */
memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc));
s->regs_rtc[GEM_ISR] = 0xFFFFFFFF;
+ for (i = 0; i < s->num_priority_queues; i++) {
+ s->regs_rtc[GEM_INT_Q1_STATUS + i] = 0x00000CE6;
+ }
/* Mask of register bits which are write 1 to clear */
memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c));
@@ -485,6 +495,10 @@ static void gem_init_register_masks(CadenceGEMState *s)
s->regs_wo[GEM_NWCTRL] = 0x00073E60;
s->regs_wo[GEM_IER] = 0x07FFFFFF;
s->regs_wo[GEM_IDR] = 0x07FFFFFF;
+ for (i = 0; i < s->num_priority_queues; i++) {
+ s->regs_wo[GEM_INT_Q1_ENABLE + i] = 0x00000CE6;
+ s->regs_wo[GEM_INT_Q1_DISABLE + i] = 0x00000CE6;
+ }
}
/*
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 05/12] net: cadence_gem: Set ISR according to queue in use
2020-05-12 14:54 [PATCH v5 00/12] Cadence GEM Fixes Sai Pavan Boddu
` (3 preceding siblings ...)
2020-05-12 14:54 ` [PATCH v5 04/12] net: cadence_gem: Define access permission for interrupt registers Sai Pavan Boddu
@ 2020-05-12 14:54 ` Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 06/12] net: cadence_gem: Move tx/rx packet buffert to CadenceGEMState Sai Pavan Boddu
` (7 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Sai Pavan Boddu @ 2020-05-12 14:54 UTC (permalink / raw)
To: Edgar E. Iglesias, Alistair Francis, Peter Maydell, Jason Wang,
Markus Armbruster, Philippe Mathieu-Daudé,
Tong Ho, Ramon Fried
Cc: qemu-arm, qemu-devel
Set ISR according to queue in use, added interrupt support for
all queues.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
hw/net/cadence_gem.c | 27 +++++++++++++++++----------
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 40bfa5b..d3f7166 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -451,6 +451,16 @@ static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx)
/* The broadcast MAC address: 0xFFFFFFFFFFFF */
static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
+static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag)
+{
+ if (q == 0) {
+ s->regs[GEM_ISR] |= flag & ~(s->regs[GEM_IMR]);
+ } else {
+ s->regs[GEM_INT_Q1_STATUS + q - 1] |= flag &
+ ~(s->regs[GEM_INT_Q1_MASK + q - 1]);
+ }
+}
+
/*
* gem_init_register_masks:
* One time initialization.
@@ -906,7 +916,7 @@ static void gem_get_rx_desc(CadenceGEMState *s, int q)
if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr);
s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
- s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]);
+ gem_set_isr(s, q, GEM_INT_RXUSED);
/* Handle interrupt consequences */
gem_update_int_status(s);
}
@@ -1080,7 +1090,7 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
gem_receive_updatestats(s, buf, size);
s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD;
- s->regs[GEM_ISR] |= GEM_INT_RXCMPL & ~(s->regs[GEM_IMR]);
+ gem_set_isr(s, q, GEM_INT_RXCMPL);
/* Handle interrupt consequences */
gem_update_int_status(s);
@@ -1231,13 +1241,7 @@ static void gem_transmit(CadenceGEMState *s)
DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]);
s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
- s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]);
-
- /* Update queue interrupt status */
- if (s->num_priority_queues > 1) {
- s->regs[GEM_INT_Q1_STATUS + q] |=
- GEM_INT_TXCMPL & ~(s->regs[GEM_INT_Q1_MASK + q]);
- }
+ gem_set_isr(s, q, GEM_INT_TXCMPL);
/* Handle interrupt consequences */
gem_update_int_status(s);
@@ -1287,7 +1291,10 @@ static void gem_transmit(CadenceGEMState *s)
if (tx_desc_get_used(desc)) {
s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED;
- s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]);
+ /* IRQ TXUSED is defined only for queue 0 */
+ if (q == 0) {
+ gem_set_isr(s, 0, GEM_INT_TXUSED);
+ }
gem_update_int_status(s);
}
}
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 06/12] net: cadence_gem: Move tx/rx packet buffert to CadenceGEMState
2020-05-12 14:54 [PATCH v5 00/12] Cadence GEM Fixes Sai Pavan Boddu
` (4 preceding siblings ...)
2020-05-12 14:54 ` [PATCH v5 05/12] net: cadence_gem: Set ISR according to queue in use Sai Pavan Boddu
@ 2020-05-12 14:54 ` Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 07/12] net: cadence_gem: Fix up code style Sai Pavan Boddu
` (6 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Sai Pavan Boddu @ 2020-05-12 14:54 UTC (permalink / raw)
To: Edgar E. Iglesias, Alistair Francis, Peter Maydell, Jason Wang,
Markus Armbruster, Philippe Mathieu-Daudé,
Tong Ho, Ramon Fried
Cc: qemu-arm, qemu-devel
Moving this buffers to CadenceGEMState, as their size will be increased
more when JUMBO frames support is added.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
hw/net/cadence_gem.c | 38 +++++++++++++++++---------------------
include/hw/net/cadence_gem.h | 4 ++++
2 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index d3f7166..11e36d0 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -928,17 +928,14 @@ static void gem_get_rx_desc(CadenceGEMState *s, int q)
*/
static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
{
- CadenceGEMState *s;
+ CadenceGEMState *s = qemu_get_nic_opaque(nc);
unsigned rxbufsize, bytes_to_copy;
unsigned rxbuf_offset;
- uint8_t rxbuf[2048];
uint8_t *rxbuf_ptr;
bool first_desc = true;
int maf;
int q = 0;
- s = qemu_get_nic_opaque(nc);
-
/* Is this destination MAC address "for us" ? */
maf = gem_mac_address_filter(s, buf);
if (maf == GEM_RX_REJECT) {
@@ -994,19 +991,19 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
} else {
unsigned crc_val;
- if (size > sizeof(rxbuf) - sizeof(crc_val)) {
- size = sizeof(rxbuf) - sizeof(crc_val);
+ if (size > MAX_FRAME_SIZE - sizeof(crc_val)) {
+ size = MAX_FRAME_SIZE - sizeof(crc_val);
}
bytes_to_copy = size;
/* The application wants the FCS field, which QEMU does not provide.
* We must try and calculate one.
*/
- memcpy(rxbuf, buf, size);
- memset(rxbuf + size, 0, sizeof(rxbuf) - size);
- rxbuf_ptr = rxbuf;
- crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60)));
- memcpy(rxbuf + size, &crc_val, sizeof(crc_val));
+ memcpy(s->rx_packet, buf, size);
+ memset(s->rx_packet + size, 0, MAX_FRAME_SIZE - size);
+ rxbuf_ptr = s->rx_packet;
+ crc_val = cpu_to_le32(crc32(0, s->rx_packet, MAX(size, 60)));
+ memcpy(s->rx_packet + size, &crc_val, sizeof(crc_val));
bytes_to_copy += 4;
size += 4;
@@ -1152,7 +1149,6 @@ static void gem_transmit(CadenceGEMState *s)
{
uint32_t desc[DESC_MAX_NUM_WORDS];
hwaddr packet_desc_addr;
- uint8_t tx_packet[2048];
uint8_t *p;
unsigned total_bytes;
int q = 0;
@@ -1168,7 +1164,7 @@ static void gem_transmit(CadenceGEMState *s)
* Packets scattered across multiple descriptors are gathered to this
* one contiguous buffer first.
*/
- p = tx_packet;
+ p = s->tx_packet;
total_bytes = 0;
for (q = s->num_priority_queues - 1; q >= 0; q--) {
@@ -1198,12 +1194,12 @@ static void gem_transmit(CadenceGEMState *s)
break;
}
- if (tx_desc_get_length(desc) > sizeof(tx_packet) -
- (p - tx_packet)) {
+ if (tx_desc_get_length(desc) > MAX_FRAME_SIZE -
+ (p - s->tx_packet)) {
DB_PRINT("TX descriptor @ 0x%" HWADDR_PRIx \
" too large: size 0x%x space 0x%zx\n",
packet_desc_addr, tx_desc_get_length(desc),
- sizeof(tx_packet) - (p - tx_packet));
+ MAX_FRAME_SIZE - (p - s->tx_packet));
break;
}
@@ -1248,24 +1244,24 @@ static void gem_transmit(CadenceGEMState *s)
/* Is checksum offload enabled? */
if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) {
- net_checksum_calculate(tx_packet, total_bytes);
+ net_checksum_calculate(s->tx_packet, total_bytes);
}
/* Update MAC statistics */
- gem_transmit_updatestats(s, tx_packet, total_bytes);
+ gem_transmit_updatestats(s, s->tx_packet, total_bytes);
/* Send the packet somewhere */
if (s->phy_loop || (s->regs[GEM_NWCTRL] &
GEM_NWCTRL_LOCALLOOP)) {
- gem_receive(qemu_get_queue(s->nic), tx_packet,
+ gem_receive(qemu_get_queue(s->nic), s->tx_packet,
total_bytes);
} else {
- qemu_send_packet(qemu_get_queue(s->nic), tx_packet,
+ qemu_send_packet(qemu_get_queue(s->nic), s->tx_packet,
total_bytes);
}
/* Prepare for next packet */
- p = tx_packet;
+ p = s->tx_packet;
total_bytes = 0;
}
diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
index 5c83036..eddac70 100644
--- a/include/hw/net/cadence_gem.h
+++ b/include/hw/net/cadence_gem.h
@@ -40,6 +40,8 @@
#define MAX_TYPE1_SCREENERS 16
#define MAX_TYPE2_SCREENERS 16
+#define MAX_FRAME_SIZE 2048
+
typedef struct CadenceGEMState {
/*< private >*/
SysBusDevice parent_obj;
@@ -80,6 +82,8 @@ typedef struct CadenceGEMState {
uint8_t can_rx_state; /* Debug only */
+ uint8_t tx_packet[MAX_FRAME_SIZE];
+ uint8_t rx_packet[MAX_FRAME_SIZE];
uint32_t rx_desc[MAX_PRIORITY_QUEUES][DESC_MAX_NUM_WORDS];
bool sar_active[4];
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 07/12] net: cadence_gem: Fix up code style
2020-05-12 14:54 [PATCH v5 00/12] Cadence GEM Fixes Sai Pavan Boddu
` (5 preceding siblings ...)
2020-05-12 14:54 ` [PATCH v5 06/12] net: cadence_gem: Move tx/rx packet buffert to CadenceGEMState Sai Pavan Boddu
@ 2020-05-12 14:54 ` Sai Pavan Boddu
2020-05-12 15:19 ` Edgar E. Iglesias
2020-05-12 14:54 ` [PATCH v5 08/12] net: cadence_gem: Add support for jumbo frames Sai Pavan Boddu
` (5 subsequent siblings)
12 siblings, 1 reply; 17+ messages in thread
From: Sai Pavan Boddu @ 2020-05-12 14:54 UTC (permalink / raw)
To: Edgar E. Iglesias, Alistair Francis, Peter Maydell, Jason Wang,
Markus Armbruster, Philippe Mathieu-Daudé,
Tong Ho, Ramon Fried
Cc: qemu-arm, qemu-devel
Fix the code style for register definitions.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
---
hw/net/cadence_gem.c | 204 ++++++++++++++++++++++++++-------------------------
1 file changed, 103 insertions(+), 101 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 11e36d0..f6ff27c 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -43,110 +43,112 @@
} \
} while (0)
-#define GEM_NWCTRL (0x00000000/4) /* Network Control reg */
-#define GEM_NWCFG (0x00000004/4) /* Network Config reg */
-#define GEM_NWSTATUS (0x00000008/4) /* Network Status reg */
-#define GEM_USERIO (0x0000000C/4) /* User IO reg */
-#define GEM_DMACFG (0x00000010/4) /* DMA Control reg */
-#define GEM_TXSTATUS (0x00000014/4) /* TX Status reg */
-#define GEM_RXQBASE (0x00000018/4) /* RX Q Base address reg */
-#define GEM_TXQBASE (0x0000001C/4) /* TX Q Base address reg */
-#define GEM_RXSTATUS (0x00000020/4) /* RX Status reg */
-#define GEM_ISR (0x00000024/4) /* Interrupt Status reg */
-#define GEM_IER (0x00000028/4) /* Interrupt Enable reg */
-#define GEM_IDR (0x0000002C/4) /* Interrupt Disable reg */
-#define GEM_IMR (0x00000030/4) /* Interrupt Mask reg */
-#define GEM_PHYMNTNC (0x00000034/4) /* Phy Maintenance reg */
-#define GEM_RXPAUSE (0x00000038/4) /* RX Pause Time reg */
-#define GEM_TXPAUSE (0x0000003C/4) /* TX Pause Time reg */
-#define GEM_TXPARTIALSF (0x00000040/4) /* TX Partial Store and Forward */
-#define GEM_RXPARTIALSF (0x00000044/4) /* RX Partial Store and Forward */
-#define GEM_HASHLO (0x00000080/4) /* Hash Low address reg */
-#define GEM_HASHHI (0x00000084/4) /* Hash High address reg */
-#define GEM_SPADDR1LO (0x00000088/4) /* Specific addr 1 low reg */
-#define GEM_SPADDR1HI (0x0000008C/4) /* Specific addr 1 high reg */
-#define GEM_SPADDR2LO (0x00000090/4) /* Specific addr 2 low reg */
-#define GEM_SPADDR2HI (0x00000094/4) /* Specific addr 2 high reg */
-#define GEM_SPADDR3LO (0x00000098/4) /* Specific addr 3 low reg */
-#define GEM_SPADDR3HI (0x0000009C/4) /* Specific addr 3 high reg */
-#define GEM_SPADDR4LO (0x000000A0/4) /* Specific addr 4 low reg */
-#define GEM_SPADDR4HI (0x000000A4/4) /* Specific addr 4 high reg */
-#define GEM_TIDMATCH1 (0x000000A8/4) /* Type ID1 Match reg */
-#define GEM_TIDMATCH2 (0x000000AC/4) /* Type ID2 Match reg */
-#define GEM_TIDMATCH3 (0x000000B0/4) /* Type ID3 Match reg */
-#define GEM_TIDMATCH4 (0x000000B4/4) /* Type ID4 Match reg */
-#define GEM_WOLAN (0x000000B8/4) /* Wake on LAN reg */
-#define GEM_IPGSTRETCH (0x000000BC/4) /* IPG Stretch reg */
-#define GEM_SVLAN (0x000000C0/4) /* Stacked VLAN reg */
-#define GEM_MODID (0x000000FC/4) /* Module ID reg */
-#define GEM_OCTTXLO (0x00000100/4) /* Octects transmitted Low reg */
-#define GEM_OCTTXHI (0x00000104/4) /* Octects transmitted High reg */
-#define GEM_TXCNT (0x00000108/4) /* Error-free Frames transmitted */
-#define GEM_TXBCNT (0x0000010C/4) /* Error-free Broadcast Frames */
-#define GEM_TXMCNT (0x00000110/4) /* Error-free Multicast Frame */
-#define GEM_TXPAUSECNT (0x00000114/4) /* Pause Frames Transmitted */
-#define GEM_TX64CNT (0x00000118/4) /* Error-free 64 TX */
-#define GEM_TX65CNT (0x0000011C/4) /* Error-free 65-127 TX */
-#define GEM_TX128CNT (0x00000120/4) /* Error-free 128-255 TX */
-#define GEM_TX256CNT (0x00000124/4) /* Error-free 256-511 */
-#define GEM_TX512CNT (0x00000128/4) /* Error-free 512-1023 TX */
-#define GEM_TX1024CNT (0x0000012C/4) /* Error-free 1024-1518 TX */
-#define GEM_TX1519CNT (0x00000130/4) /* Error-free larger than 1519 TX */
-#define GEM_TXURUNCNT (0x00000134/4) /* TX under run error counter */
-#define GEM_SINGLECOLLCNT (0x00000138/4) /* Single Collision Frames */
-#define GEM_MULTCOLLCNT (0x0000013C/4) /* Multiple Collision Frames */
-#define GEM_EXCESSCOLLCNT (0x00000140/4) /* Excessive Collision Frames */
-#define GEM_LATECOLLCNT (0x00000144/4) /* Late Collision Frames */
-#define GEM_DEFERTXCNT (0x00000148/4) /* Deferred Transmission Frames */
-#define GEM_CSENSECNT (0x0000014C/4) /* Carrier Sense Error Counter */
-#define GEM_OCTRXLO (0x00000150/4) /* Octects Received register Low */
-#define GEM_OCTRXHI (0x00000154/4) /* Octects Received register High */
-#define GEM_RXCNT (0x00000158/4) /* Error-free Frames Received */
-#define GEM_RXBROADCNT (0x0000015C/4) /* Error-free Broadcast Frames RX */
-#define GEM_RXMULTICNT (0x00000160/4) /* Error-free Multicast Frames RX */
-#define GEM_RXPAUSECNT (0x00000164/4) /* Pause Frames Received Counter */
-#define GEM_RX64CNT (0x00000168/4) /* Error-free 64 byte Frames RX */
-#define GEM_RX65CNT (0x0000016C/4) /* Error-free 65-127B Frames RX */
-#define GEM_RX128CNT (0x00000170/4) /* Error-free 128-255B Frames RX */
-#define GEM_RX256CNT (0x00000174/4) /* Error-free 256-512B Frames RX */
-#define GEM_RX512CNT (0x00000178/4) /* Error-free 512-1023B Frames RX */
-#define GEM_RX1024CNT (0x0000017C/4) /* Error-free 1024-1518B Frames RX */
-#define GEM_RX1519CNT (0x00000180/4) /* Error-free 1519-max Frames RX */
-#define GEM_RXUNDERCNT (0x00000184/4) /* Undersize Frames Received */
-#define GEM_RXOVERCNT (0x00000188/4) /* Oversize Frames Received */
-#define GEM_RXJABCNT (0x0000018C/4) /* Jabbers Received Counter */
-#define GEM_RXFCSCNT (0x00000190/4) /* Frame Check seq. Error Counter */
-#define GEM_RXLENERRCNT (0x00000194/4) /* Length Field Error Counter */
-#define GEM_RXSYMERRCNT (0x00000198/4) /* Symbol Error Counter */
-#define GEM_RXALIGNERRCNT (0x0000019C/4) /* Alignment Error Counter */
-#define GEM_RXRSCERRCNT (0x000001A0/4) /* Receive Resource Error Counter */
-#define GEM_RXORUNCNT (0x000001A4/4) /* Receive Overrun Counter */
-#define GEM_RXIPCSERRCNT (0x000001A8/4) /* IP header Checksum Error Counter */
-#define GEM_RXTCPCCNT (0x000001AC/4) /* TCP Checksum Error Counter */
-#define GEM_RXUDPCCNT (0x000001B0/4) /* UDP Checksum Error Counter */
-
-#define GEM_1588S (0x000001D0/4) /* 1588 Timer Seconds */
-#define GEM_1588NS (0x000001D4/4) /* 1588 Timer Nanoseconds */
-#define GEM_1588ADJ (0x000001D8/4) /* 1588 Timer Adjust */
-#define GEM_1588INC (0x000001DC/4) /* 1588 Timer Increment */
-#define GEM_PTPETXS (0x000001E0/4) /* PTP Event Frame Transmitted (s) */
-#define GEM_PTPETXNS (0x000001E4/4) /* PTP Event Frame Transmitted (ns) */
-#define GEM_PTPERXS (0x000001E8/4) /* PTP Event Frame Received (s) */
-#define GEM_PTPERXNS (0x000001EC/4) /* PTP Event Frame Received (ns) */
-#define GEM_PTPPTXS (0x000001E0/4) /* PTP Peer Frame Transmitted (s) */
-#define GEM_PTPPTXNS (0x000001E4/4) /* PTP Peer Frame Transmitted (ns) */
-#define GEM_PTPPRXS (0x000001E8/4) /* PTP Peer Frame Received (s) */
-#define GEM_PTPPRXNS (0x000001EC/4) /* PTP Peer Frame Received (ns) */
+#define GEM_NWCTRL (0x00000000 / 4) /* Network Control reg */
+#define GEM_NWCFG (0x00000004 / 4) /* Network Config reg */
+#define GEM_NWSTATUS (0x00000008 / 4) /* Network Status reg */
+#define GEM_USERIO (0x0000000C / 4) /* User IO reg */
+#define GEM_DMACFG (0x00000010 / 4) /* DMA Control reg */
+#define GEM_TXSTATUS (0x00000014 / 4) /* TX Status reg */
+#define GEM_RXQBASE (0x00000018 / 4) /* RX Q Base address reg */
+#define GEM_TXQBASE (0x0000001C / 4) /* TX Q Base address reg */
+#define GEM_RXSTATUS (0x00000020 / 4) /* RX Status reg */
+#define GEM_ISR (0x00000024 / 4) /* Interrupt Status reg */
+#define GEM_IER (0x00000028 / 4) /* Interrupt Enable reg */
+#define GEM_IDR (0x0000002C / 4) /* Interrupt Disable reg */
+#define GEM_IMR (0x00000030 / 4) /* Interrupt Mask reg */
+#define GEM_PHYMNTNC (0x00000034 / 4) /* Phy Maintenance reg */
+#define GEM_RXPAUSE (0x00000038 / 4) /* RX Pause Time reg */
+#define GEM_TXPAUSE (0x0000003C / 4) /* TX Pause Time reg */
+#define GEM_TXPARTIALSF (0x00000040 / 4) /* TX Partial Store and Forward */
+#define GEM_RXPARTIALSF (0x00000044 / 4) /* RX Partial Store and Forward */
+#define GEM_HASHLO (0x00000080 / 4) /* Hash Low address reg */
+#define GEM_HASHHI (0x00000084 / 4) /* Hash High address reg */
+#define GEM_SPADDR1LO (0x00000088 / 4) /* Specific addr 1 low reg */
+#define GEM_SPADDR1HI (0x0000008C / 4) /* Specific addr 1 high reg */
+#define GEM_SPADDR2LO (0x00000090 / 4) /* Specific addr 2 low reg */
+#define GEM_SPADDR2HI (0x00000094 / 4) /* Specific addr 2 high reg */
+#define GEM_SPADDR3LO (0x00000098 / 4) /* Specific addr 3 low reg */
+#define GEM_SPADDR3HI (0x0000009C / 4) /* Specific addr 3 high reg */
+#define GEM_SPADDR4LO (0x000000A0 / 4) /* Specific addr 4 low reg */
+#define GEM_SPADDR4HI (0x000000A4 / 4) /* Specific addr 4 high reg */
+#define GEM_TIDMATCH1 (0x000000A8 / 4) /* Type ID1 Match reg */
+#define GEM_TIDMATCH2 (0x000000AC / 4) /* Type ID2 Match reg */
+#define GEM_TIDMATCH3 (0x000000B0 / 4) /* Type ID3 Match reg */
+#define GEM_TIDMATCH4 (0x000000B4 / 4) /* Type ID4 Match reg */
+#define GEM_WOLAN (0x000000B8 / 4) /* Wake on LAN reg */
+#define GEM_IPGSTRETCH (0x000000BC / 4) /* IPG Stretch reg */
+#define GEM_SVLAN (0x000000C0 / 4) /* Stacked VLAN reg */
+#define GEM_MODID (0x000000FC / 4) /* Module ID reg */
+#define GEM_OCTTXLO (0x00000100 / 4) /* Octects transmitted Low reg */
+#define GEM_OCTTXHI (0x00000104 / 4) /* Octects transmitted High reg */
+#define GEM_TXCNT (0x00000108 / 4) /* Error-free Frames transmitted */
+#define GEM_TXBCNT (0x0000010C / 4) /* Error-free Broadcast Frames */
+#define GEM_TXMCNT (0x00000110 / 4) /* Error-free Multicast Frame */
+#define GEM_TXPAUSECNT (0x00000114 / 4) /* Pause Frames Transmitted */
+#define GEM_TX64CNT (0x00000118 / 4) /* Error-free 64 TX */
+#define GEM_TX65CNT (0x0000011C / 4) /* Error-free 65-127 TX */
+#define GEM_TX128CNT (0x00000120 / 4) /* Error-free 128-255 TX */
+#define GEM_TX256CNT (0x00000124 / 4) /* Error-free 256-511 */
+#define GEM_TX512CNT (0x00000128 / 4) /* Error-free 512-1023 TX */
+#define GEM_TX1024CNT (0x0000012C / 4) /* Error-free 1024-1518 TX */
+#define GEM_TX1519CNT (0x00000130 / 4) /* Error-free larger than 1519 TX */
+#define GEM_TXURUNCNT (0x00000134 / 4) /* TX under run error counter */
+#define GEM_SINGLECOLLCNT (0x00000138 / 4) /* Single Collision Frames */
+#define GEM_MULTCOLLCNT (0x0000013C / 4) /* Multiple Collision Frames */
+#define GEM_EXCESSCOLLCNT (0x00000140 / 4) /* Excessive Collision Frames */
+#define GEM_LATECOLLCNT (0x00000144 / 4) /* Late Collision Frames */
+#define GEM_DEFERTXCNT (0x00000148 / 4) /* Deferred Transmission Frames */
+#define GEM_CSENSECNT (0x0000014C / 4) /* Carrier Sense Error Counter */
+#define GEM_OCTRXLO (0x00000150 / 4) /* Octects Received register Low */
+#define GEM_OCTRXHI (0x00000154 / 4) /* Octects Received register High */
+#define GEM_RXCNT (0x00000158 / 4) /* Error-free Frames Received */
+#define GEM_RXBROADCNT (0x0000015C / 4) /* Error-free Broadcast Frames RX */
+#define GEM_RXMULTICNT (0x00000160 / 4) /* Error-free Multicast Frames RX */
+#define GEM_RXPAUSECNT (0x00000164 / 4) /* Pause Frames Received Counter */
+#define GEM_RX64CNT (0x00000168 / 4) /* Error-free 64 byte Frames RX */
+#define GEM_RX65CNT (0x0000016C / 4) /* Error-free 65-127B Frames RX */
+#define GEM_RX128CNT (0x00000170 / 4) /* Error-free 128-255B Frames RX */
+#define GEM_RX256CNT (0x00000174 / 4) /* Error-free 256-512B Frames RX */
+#define GEM_RX512CNT (0x00000178 / 4) /* Error-free 512-1023B Frames RX */
+#define GEM_RX1024CNT (0x0000017C / 4) /* Error-free 1024-1518B Frames RX */
+#define GEM_RX1519CNT (0x00000180 / 4) /* Error-free 1519-max Frames RX */
+#define GEM_RXUNDERCNT (0x00000184 / 4) /* Undersize Frames Received */
+#define GEM_RXOVERCNT (0x00000188 / 4) /* Oversize Frames Received */
+#define GEM_RXJABCNT (0x0000018C / 4) /* Jabbers Received Counter */
+#define GEM_RXFCSCNT (0x00000190 / 4) /* Frame Check seq. Error Counter */
+#define GEM_RXLENERRCNT (0x00000194 / 4) /* Length Field Error Counter */
+#define GEM_RXSYMERRCNT (0x00000198 / 4) /* Symbol Error Counter */
+#define GEM_RXALIGNERRCNT (0x0000019C / 4) /* Alignment Error Counter */
+#define GEM_RXRSCERRCNT (0x000001A0 / 4) /* Receive Resource Error Counter */
+#define GEM_RXORUNCNT (0x000001A4 / 4) /* Receive Overrun Counter */
+#define GEM_RXIPCSERRCNT (0x000001A8 / 4) /* IP header Checksum Err Counter */
+#define GEM_RXTCPCCNT (0x000001AC / 4) /* TCP Checksum Error Counter */
+#define GEM_RXUDPCCNT (0x000001B0 / 4) /* UDP Checksum Error Counter */
+
+#define GEM_1588S (0x000001D0 / 4) /* 1588 Timer Seconds */
+#define GEM_1588NS (0x000001D4 / 4) /* 1588 Timer Nanoseconds */
+#define GEM_1588ADJ (0x000001D8 / 4) /* 1588 Timer Adjust */
+#define GEM_1588INC (0x000001DC / 4) /* 1588 Timer Increment */
+#define GEM_PTPETXS (0x000001E0 / 4) /* PTP Event Frame Transmitted (s) */
+#define GEM_PTPETXNS (0x000001E4 / 4) /*
+ * PTP Event Frame Transmitted (ns)
+ */
+#define GEM_PTPERXS (0x000001E8 / 4) /* PTP Event Frame Received (s) */
+#define GEM_PTPERXNS (0x000001EC / 4) /* PTP Event Frame Received (ns) */
+#define GEM_PTPPTXS (0x000001E0 / 4) /* PTP Peer Frame Transmitted (s) */
+#define GEM_PTPPTXNS (0x000001E4 / 4) /* PTP Peer Frame Transmitted (ns) */
+#define GEM_PTPPRXS (0x000001E8 / 4) /* PTP Peer Frame Received (s) */
+#define GEM_PTPPRXNS (0x000001EC / 4) /* PTP Peer Frame Received (ns) */
/* Design Configuration Registers */
-#define GEM_DESCONF (0x00000280/4)
-#define GEM_DESCONF2 (0x00000284/4)
-#define GEM_DESCONF3 (0x00000288/4)
-#define GEM_DESCONF4 (0x0000028C/4)
-#define GEM_DESCONF5 (0x00000290/4)
-#define GEM_DESCONF6 (0x00000294/4)
+#define GEM_DESCONF (0x00000280 / 4)
+#define GEM_DESCONF2 (0x00000284 / 4)
+#define GEM_DESCONF3 (0x00000288 / 4)
+#define GEM_DESCONF4 (0x0000028C / 4)
+#define GEM_DESCONF5 (0x00000290 / 4)
+#define GEM_DESCONF6 (0x00000294 / 4)
#define GEM_DESCONF6_64B_MASK (1U << 23)
-#define GEM_DESCONF7 (0x00000298/4)
+#define GEM_DESCONF7 (0x00000298 / 4)
#define GEM_INT_Q1_STATUS (0x00000400 / 4)
#define GEM_INT_Q1_MASK (0x00000640 / 4)
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v5 07/12] net: cadence_gem: Fix up code style
2020-05-12 14:54 ` [PATCH v5 07/12] net: cadence_gem: Fix up code style Sai Pavan Boddu
@ 2020-05-12 15:19 ` Edgar E. Iglesias
0 siblings, 0 replies; 17+ messages in thread
From: Edgar E. Iglesias @ 2020-05-12 15:19 UTC (permalink / raw)
To: Sai Pavan Boddu
Cc: Peter Maydell, Jason Wang, Markus Armbruster, qemu-devel,
qemu-arm, Tong Ho, Alistair Francis, Philippe Mathieu-Daudé,
Ramon Fried
On Tue, May 12, 2020 at 08:24:49PM +0530, Sai Pavan Boddu wrote:
> Fix the code style for register definitions.
>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> ---
> hw/net/cadence_gem.c | 204 ++++++++++++++++++++++++++-------------------------
> 1 file changed, 103 insertions(+), 101 deletions(-)
>
> diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
> index 11e36d0..f6ff27c 100644
> --- a/hw/net/cadence_gem.c
> +++ b/hw/net/cadence_gem.c
> @@ -43,110 +43,112 @@
> } \
> } while (0)
>
> -#define GEM_NWCTRL (0x00000000/4) /* Network Control reg */
> -#define GEM_NWCFG (0x00000004/4) /* Network Config reg */
> -#define GEM_NWSTATUS (0x00000008/4) /* Network Status reg */
> -#define GEM_USERIO (0x0000000C/4) /* User IO reg */
> -#define GEM_DMACFG (0x00000010/4) /* DMA Control reg */
> -#define GEM_TXSTATUS (0x00000014/4) /* TX Status reg */
> -#define GEM_RXQBASE (0x00000018/4) /* RX Q Base address reg */
> -#define GEM_TXQBASE (0x0000001C/4) /* TX Q Base address reg */
> -#define GEM_RXSTATUS (0x00000020/4) /* RX Status reg */
> -#define GEM_ISR (0x00000024/4) /* Interrupt Status reg */
> -#define GEM_IER (0x00000028/4) /* Interrupt Enable reg */
> -#define GEM_IDR (0x0000002C/4) /* Interrupt Disable reg */
> -#define GEM_IMR (0x00000030/4) /* Interrupt Mask reg */
> -#define GEM_PHYMNTNC (0x00000034/4) /* Phy Maintenance reg */
> -#define GEM_RXPAUSE (0x00000038/4) /* RX Pause Time reg */
> -#define GEM_TXPAUSE (0x0000003C/4) /* TX Pause Time reg */
> -#define GEM_TXPARTIALSF (0x00000040/4) /* TX Partial Store and Forward */
> -#define GEM_RXPARTIALSF (0x00000044/4) /* RX Partial Store and Forward */
> -#define GEM_HASHLO (0x00000080/4) /* Hash Low address reg */
> -#define GEM_HASHHI (0x00000084/4) /* Hash High address reg */
> -#define GEM_SPADDR1LO (0x00000088/4) /* Specific addr 1 low reg */
> -#define GEM_SPADDR1HI (0x0000008C/4) /* Specific addr 1 high reg */
> -#define GEM_SPADDR2LO (0x00000090/4) /* Specific addr 2 low reg */
> -#define GEM_SPADDR2HI (0x00000094/4) /* Specific addr 2 high reg */
> -#define GEM_SPADDR3LO (0x00000098/4) /* Specific addr 3 low reg */
> -#define GEM_SPADDR3HI (0x0000009C/4) /* Specific addr 3 high reg */
> -#define GEM_SPADDR4LO (0x000000A0/4) /* Specific addr 4 low reg */
> -#define GEM_SPADDR4HI (0x000000A4/4) /* Specific addr 4 high reg */
> -#define GEM_TIDMATCH1 (0x000000A8/4) /* Type ID1 Match reg */
> -#define GEM_TIDMATCH2 (0x000000AC/4) /* Type ID2 Match reg */
> -#define GEM_TIDMATCH3 (0x000000B0/4) /* Type ID3 Match reg */
> -#define GEM_TIDMATCH4 (0x000000B4/4) /* Type ID4 Match reg */
> -#define GEM_WOLAN (0x000000B8/4) /* Wake on LAN reg */
> -#define GEM_IPGSTRETCH (0x000000BC/4) /* IPG Stretch reg */
> -#define GEM_SVLAN (0x000000C0/4) /* Stacked VLAN reg */
> -#define GEM_MODID (0x000000FC/4) /* Module ID reg */
> -#define GEM_OCTTXLO (0x00000100/4) /* Octects transmitted Low reg */
> -#define GEM_OCTTXHI (0x00000104/4) /* Octects transmitted High reg */
> -#define GEM_TXCNT (0x00000108/4) /* Error-free Frames transmitted */
> -#define GEM_TXBCNT (0x0000010C/4) /* Error-free Broadcast Frames */
> -#define GEM_TXMCNT (0x00000110/4) /* Error-free Multicast Frame */
> -#define GEM_TXPAUSECNT (0x00000114/4) /* Pause Frames Transmitted */
> -#define GEM_TX64CNT (0x00000118/4) /* Error-free 64 TX */
> -#define GEM_TX65CNT (0x0000011C/4) /* Error-free 65-127 TX */
> -#define GEM_TX128CNT (0x00000120/4) /* Error-free 128-255 TX */
> -#define GEM_TX256CNT (0x00000124/4) /* Error-free 256-511 */
> -#define GEM_TX512CNT (0x00000128/4) /* Error-free 512-1023 TX */
> -#define GEM_TX1024CNT (0x0000012C/4) /* Error-free 1024-1518 TX */
> -#define GEM_TX1519CNT (0x00000130/4) /* Error-free larger than 1519 TX */
> -#define GEM_TXURUNCNT (0x00000134/4) /* TX under run error counter */
> -#define GEM_SINGLECOLLCNT (0x00000138/4) /* Single Collision Frames */
> -#define GEM_MULTCOLLCNT (0x0000013C/4) /* Multiple Collision Frames */
> -#define GEM_EXCESSCOLLCNT (0x00000140/4) /* Excessive Collision Frames */
> -#define GEM_LATECOLLCNT (0x00000144/4) /* Late Collision Frames */
> -#define GEM_DEFERTXCNT (0x00000148/4) /* Deferred Transmission Frames */
> -#define GEM_CSENSECNT (0x0000014C/4) /* Carrier Sense Error Counter */
> -#define GEM_OCTRXLO (0x00000150/4) /* Octects Received register Low */
> -#define GEM_OCTRXHI (0x00000154/4) /* Octects Received register High */
> -#define GEM_RXCNT (0x00000158/4) /* Error-free Frames Received */
> -#define GEM_RXBROADCNT (0x0000015C/4) /* Error-free Broadcast Frames RX */
> -#define GEM_RXMULTICNT (0x00000160/4) /* Error-free Multicast Frames RX */
> -#define GEM_RXPAUSECNT (0x00000164/4) /* Pause Frames Received Counter */
> -#define GEM_RX64CNT (0x00000168/4) /* Error-free 64 byte Frames RX */
> -#define GEM_RX65CNT (0x0000016C/4) /* Error-free 65-127B Frames RX */
> -#define GEM_RX128CNT (0x00000170/4) /* Error-free 128-255B Frames RX */
> -#define GEM_RX256CNT (0x00000174/4) /* Error-free 256-512B Frames RX */
> -#define GEM_RX512CNT (0x00000178/4) /* Error-free 512-1023B Frames RX */
> -#define GEM_RX1024CNT (0x0000017C/4) /* Error-free 1024-1518B Frames RX */
> -#define GEM_RX1519CNT (0x00000180/4) /* Error-free 1519-max Frames RX */
> -#define GEM_RXUNDERCNT (0x00000184/4) /* Undersize Frames Received */
> -#define GEM_RXOVERCNT (0x00000188/4) /* Oversize Frames Received */
> -#define GEM_RXJABCNT (0x0000018C/4) /* Jabbers Received Counter */
> -#define GEM_RXFCSCNT (0x00000190/4) /* Frame Check seq. Error Counter */
> -#define GEM_RXLENERRCNT (0x00000194/4) /* Length Field Error Counter */
> -#define GEM_RXSYMERRCNT (0x00000198/4) /* Symbol Error Counter */
> -#define GEM_RXALIGNERRCNT (0x0000019C/4) /* Alignment Error Counter */
> -#define GEM_RXRSCERRCNT (0x000001A0/4) /* Receive Resource Error Counter */
> -#define GEM_RXORUNCNT (0x000001A4/4) /* Receive Overrun Counter */
> -#define GEM_RXIPCSERRCNT (0x000001A8/4) /* IP header Checksum Error Counter */
> -#define GEM_RXTCPCCNT (0x000001AC/4) /* TCP Checksum Error Counter */
> -#define GEM_RXUDPCCNT (0x000001B0/4) /* UDP Checksum Error Counter */
> -
> -#define GEM_1588S (0x000001D0/4) /* 1588 Timer Seconds */
> -#define GEM_1588NS (0x000001D4/4) /* 1588 Timer Nanoseconds */
> -#define GEM_1588ADJ (0x000001D8/4) /* 1588 Timer Adjust */
> -#define GEM_1588INC (0x000001DC/4) /* 1588 Timer Increment */
> -#define GEM_PTPETXS (0x000001E0/4) /* PTP Event Frame Transmitted (s) */
> -#define GEM_PTPETXNS (0x000001E4/4) /* PTP Event Frame Transmitted (ns) */
> -#define GEM_PTPERXS (0x000001E8/4) /* PTP Event Frame Received (s) */
> -#define GEM_PTPERXNS (0x000001EC/4) /* PTP Event Frame Received (ns) */
> -#define GEM_PTPPTXS (0x000001E0/4) /* PTP Peer Frame Transmitted (s) */
> -#define GEM_PTPPTXNS (0x000001E4/4) /* PTP Peer Frame Transmitted (ns) */
> -#define GEM_PTPPRXS (0x000001E8/4) /* PTP Peer Frame Received (s) */
> -#define GEM_PTPPRXNS (0x000001EC/4) /* PTP Peer Frame Received (ns) */
> +#define GEM_NWCTRL (0x00000000 / 4) /* Network Control reg */
> +#define GEM_NWCFG (0x00000004 / 4) /* Network Config reg */
> +#define GEM_NWSTATUS (0x00000008 / 4) /* Network Status reg */
> +#define GEM_USERIO (0x0000000C / 4) /* User IO reg */
> +#define GEM_DMACFG (0x00000010 / 4) /* DMA Control reg */
> +#define GEM_TXSTATUS (0x00000014 / 4) /* TX Status reg */
> +#define GEM_RXQBASE (0x00000018 / 4) /* RX Q Base address reg */
> +#define GEM_TXQBASE (0x0000001C / 4) /* TX Q Base address reg */
> +#define GEM_RXSTATUS (0x00000020 / 4) /* RX Status reg */
> +#define GEM_ISR (0x00000024 / 4) /* Interrupt Status reg */
> +#define GEM_IER (0x00000028 / 4) /* Interrupt Enable reg */
> +#define GEM_IDR (0x0000002C / 4) /* Interrupt Disable reg */
> +#define GEM_IMR (0x00000030 / 4) /* Interrupt Mask reg */
> +#define GEM_PHYMNTNC (0x00000034 / 4) /* Phy Maintenance reg */
> +#define GEM_RXPAUSE (0x00000038 / 4) /* RX Pause Time reg */
> +#define GEM_TXPAUSE (0x0000003C / 4) /* TX Pause Time reg */
> +#define GEM_TXPARTIALSF (0x00000040 / 4) /* TX Partial Store and Forward */
> +#define GEM_RXPARTIALSF (0x00000044 / 4) /* RX Partial Store and Forward */
> +#define GEM_HASHLO (0x00000080 / 4) /* Hash Low address reg */
> +#define GEM_HASHHI (0x00000084 / 4) /* Hash High address reg */
> +#define GEM_SPADDR1LO (0x00000088 / 4) /* Specific addr 1 low reg */
> +#define GEM_SPADDR1HI (0x0000008C / 4) /* Specific addr 1 high reg */
> +#define GEM_SPADDR2LO (0x00000090 / 4) /* Specific addr 2 low reg */
> +#define GEM_SPADDR2HI (0x00000094 / 4) /* Specific addr 2 high reg */
> +#define GEM_SPADDR3LO (0x00000098 / 4) /* Specific addr 3 low reg */
> +#define GEM_SPADDR3HI (0x0000009C / 4) /* Specific addr 3 high reg */
> +#define GEM_SPADDR4LO (0x000000A0 / 4) /* Specific addr 4 low reg */
> +#define GEM_SPADDR4HI (0x000000A4 / 4) /* Specific addr 4 high reg */
> +#define GEM_TIDMATCH1 (0x000000A8 / 4) /* Type ID1 Match reg */
> +#define GEM_TIDMATCH2 (0x000000AC / 4) /* Type ID2 Match reg */
> +#define GEM_TIDMATCH3 (0x000000B0 / 4) /* Type ID3 Match reg */
> +#define GEM_TIDMATCH4 (0x000000B4 / 4) /* Type ID4 Match reg */
> +#define GEM_WOLAN (0x000000B8 / 4) /* Wake on LAN reg */
> +#define GEM_IPGSTRETCH (0x000000BC / 4) /* IPG Stretch reg */
> +#define GEM_SVLAN (0x000000C0 / 4) /* Stacked VLAN reg */
> +#define GEM_MODID (0x000000FC / 4) /* Module ID reg */
> +#define GEM_OCTTXLO (0x00000100 / 4) /* Octects transmitted Low reg */
> +#define GEM_OCTTXHI (0x00000104 / 4) /* Octects transmitted High reg */
> +#define GEM_TXCNT (0x00000108 / 4) /* Error-free Frames transmitted */
> +#define GEM_TXBCNT (0x0000010C / 4) /* Error-free Broadcast Frames */
> +#define GEM_TXMCNT (0x00000110 / 4) /* Error-free Multicast Frame */
> +#define GEM_TXPAUSECNT (0x00000114 / 4) /* Pause Frames Transmitted */
> +#define GEM_TX64CNT (0x00000118 / 4) /* Error-free 64 TX */
> +#define GEM_TX65CNT (0x0000011C / 4) /* Error-free 65-127 TX */
> +#define GEM_TX128CNT (0x00000120 / 4) /* Error-free 128-255 TX */
> +#define GEM_TX256CNT (0x00000124 / 4) /* Error-free 256-511 */
> +#define GEM_TX512CNT (0x00000128 / 4) /* Error-free 512-1023 TX */
> +#define GEM_TX1024CNT (0x0000012C / 4) /* Error-free 1024-1518 TX */
> +#define GEM_TX1519CNT (0x00000130 / 4) /* Error-free larger than 1519 TX */
> +#define GEM_TXURUNCNT (0x00000134 / 4) /* TX under run error counter */
> +#define GEM_SINGLECOLLCNT (0x00000138 / 4) /* Single Collision Frames */
> +#define GEM_MULTCOLLCNT (0x0000013C / 4) /* Multiple Collision Frames */
> +#define GEM_EXCESSCOLLCNT (0x00000140 / 4) /* Excessive Collision Frames */
> +#define GEM_LATECOLLCNT (0x00000144 / 4) /* Late Collision Frames */
> +#define GEM_DEFERTXCNT (0x00000148 / 4) /* Deferred Transmission Frames */
> +#define GEM_CSENSECNT (0x0000014C / 4) /* Carrier Sense Error Counter */
> +#define GEM_OCTRXLO (0x00000150 / 4) /* Octects Received register Low */
> +#define GEM_OCTRXHI (0x00000154 / 4) /* Octects Received register High */
> +#define GEM_RXCNT (0x00000158 / 4) /* Error-free Frames Received */
> +#define GEM_RXBROADCNT (0x0000015C / 4) /* Error-free Broadcast Frames RX */
> +#define GEM_RXMULTICNT (0x00000160 / 4) /* Error-free Multicast Frames RX */
> +#define GEM_RXPAUSECNT (0x00000164 / 4) /* Pause Frames Received Counter */
> +#define GEM_RX64CNT (0x00000168 / 4) /* Error-free 64 byte Frames RX */
> +#define GEM_RX65CNT (0x0000016C / 4) /* Error-free 65-127B Frames RX */
> +#define GEM_RX128CNT (0x00000170 / 4) /* Error-free 128-255B Frames RX */
> +#define GEM_RX256CNT (0x00000174 / 4) /* Error-free 256-512B Frames RX */
> +#define GEM_RX512CNT (0x00000178 / 4) /* Error-free 512-1023B Frames RX */
> +#define GEM_RX1024CNT (0x0000017C / 4) /* Error-free 1024-1518B Frames RX */
> +#define GEM_RX1519CNT (0x00000180 / 4) /* Error-free 1519-max Frames RX */
> +#define GEM_RXUNDERCNT (0x00000184 / 4) /* Undersize Frames Received */
> +#define GEM_RXOVERCNT (0x00000188 / 4) /* Oversize Frames Received */
> +#define GEM_RXJABCNT (0x0000018C / 4) /* Jabbers Received Counter */
> +#define GEM_RXFCSCNT (0x00000190 / 4) /* Frame Check seq. Error Counter */
> +#define GEM_RXLENERRCNT (0x00000194 / 4) /* Length Field Error Counter */
> +#define GEM_RXSYMERRCNT (0x00000198 / 4) /* Symbol Error Counter */
> +#define GEM_RXALIGNERRCNT (0x0000019C / 4) /* Alignment Error Counter */
> +#define GEM_RXRSCERRCNT (0x000001A0 / 4) /* Receive Resource Error Counter */
> +#define GEM_RXORUNCNT (0x000001A4 / 4) /* Receive Overrun Counter */
> +#define GEM_RXIPCSERRCNT (0x000001A8 / 4) /* IP header Checksum Err Counter */
> +#define GEM_RXTCPCCNT (0x000001AC / 4) /* TCP Checksum Error Counter */
> +#define GEM_RXUDPCCNT (0x000001B0 / 4) /* UDP Checksum Error Counter */
> +
> +#define GEM_1588S (0x000001D0 / 4) /* 1588 Timer Seconds */
> +#define GEM_1588NS (0x000001D4 / 4) /* 1588 Timer Nanoseconds */
> +#define GEM_1588ADJ (0x000001D8 / 4) /* 1588 Timer Adjust */
> +#define GEM_1588INC (0x000001DC / 4) /* 1588 Timer Increment */
> +#define GEM_PTPETXS (0x000001E0 / 4) /* PTP Event Frame Transmitted (s) */
> +#define GEM_PTPETXNS (0x000001E4 / 4) /*
> + * PTP Event Frame Transmitted (ns)
> + */
> +#define GEM_PTPERXS (0x000001E8 / 4) /* PTP Event Frame Received (s) */
> +#define GEM_PTPERXNS (0x000001EC / 4) /* PTP Event Frame Received (ns) */
> +#define GEM_PTPPTXS (0x000001E0 / 4) /* PTP Peer Frame Transmitted (s) */
> +#define GEM_PTPPTXNS (0x000001E4 / 4) /* PTP Peer Frame Transmitted (ns) */
> +#define GEM_PTPPRXS (0x000001E8 / 4) /* PTP Peer Frame Received (s) */
> +#define GEM_PTPPRXNS (0x000001EC / 4) /* PTP Peer Frame Received (ns) */
>
> /* Design Configuration Registers */
> -#define GEM_DESCONF (0x00000280/4)
> -#define GEM_DESCONF2 (0x00000284/4)
> -#define GEM_DESCONF3 (0x00000288/4)
> -#define GEM_DESCONF4 (0x0000028C/4)
> -#define GEM_DESCONF5 (0x00000290/4)
> -#define GEM_DESCONF6 (0x00000294/4)
> +#define GEM_DESCONF (0x00000280 / 4)
> +#define GEM_DESCONF2 (0x00000284 / 4)
> +#define GEM_DESCONF3 (0x00000288 / 4)
> +#define GEM_DESCONF4 (0x0000028C / 4)
> +#define GEM_DESCONF5 (0x00000290 / 4)
> +#define GEM_DESCONF6 (0x00000294 / 4)
> #define GEM_DESCONF6_64B_MASK (1U << 23)
> -#define GEM_DESCONF7 (0x00000298/4)
> +#define GEM_DESCONF7 (0x00000298 / 4)
>
> #define GEM_INT_Q1_STATUS (0x00000400 / 4)
> #define GEM_INT_Q1_MASK (0x00000640 / 4)
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v5 08/12] net: cadence_gem: Add support for jumbo frames
2020-05-12 14:54 [PATCH v5 00/12] Cadence GEM Fixes Sai Pavan Boddu
` (6 preceding siblings ...)
2020-05-12 14:54 ` [PATCH v5 07/12] net: cadence_gem: Fix up code style Sai Pavan Boddu
@ 2020-05-12 14:54 ` Sai Pavan Boddu
2020-05-12 15:19 ` Edgar E. Iglesias
2020-05-12 14:54 ` [PATCH v5 09/12] net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg Sai Pavan Boddu
` (4 subsequent siblings)
12 siblings, 1 reply; 17+ messages in thread
From: Sai Pavan Boddu @ 2020-05-12 14:54 UTC (permalink / raw)
To: Edgar E. Iglesias, Alistair Francis, Peter Maydell, Jason Wang,
Markus Armbruster, Philippe Mathieu-Daudé,
Tong Ho, Ramon Fried
Cc: qemu-arm, qemu-devel
Add a property "jumbo-max-len", which sets default value of jumbo frames
up to 16,383 bytes. Add Frame length checks for standard and jumbo
frames.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
---
hw/net/cadence_gem.c | 51 +++++++++++++++++++++++++++++++++++++++-----
include/hw/net/cadence_gem.h | 4 +++-
2 files changed, 49 insertions(+), 6 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index f6ff27c..eb02946 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -61,6 +61,7 @@
#define GEM_TXPAUSE (0x0000003C / 4) /* TX Pause Time reg */
#define GEM_TXPARTIALSF (0x00000040 / 4) /* TX Partial Store and Forward */
#define GEM_RXPARTIALSF (0x00000044 / 4) /* RX Partial Store and Forward */
+#define GEM_JUMBO_MAX_LEN (0x00000048 / 4) /* Max Jumbo Frame Size */
#define GEM_HASHLO (0x00000080 / 4) /* Hash Low address reg */
#define GEM_HASHHI (0x00000084 / 4) /* Hash High address reg */
#define GEM_SPADDR1LO (0x00000088 / 4) /* Specific addr 1 low reg */
@@ -212,10 +213,12 @@
#define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */
#define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */
#define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */
+#define GEM_NWCFG_RCV_1538 0x00000100 /* Receive 1538 bytes frame */
#define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */
#define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */
#define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */
#define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */
+#define GEM_NWCFG_JUMBO_FRAME 0x00000008 /* Jumbo Frames enable */
#define GEM_DMACFG_ADDR_64B (1U << 30)
#define GEM_DMACFG_TX_BD_EXT (1U << 29)
@@ -233,6 +236,7 @@
/* GEM_ISR GEM_IER GEM_IDR GEM_IMR */
#define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */
+#define GEM_INT_AMBA_ERR 0x00000040
#define GEM_INT_TXUSED 0x00000008
#define GEM_INT_RXUSED 0x00000004
#define GEM_INT_RXCMPL 0x00000002
@@ -453,6 +457,24 @@ static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx)
/* The broadcast MAC address: 0xFFFFFFFFFFFF */
static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
+static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx)
+{
+ uint32_t size;
+ if (s->regs[GEM_NWCFG] & GEM_NWCFG_JUMBO_FRAME) {
+ size = s->regs[GEM_JUMBO_MAX_LEN];
+ if (size > s->jumbo_max_len) {
+ size = s->jumbo_max_len;
+ qemu_log_mask(LOG_GUEST_ERROR, "GEM_JUMBO_MAX_LEN reg cannot be"
+ " greater than 0x%" PRIx32 "\n", s->jumbo_max_len);
+ }
+ } else if (tx) {
+ size = 1518;
+ } else {
+ size = s->regs[GEM_NWCFG] & GEM_NWCFG_RCV_1538 ? 1538 : 1518;
+ }
+ return size;
+}
+
static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag)
{
if (q == 0) {
@@ -1016,6 +1038,12 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
/* Find which queue we are targeting */
q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize);
+ if (size > gem_get_max_buf_len(s, false)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "rx frame too long\n");
+ gem_set_isr(s, q, GEM_INT_AMBA_ERR);
+ return -1;
+ }
+
while (bytes_to_copy) {
hwaddr desc_addr;
@@ -1196,12 +1224,13 @@ static void gem_transmit(CadenceGEMState *s)
break;
}
- if (tx_desc_get_length(desc) > MAX_FRAME_SIZE -
+ if (tx_desc_get_length(desc) > gem_get_max_buf_len(s, true) -
(p - s->tx_packet)) {
- DB_PRINT("TX descriptor @ 0x%" HWADDR_PRIx \
- " too large: size 0x%x space 0x%zx\n",
+ qemu_log_mask(LOG_GUEST_ERROR, "TX descriptor @ 0x%" \
+ HWADDR_PRIx " too large: size 0x%x space 0x%zx\n",
packet_desc_addr, tx_desc_get_length(desc),
- MAX_FRAME_SIZE - (p - s->tx_packet));
+ gem_get_max_buf_len(s, true) - (p - s->tx_packet));
+ gem_set_isr(s, q, GEM_INT_AMBA_ERR);
break;
}
@@ -1343,9 +1372,10 @@ static void gem_reset(DeviceState *d)
s->regs[GEM_RXPARTIALSF] = 0x000003ff;
s->regs[GEM_MODID] = s->revision;
s->regs[GEM_DESCONF] = 0x02500111;
- s->regs[GEM_DESCONF2] = 0x2ab13fff;
+ s->regs[GEM_DESCONF2] = 0x2ab10000 | s->jumbo_max_len;
s->regs[GEM_DESCONF5] = 0x002f2045;
s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK;
+ s->regs[GEM_JUMBO_MAX_LEN] = s->jumbo_max_len;
if (s->num_priority_queues > 1) {
queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1);
@@ -1516,6 +1546,9 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
s->regs[GEM_IMR] &= ~val;
gem_update_int_status(s);
break;
+ case GEM_JUMBO_MAX_LEN:
+ s->regs[GEM_JUMBO_MAX_LEN] = val & MAX_JUMBO_FRAME_SIZE_MASK;
+ break;
case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE:
s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &= ~val;
gem_update_int_status(s);
@@ -1610,6 +1643,12 @@ static void gem_realize(DeviceState *dev, Error **errp)
s->nic = qemu_new_nic(&net_gem_info, &s->conf,
object_get_typename(OBJECT(dev)), dev->id, s);
+
+ if (s->jumbo_max_len > MAX_FRAME_SIZE) {
+ error_setg(errp, "jumbo-max-len is greater than %d",
+ MAX_FRAME_SIZE);
+ return;
+ }
}
static void gem_init(Object *obj)
@@ -1659,6 +1698,8 @@ static Property gem_properties[] = {
num_type1_screeners, 4),
DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState,
num_type2_screeners, 4),
+ DEFINE_PROP_UINT16("jumbo-max-len", CadenceGEMState,
+ jumbo_max_len, 10240),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
index eddac70..54e646f 100644
--- a/include/hw/net/cadence_gem.h
+++ b/include/hw/net/cadence_gem.h
@@ -40,7 +40,8 @@
#define MAX_TYPE1_SCREENERS 16
#define MAX_TYPE2_SCREENERS 16
-#define MAX_FRAME_SIZE 2048
+#define MAX_JUMBO_FRAME_SIZE_MASK 0x3FFF
+#define MAX_FRAME_SIZE MAX_JUMBO_FRAME_SIZE_MASK
typedef struct CadenceGEMState {
/*< private >*/
@@ -59,6 +60,7 @@ typedef struct CadenceGEMState {
uint8_t num_type1_screeners;
uint8_t num_type2_screeners;
uint32_t revision;
+ uint16_t jumbo_max_len;
/* GEM registers backing store */
uint32_t regs[CADENCE_GEM_MAXREG];
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v5 08/12] net: cadence_gem: Add support for jumbo frames
2020-05-12 14:54 ` [PATCH v5 08/12] net: cadence_gem: Add support for jumbo frames Sai Pavan Boddu
@ 2020-05-12 15:19 ` Edgar E. Iglesias
2020-05-13 5:15 ` Sai Pavan Boddu
0 siblings, 1 reply; 17+ messages in thread
From: Edgar E. Iglesias @ 2020-05-12 15:19 UTC (permalink / raw)
To: Sai Pavan Boddu
Cc: Peter Maydell, Jason Wang, Markus Armbruster, qemu-devel,
qemu-arm, Tong Ho, Alistair Francis, Philippe Mathieu-Daudé,
Ramon Fried
On Tue, May 12, 2020 at 08:24:50PM +0530, Sai Pavan Boddu wrote:
> Add a property "jumbo-max-len", which sets default value of jumbo frames
> up to 16,383 bytes. Add Frame length checks for standard and jumbo
> frames.
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> ---
> hw/net/cadence_gem.c | 51 +++++++++++++++++++++++++++++++++++++++-----
> include/hw/net/cadence_gem.h | 4 +++-
> 2 files changed, 49 insertions(+), 6 deletions(-)
>
> diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
> index f6ff27c..eb02946 100644
> --- a/hw/net/cadence_gem.c
> +++ b/hw/net/cadence_gem.c
> @@ -61,6 +61,7 @@
> #define GEM_TXPAUSE (0x0000003C / 4) /* TX Pause Time reg */
> #define GEM_TXPARTIALSF (0x00000040 / 4) /* TX Partial Store and Forward */
> #define GEM_RXPARTIALSF (0x00000044 / 4) /* RX Partial Store and Forward */
> +#define GEM_JUMBO_MAX_LEN (0x00000048 / 4) /* Max Jumbo Frame Size */
> #define GEM_HASHLO (0x00000080 / 4) /* Hash Low address reg */
> #define GEM_HASHHI (0x00000084 / 4) /* Hash High address reg */
> #define GEM_SPADDR1LO (0x00000088 / 4) /* Specific addr 1 low reg */
> @@ -212,10 +213,12 @@
> #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */
> #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */
> #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */
> +#define GEM_NWCFG_RCV_1538 0x00000100 /* Receive 1538 bytes frame */
> #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */
> #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */
> #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */
> #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */
> +#define GEM_NWCFG_JUMBO_FRAME 0x00000008 /* Jumbo Frames enable */
>
> #define GEM_DMACFG_ADDR_64B (1U << 30)
> #define GEM_DMACFG_TX_BD_EXT (1U << 29)
> @@ -233,6 +236,7 @@
>
> /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */
> #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */
> +#define GEM_INT_AMBA_ERR 0x00000040
> #define GEM_INT_TXUSED 0x00000008
> #define GEM_INT_RXUSED 0x00000004
> #define GEM_INT_RXCMPL 0x00000002
> @@ -453,6 +457,24 @@ static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx)
> /* The broadcast MAC address: 0xFFFFFFFFFFFF */
> static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
>
> +static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx)
> +{
> + uint32_t size;
> + if (s->regs[GEM_NWCFG] & GEM_NWCFG_JUMBO_FRAME) {
> + size = s->regs[GEM_JUMBO_MAX_LEN];
> + if (size > s->jumbo_max_len) {
> + size = s->jumbo_max_len;
> + qemu_log_mask(LOG_GUEST_ERROR, "GEM_JUMBO_MAX_LEN reg cannot be"
> + " greater than 0x%" PRIx32 "\n", s->jumbo_max_len);
> + }
> + } else if (tx) {
> + size = 1518;
> + } else {
> + size = s->regs[GEM_NWCFG] & GEM_NWCFG_RCV_1538 ? 1538 : 1518;
> + }
> + return size;
> +}
> +
> static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag)
> {
> if (q == 0) {
> @@ -1016,6 +1038,12 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
> /* Find which queue we are targeting */
> q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize);
>
> + if (size > gem_get_max_buf_len(s, false)) {
> + qemu_log_mask(LOG_GUEST_ERROR, "rx frame too long\n");
> + gem_set_isr(s, q, GEM_INT_AMBA_ERR);
> + return -1;
> + }
> +
> while (bytes_to_copy) {
> hwaddr desc_addr;
>
> @@ -1196,12 +1224,13 @@ static void gem_transmit(CadenceGEMState *s)
> break;
> }
>
> - if (tx_desc_get_length(desc) > MAX_FRAME_SIZE -
> + if (tx_desc_get_length(desc) > gem_get_max_buf_len(s, true) -
> (p - s->tx_packet)) {
> - DB_PRINT("TX descriptor @ 0x%" HWADDR_PRIx \
> - " too large: size 0x%x space 0x%zx\n",
> + qemu_log_mask(LOG_GUEST_ERROR, "TX descriptor @ 0x%" \
> + HWADDR_PRIx " too large: size 0x%x space 0x%zx\n",
> packet_desc_addr, tx_desc_get_length(desc),
> - MAX_FRAME_SIZE - (p - s->tx_packet));
> + gem_get_max_buf_len(s, true) - (p - s->tx_packet));
> + gem_set_isr(s, q, GEM_INT_AMBA_ERR);
> break;
> }
>
> @@ -1343,9 +1372,10 @@ static void gem_reset(DeviceState *d)
> s->regs[GEM_RXPARTIALSF] = 0x000003ff;
> s->regs[GEM_MODID] = s->revision;
> s->regs[GEM_DESCONF] = 0x02500111;
> - s->regs[GEM_DESCONF2] = 0x2ab13fff;
> + s->regs[GEM_DESCONF2] = 0x2ab10000 | s->jumbo_max_len;
> s->regs[GEM_DESCONF5] = 0x002f2045;
> s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK;
> + s->regs[GEM_JUMBO_MAX_LEN] = s->jumbo_max_len;
>
> if (s->num_priority_queues > 1) {
> queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1);
> @@ -1516,6 +1546,9 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
> s->regs[GEM_IMR] &= ~val;
> gem_update_int_status(s);
> break;
> + case GEM_JUMBO_MAX_LEN:
> + s->regs[GEM_JUMBO_MAX_LEN] = val & MAX_JUMBO_FRAME_SIZE_MASK;
> + break;
> case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE:
> s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &= ~val;
> gem_update_int_status(s);
> @@ -1610,6 +1643,12 @@ static void gem_realize(DeviceState *dev, Error **errp)
>
> s->nic = qemu_new_nic(&net_gem_info, &s->conf,
> object_get_typename(OBJECT(dev)), dev->id, s);
> +
> + if (s->jumbo_max_len > MAX_FRAME_SIZE) {
> + error_setg(errp, "jumbo-max-len is greater than %d",
> + MAX_FRAME_SIZE);
> + return;
> + }
> }
>
> static void gem_init(Object *obj)
> @@ -1659,6 +1698,8 @@ static Property gem_properties[] = {
> num_type1_screeners, 4),
> DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState,
> num_type2_screeners, 4),
> + DEFINE_PROP_UINT16("jumbo-max-len", CadenceGEMState,
> + jumbo_max_len, 10240),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
> index eddac70..54e646f 100644
> --- a/include/hw/net/cadence_gem.h
> +++ b/include/hw/net/cadence_gem.h
> @@ -40,7 +40,8 @@
> #define MAX_TYPE1_SCREENERS 16
> #define MAX_TYPE2_SCREENERS 16
>
> -#define MAX_FRAME_SIZE 2048
> +#define MAX_JUMBO_FRAME_SIZE_MASK 0x3FFF
> +#define MAX_FRAME_SIZE MAX_JUMBO_FRAME_SIZE_MASK
>
> typedef struct CadenceGEMState {
> /*< private >*/
> @@ -59,6 +60,7 @@ typedef struct CadenceGEMState {
> uint8_t num_type1_screeners;
> uint8_t num_type2_screeners;
> uint32_t revision;
> + uint16_t jumbo_max_len;
>
> /* GEM registers backing store */
> uint32_t regs[CADENCE_GEM_MAXREG];
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 17+ messages in thread* RE: [PATCH v5 08/12] net: cadence_gem: Add support for jumbo frames
2020-05-12 15:19 ` Edgar E. Iglesias
@ 2020-05-13 5:15 ` Sai Pavan Boddu
0 siblings, 0 replies; 17+ messages in thread
From: Sai Pavan Boddu @ 2020-05-13 5:15 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: Peter Maydell, Jason Wang, Markus Armbruster, qemu-devel,
qemu-arm, Alistair Francis, Ramon Fried,
Philippe Mathieu-Daudé,
Tong Ho
Thanks for review edgar!
Regards,
Sai pavan
> -----Original Message-----
> From: Edgar E. Iglesias <edgar.iglesias@gmail.com>
> Sent: Tuesday, May 12, 2020 8:50 PM
> To: Sai Pavan Boddu <saipava@xilinx.com>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>; Peter Maydell
> <peter.maydell@linaro.org>; Jason Wang <jasowang@redhat.com>; Markus
> Armbruster <armbru@redhat.com>; Philippe Mathieu-Daudé
> <philmd@redhat.com>; Tong Ho <tongh@xilinx.com>; Ramon Fried
> <rfried.dev@gmail.com>; qemu-arm@nongnu.org; qemu-
> devel@nongnu.org
> Subject: Re: [PATCH v5 08/12] net: cadence_gem: Add support for jumbo
> frames
>
> On Tue, May 12, 2020 at 08:24:50PM +0530, Sai Pavan Boddu wrote:
> > Add a property "jumbo-max-len", which sets default value of jumbo
> > frames up to 16,383 bytes. Add Frame length checks for standard and
> > jumbo frames.
>
> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>
>
>
> >
> > Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> > ---
> > hw/net/cadence_gem.c | 51
> +++++++++++++++++++++++++++++++++++++++-----
> > include/hw/net/cadence_gem.h | 4 +++-
> > 2 files changed, 49 insertions(+), 6 deletions(-)
> >
> > diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
> > f6ff27c..eb02946 100644
> > --- a/hw/net/cadence_gem.c
> > +++ b/hw/net/cadence_gem.c
> > @@ -61,6 +61,7 @@
> > #define GEM_TXPAUSE (0x0000003C / 4) /* TX Pause Time reg */
> > #define GEM_TXPARTIALSF (0x00000040 / 4) /* TX Partial Store and
> Forward */
> > #define GEM_RXPARTIALSF (0x00000044 / 4) /* RX Partial Store and
> Forward */
> > +#define GEM_JUMBO_MAX_LEN (0x00000048 / 4) /* Max Jumbo Frame
> Size */
> > #define GEM_HASHLO (0x00000080 / 4) /* Hash Low address reg */
> > #define GEM_HASHHI (0x00000084 / 4) /* Hash High address reg */
> > #define GEM_SPADDR1LO (0x00000088 / 4) /* Specific addr 1 low reg */
> > @@ -212,10 +213,12 @@
> > #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with
> len err */
> > #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer
> offset mask */
> > #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift
> */
> > +#define GEM_NWCFG_RCV_1538 0x00000100 /* Receive 1538 bytes
> frame */
> > #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash
> match */
> > #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if
> hash match */
> > #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast
> packets */
> > #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */
> > +#define GEM_NWCFG_JUMBO_FRAME 0x00000008 /* Jumbo Frames
> enable */
> >
> > #define GEM_DMACFG_ADDR_64B (1U << 30)
> > #define GEM_DMACFG_TX_BD_EXT (1U << 29)
> > @@ -233,6 +236,7 @@
> >
> > /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */
> > #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */
> > +#define GEM_INT_AMBA_ERR 0x00000040
> > #define GEM_INT_TXUSED 0x00000008
> > #define GEM_INT_RXUSED 0x00000004
> > #define GEM_INT_RXCMPL 0x00000002
> > @@ -453,6 +457,24 @@ static inline void rx_desc_set_sar(uint32_t
> > *desc, int sar_idx)
> > /* The broadcast MAC address: 0xFFFFFFFFFFFF */ static const uint8_t
> > broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
> >
> > +static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx) {
> > + uint32_t size;
> > + if (s->regs[GEM_NWCFG] & GEM_NWCFG_JUMBO_FRAME) {
> > + size = s->regs[GEM_JUMBO_MAX_LEN];
> > + if (size > s->jumbo_max_len) {
> > + size = s->jumbo_max_len;
> > + qemu_log_mask(LOG_GUEST_ERROR, "GEM_JUMBO_MAX_LEN
> reg cannot be"
> > + " greater than 0x%" PRIx32 "\n", s->jumbo_max_len);
> > + }
> > + } else if (tx) {
> > + size = 1518;
> > + } else {
> > + size = s->regs[GEM_NWCFG] & GEM_NWCFG_RCV_1538 ? 1538 :
> 1518;
> > + }
> > + return size;
> > +}
> > +
> > static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag) {
> > if (q == 0) {
> > @@ -1016,6 +1038,12 @@ static ssize_t gem_receive(NetClientState *nc,
> const uint8_t *buf, size_t size)
> > /* Find which queue we are targeting */
> > q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize);
> >
> > + if (size > gem_get_max_buf_len(s, false)) {
> > + qemu_log_mask(LOG_GUEST_ERROR, "rx frame too long\n");
> > + gem_set_isr(s, q, GEM_INT_AMBA_ERR);
> > + return -1;
> > + }
> > +
> > while (bytes_to_copy) {
> > hwaddr desc_addr;
> >
> > @@ -1196,12 +1224,13 @@ static void gem_transmit(CadenceGEMState
> *s)
> > break;
> > }
> >
> > - if (tx_desc_get_length(desc) > MAX_FRAME_SIZE -
> > + if (tx_desc_get_length(desc) > gem_get_max_buf_len(s,
> > + true) -
> > (p - s->tx_packet)) {
> > - DB_PRINT("TX descriptor @ 0x%" HWADDR_PRIx \
> > - " too large: size 0x%x space 0x%zx\n",
> > + qemu_log_mask(LOG_GUEST_ERROR, "TX descriptor @ 0x%" \
> > + HWADDR_PRIx " too large: size 0x%x space
> > + 0x%zx\n",
> > packet_desc_addr, tx_desc_get_length(desc),
> > - MAX_FRAME_SIZE - (p - s->tx_packet));
> > + gem_get_max_buf_len(s, true) - (p - s->tx_packet));
> > + gem_set_isr(s, q, GEM_INT_AMBA_ERR);
> > break;
> > }
> >
> > @@ -1343,9 +1372,10 @@ static void gem_reset(DeviceState *d)
> > s->regs[GEM_RXPARTIALSF] = 0x000003ff;
> > s->regs[GEM_MODID] = s->revision;
> > s->regs[GEM_DESCONF] = 0x02500111;
> > - s->regs[GEM_DESCONF2] = 0x2ab13fff;
> > + s->regs[GEM_DESCONF2] = 0x2ab10000 | s->jumbo_max_len;
> > s->regs[GEM_DESCONF5] = 0x002f2045;
> > s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK;
> > + s->regs[GEM_JUMBO_MAX_LEN] = s->jumbo_max_len;
> >
> > if (s->num_priority_queues > 1) {
> > queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1);
> > @@ -1516,6 +1546,9 @@ static void gem_write(void *opaque, hwaddr
> offset, uint64_t val,
> > s->regs[GEM_IMR] &= ~val;
> > gem_update_int_status(s);
> > break;
> > + case GEM_JUMBO_MAX_LEN:
> > + s->regs[GEM_JUMBO_MAX_LEN] = val &
> MAX_JUMBO_FRAME_SIZE_MASK;
> > + break;
> > case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE:
> > s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &=
> ~val;
> > gem_update_int_status(s);
> > @@ -1610,6 +1643,12 @@ static void gem_realize(DeviceState *dev, Error
> > **errp)
> >
> > s->nic = qemu_new_nic(&net_gem_info, &s->conf,
> > object_get_typename(OBJECT(dev)), dev->id,
> > s);
> > +
> > + if (s->jumbo_max_len > MAX_FRAME_SIZE) {
> > + error_setg(errp, "jumbo-max-len is greater than %d",
> > + MAX_FRAME_SIZE);
> > + return;
> > + }
> > }
> >
> > static void gem_init(Object *obj)
> > @@ -1659,6 +1698,8 @@ static Property gem_properties[] = {
> > num_type1_screeners, 4),
> > DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState,
> > num_type2_screeners, 4),
> > + DEFINE_PROP_UINT16("jumbo-max-len", CadenceGEMState,
> > + jumbo_max_len, 10240),
> > DEFINE_PROP_END_OF_LIST(),
> > };
> >
> > diff --git a/include/hw/net/cadence_gem.h
> > b/include/hw/net/cadence_gem.h index eddac70..54e646f 100644
> > --- a/include/hw/net/cadence_gem.h
> > +++ b/include/hw/net/cadence_gem.h
> > @@ -40,7 +40,8 @@
> > #define MAX_TYPE1_SCREENERS 16
> > #define MAX_TYPE2_SCREENERS 16
> >
> > -#define MAX_FRAME_SIZE 2048
> > +#define MAX_JUMBO_FRAME_SIZE_MASK 0x3FFF #define
> MAX_FRAME_SIZE
> > +MAX_JUMBO_FRAME_SIZE_MASK
> >
> > typedef struct CadenceGEMState {
> > /*< private >*/
> > @@ -59,6 +60,7 @@ typedef struct CadenceGEMState {
> > uint8_t num_type1_screeners;
> > uint8_t num_type2_screeners;
> > uint32_t revision;
> > + uint16_t jumbo_max_len;
> >
> > /* GEM registers backing store */
> > uint32_t regs[CADENCE_GEM_MAXREG];
> > --
> > 2.7.4
> >
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v5 09/12] net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg
2020-05-12 14:54 [PATCH v5 00/12] Cadence GEM Fixes Sai Pavan Boddu
` (7 preceding siblings ...)
2020-05-12 14:54 ` [PATCH v5 08/12] net: cadence_gem: Add support for jumbo frames Sai Pavan Boddu
@ 2020-05-12 14:54 ` Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 10/12] net: cadence_gem: Update the reset value for interrupt mask register Sai Pavan Boddu
` (3 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Sai Pavan Boddu @ 2020-05-12 14:54 UTC (permalink / raw)
To: Edgar E. Iglesias, Alistair Francis, Peter Maydell, Jason Wang,
Markus Armbruster, Philippe Mathieu-Daudé,
Tong Ho, Ramon Fried
Cc: qemu-arm, qemu-devel
Advertise support of clear-on-read for ISR registers.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
hw/net/cadence_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index eb02946..3e7b32f 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1371,7 +1371,7 @@ static void gem_reset(DeviceState *d)
s->regs[GEM_TXPARTIALSF] = 0x000003ff;
s->regs[GEM_RXPARTIALSF] = 0x000003ff;
s->regs[GEM_MODID] = s->revision;
- s->regs[GEM_DESCONF] = 0x02500111;
+ s->regs[GEM_DESCONF] = 0x02D00111;
s->regs[GEM_DESCONF2] = 0x2ab10000 | s->jumbo_max_len;
s->regs[GEM_DESCONF5] = 0x002f2045;
s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK;
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 10/12] net: cadence_gem: Update the reset value for interrupt mask register
2020-05-12 14:54 [PATCH v5 00/12] Cadence GEM Fixes Sai Pavan Boddu
` (8 preceding siblings ...)
2020-05-12 14:54 ` [PATCH v5 09/12] net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg Sai Pavan Boddu
@ 2020-05-12 14:54 ` Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 11/12] net: cadence_gem: TX_LAST bit should be set by guest Sai Pavan Boddu
` (2 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Sai Pavan Boddu @ 2020-05-12 14:54 UTC (permalink / raw)
To: Edgar E. Iglesias, Alistair Francis, Peter Maydell, Jason Wang,
Markus Armbruster, Philippe Mathieu-Daudé,
Tong Ho, Ramon Fried
Cc: qemu-arm, qemu-devel
Mask all interrupt on reset.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
hw/net/cadence_gem.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 3e7b32f..ddb8938 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1375,6 +1375,7 @@ static void gem_reset(DeviceState *d)
s->regs[GEM_DESCONF2] = 0x2ab10000 | s->jumbo_max_len;
s->regs[GEM_DESCONF5] = 0x002f2045;
s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK;
+ s->regs[GEM_INT_Q1_MASK] = 0x00000CE6;
s->regs[GEM_JUMBO_MAX_LEN] = s->jumbo_max_len;
if (s->num_priority_queues > 1) {
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 11/12] net: cadence_gem: TX_LAST bit should be set by guest
2020-05-12 14:54 [PATCH v5 00/12] Cadence GEM Fixes Sai Pavan Boddu
` (9 preceding siblings ...)
2020-05-12 14:54 ` [PATCH v5 10/12] net: cadence_gem: Update the reset value for interrupt mask register Sai Pavan Boddu
@ 2020-05-12 14:54 ` Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 12/12] net: cadence_gem: Fix RX address filtering Sai Pavan Boddu
2020-05-14 6:47 ` [PATCH v5 00/12] Cadence GEM Fixes Jason Wang
12 siblings, 0 replies; 17+ messages in thread
From: Sai Pavan Boddu @ 2020-05-12 14:54 UTC (permalink / raw)
To: Edgar E. Iglesias, Alistair Francis, Peter Maydell, Jason Wang,
Markus Armbruster, Philippe Mathieu-Daudé,
Tong Ho, Ramon Fried
Cc: qemu-arm, qemu-devel
TX_LAST bit should not be set by hardware, its set by guest to inform
the last bd of the frame.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
hw/net/cadence_gem.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index ddb8938..57d94a5 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -350,11 +350,6 @@ static inline unsigned tx_desc_get_last(uint32_t *desc)
return (desc[1] & DESC_1_TX_LAST) ? 1 : 0;
}
-static inline void tx_desc_set_last(uint32_t *desc)
-{
- desc[1] |= DESC_1_TX_LAST;
-}
-
static inline unsigned tx_desc_get_length(uint32_t *desc)
{
return desc[1] & DESC_1_LENGTH;
@@ -1298,7 +1293,6 @@ static void gem_transmit(CadenceGEMState *s)
/* read next descriptor */
if (tx_desc_get_wrap(desc)) {
- tx_desc_set_last(desc);
if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
packet_desc_addr = s->regs[GEM_TBQPH];
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 12/12] net: cadence_gem: Fix RX address filtering
2020-05-12 14:54 [PATCH v5 00/12] Cadence GEM Fixes Sai Pavan Boddu
` (10 preceding siblings ...)
2020-05-12 14:54 ` [PATCH v5 11/12] net: cadence_gem: TX_LAST bit should be set by guest Sai Pavan Boddu
@ 2020-05-12 14:54 ` Sai Pavan Boddu
2020-05-14 6:47 ` [PATCH v5 00/12] Cadence GEM Fixes Jason Wang
12 siblings, 0 replies; 17+ messages in thread
From: Sai Pavan Boddu @ 2020-05-12 14:54 UTC (permalink / raw)
To: Edgar E. Iglesias, Alistair Francis, Peter Maydell, Jason Wang,
Markus Armbruster, Philippe Mathieu-Daudé,
Tong Ho, Ramon Fried
Cc: qemu-arm, qemu-devel
From: Tong Ho <tong.ho@xilinx.com>
Two defects are fixed:
1/ Detection of multicast frames
2/ Treating drop of mis-addressed frames as non-error
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
hw/net/cadence_gem.c | 26 +++++++++++---------------
1 file changed, 11 insertions(+), 15 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 57d94a5..71d42b8 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -34,6 +34,7 @@
#include "qemu/module.h"
#include "sysemu/dma.h"
#include "net/checksum.h"
+#include "net/eth.h"
#define CADENCE_GEM_ERR_DEBUG 0
#define DB_PRINT(...) do {\
@@ -702,7 +703,7 @@ static unsigned calc_mac_hash(const uint8_t *mac)
static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
{
uint8_t *gem_spaddr;
- int i;
+ int i, is_mc;
/* Promiscuous mode? */
if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) {
@@ -718,22 +719,17 @@ static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
}
/* Accept packets -w- hash match? */
- if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) ||
- (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) {
+ is_mc = is_multicast_ether_addr(packet);
+ if ((is_mc && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) ||
+ (!is_mc && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) {
+ uint64_t buckets;
unsigned hash_index;
hash_index = calc_mac_hash(packet);
- if (hash_index < 32) {
- if (s->regs[GEM_HASHLO] & (1<<hash_index)) {
- return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT :
- GEM_RX_UNICAST_HASH_ACCEPT;
- }
- } else {
- hash_index -= 32;
- if (s->regs[GEM_HASHHI] & (1<<hash_index)) {
- return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT :
- GEM_RX_UNICAST_HASH_ACCEPT;
- }
+ buckets = ((uint64_t)s->regs[GEM_HASHHI] << 32) | s->regs[GEM_HASHLO];
+ if ((buckets >> hash_index) & 1) {
+ return is_mc ? GEM_RX_MULTICAST_HASH_ACCEPT
+ : GEM_RX_UNICAST_HASH_ACCEPT;
}
}
@@ -958,7 +954,7 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
/* Is this destination MAC address "for us" ? */
maf = gem_mac_address_filter(s, buf);
if (maf == GEM_RX_REJECT) {
- return -1;
+ return size; /* no, drop siliently b/c it's not an error */
}
/* Discard packets with receive length error enabled ? */
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v5 00/12] Cadence GEM Fixes
2020-05-12 14:54 [PATCH v5 00/12] Cadence GEM Fixes Sai Pavan Boddu
` (11 preceding siblings ...)
2020-05-12 14:54 ` [PATCH v5 12/12] net: cadence_gem: Fix RX address filtering Sai Pavan Boddu
@ 2020-05-14 6:47 ` Jason Wang
12 siblings, 0 replies; 17+ messages in thread
From: Jason Wang @ 2020-05-14 6:47 UTC (permalink / raw)
To: Sai Pavan Boddu, Edgar E. Iglesias, Alistair Francis,
Peter Maydell, Markus Armbruster, Philippe Mathieu-Daudé,
Tong Ho, Ramon Fried
Cc: qemu-arm, qemu-devel
On 2020/5/12 下午10:54, Sai Pavan Boddu wrote:
> Hi,
>
> Following patch series fixes issues with priority queues,
> Adds JUMBO Frame support,
> Makes Debug statements compilable &
> Fixes related to multicast frames.
>
> Changes for V2:
> Fixed build failure on fedora docker machine
> Fix buggy debug print to use sized integer casting
> Changes for V3:
> 1/10: Fixed debug statments to use %u and %zd
> Remove rxoffset for buffer address
> 2/10: Add inline functions to get tx/rx queue base address.
> 4/10: fix read only mask
> 5/10: Move packet buffers to CadenceGEMState
> 6/10: Add JUMBO MAX LEN register
> Changes for V4:
> 7/11: Fix up the existing code style in register defines
> 8/11: jumbo-max-len property sets the default value of jumbo frame
> Add frame lenght checks for tx and rx
> Changes for V5:
> 8/11: Add a cap on jumbo frame size and print guest errors if exceeded.
> Move jumo_max_len property into static properties section.
>
> Sai Pavan Boddu (11):
> net: cadence_gem: Fix debug statements
> net: cadence_gem: Fix the queue address update during wrap around
> net: cadence_gem: Fix irq update w.r.t queue
> net: cadence_gem: Define access permission for interrupt registers
> net: cadence_gem: Set ISR according to queue in use
> net: cadence_gem: Move tx/rx packet buffert to CadenceGEMState
> net: cadence_gem: Fix up code style
> net: cadence_gem: Add support for jumbo frames
> net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg
> net: cadence_gem: Update the reset value for interrupt mask register
> net: cadence_gem: TX_LAST bit should be set by guest
>
> Tong Ho (1):
> net: cadence_gem: Fix RX address filtering
>
> hw/net/cadence_gem.c | 458 ++++++++++++++++++++++++-------------------
> include/hw/net/cadence_gem.h | 6 +
> 2 files changed, 265 insertions(+), 199 deletions(-)
>
Applied.
Thanks
^ permalink raw reply [flat|nested] 17+ messages in thread